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101 innovation drive san jose, ca 95134 www.altera.com stratix ii device handbook, volume 1 sii5v1-4.5
copyright ? 2011 altera corporation. all righ ts reserved. altera, the programmable solu tions company, the stylized altera logo, specific device des- ignations, and all other words and logos that are identified as tr ademarks and/or service marks ar e, unless noted otherwise, th e trademarks and service marks of altera corporation in the u.s. and other countries. all other product or service names are the property of the ir respective holders. al- tera products are protected under numerous u.s. and foreign patents and pending app lications, maskwork rights, and copyrights. altera warrants performance of its semiconductor products to current specifications in accordance with altera's standard warranty, but reserves the right to make changes to any products and services at any time with out notice. altera assumes no responsibility or liabil- ity arising out of the application or use of any information, produc t, or service described herein except as expressly agreed to in writing by al tera corporation. altera customers are advised to obtain the latest ver- sion of device specifications before relying on an y published information and before placing orders for products or services . ii altera corporation
altera corporation iii contents chapter revision dates .......................................................................... vii about this handbook ................................................................................ i how to contact altera .......................................................................................................... ..................... i typographic conventions ........................................................................................................ ................. i section i. stratix ii devi ce family data sheet revision history ............................................................................................................... ........ section i?1 chapter 1. introduction introduction ................................................................................................................... ......................... 1?1 features ....................................................................................................................... ............................ 1?1 document revision history ...................................................................................................... ........... 1?6 chapter 2. stratix ii architecture functional description ......................................................................................................... ................. 2?1 logic array blocks ............................................................................................................. ................... 2?3 lab interconnects .............................................................................................................. .............. 2?4 lab control signals ............................................................................................................ ............. 2?5 adaptive logic modules ......................................................................................................... ............. 2?6 alm operating modes ............................................................................................................ ....... 2?9 register chain ................................................................................................................. ................ 2?20 clear & preset logic control ................................................................................................... ..... 2?22 multitrack interconnect ........................................................................................................ ............. 2?22 trimatrix memory ............................................................................................................... ................ 2?28 memory block size .............................................................................................................. ........... 2?29 digital signal processing block ................................................................................................ ......... 2?40 modes of operation ............................................................................................................. .......... 2?44 dsp block interface ............................................................................................................ ............ 2?44 plls & clock networks .......................................................................................................... ........... 2?48 global & hierarchical clocking ................................................................................................. .. 2?48 enhanced & fast plls ........................................................................................................... ........ 2?57 enhanced plls .................................................................................................................. ............. 2?68 fast plls ...................................................................................................................... .................... 2?69 i/o structure .................................................................................................................. ........... ........... 2?69 double data rate i/o pins .................................... .................................................................. ..... 2?77 external ram interfacing ....................................................................................................... ...... 2?81 programmable drive strength .................................................................................................... .2?83
iv altera corporation contents stratix ii device handbook, volume 1 open-drain output .............................................................................................................. .......... 2?84 bus hold ....................................................................................................................... ................... 2?84 programmable pull-up resistor .................................................................................................. 2?85 advanced i/o standard support ................................................................................................ 2? 85 on-chip termination ............................................................................................................ ........ 2?89 multivolt i/o interface ........................................................................................................ ......... 2?93 high-speed differential i/o with dpa su pport ................ ........... ............ ........... ........... ......... ...... 2?96 dedicated circuitry with dpa support ........ ............ ........... ........... ........... ......... ......... ............. 2?100 fast pll & channel layout ...................................................................................................... .. 2?102 document revision history ...................................................................................................... ....... 2?104 chapter 3. configuration & testing ieee std. 1149.1 jtag boundary -scan support ...... ........... ........... ............ ........... ........... ........... ...... 3?1 signaltap ii embedded logic analyzer ........................................................................................... . 3?4 configuration .................................................................................................................. ....................... 3?4 operating modes ................................................................................................................ .............. 3?5 configuration schemes .......................................................................................................... ......... 3?7 configuring stratix ii fpgas with jrunner ................... ............................................................ 3?10 programming serial configuration de vices with srunner ..................................................... 3?10 configuring stratix ii fpgas with the microblaster driver ................................................... 3?11 pll reconfiguration ............................................................................................................ .......... 3?11 temperature sensing diode (tsd) ................................................................................................ ... 3?11 automated single event upset (seu) dete ction ............ ........... ........... ........... ........... ............ ........ 3?13 custom-built circuitry ......................................................................................................... ......... 3?14 software interface ............................................................................................................. .............. 3?14 document revision history ...................................................................................................... ......... 3?14 chapter 4. hot socketing & power-on reset stratix ii hot-socketing specifications ................................................................................................... ............ 4?1 devices can be driven before power-up ...................... .............................................................. 4?2 i/o pins remain tri-stated during power-up ........................................................................... 4?2 signal pins do not drive the v ccio , v ccint or v ccpd power supplies .................................... 4?2 hot socketing feature implementation in stratix ii devi ces .......................................................... 4?3 power-on reset circuitry ....................................... ................................................................ ............. 4?5 document revision history ...................................................................................................... ........... 4?6 chapter 5. dc & switching characteristics operating conditions ........................................................................................................... ................ 5?1 absolute maximum ratings ....................................................................................................... .... 5?1 recommended operating conditions ........ .................................................................................. 5?2 dc electrical characteristics .................................................................................................. ........ 5?3 i/o standard specifications .................................................................................................... ....... 5?4 bus hold specifications ........................................................................................................ ......... 5?17 on-chip termination specifications ............................. .............................................................. 5? 17 pin capacitance ................................................................................................................ .............. 5?19 power consumption .............................................................................................................. ............. 5?20
altera corporation v contents contents timing model ................................................................................................................... ............ ........ 5?20 preliminary & final timing ..................................................................................................... ..... 5?20 i/o timing measurement methodology .................................................................................... 5?21 performance .................................................................................................................... ................ 5?27 internal timing parameters ..................................................................................................... ..... 5?34 stratix ii clock timing parameters .............................................................................................. 5?41 clock network skew adders ...................................................................................................... .5?50 ioe programmable delay ......................................................................................................... .... 5?51 default capacitive loading of different i/o standards . ......................................................... 5?52 i/o delays ..................................................................................................................... .................. 5?54 maximum input & output clock toggle rate .......................................................................... 5?66 duty cycle distortion .......................................................................................................... ......... ...... 5?77 dcd measurement techniques ................................................................................................... 5? 78 high-speed i/o specifications .................................................................................................. ........ 5?87 pll timing specifications ...................................................................................................... ............ 5?91 external memory interfac e specifications ....................................................................................... 5?94 jtag timing specifications ..................................................................................................... .......... 5?96 document revision history ...................................................................................................... ......... 5?97 chapter 6. reference & ordering information software ....................................................................................................................... ........................... 6?1 device pin-outs ................................................................................................................ ..................... 6?1 ordering information ........................................................................................................... ................ 6?1 document revision history ...................................................................................................... ........... 6?2
vi altera corporation contents stratix ii device handbook, volume 1
altera corporation vii chapter revision dates the chapters in this book, stratix ii device handbook, volume 1 , were revised on the following dates. where chapters or groups of chapters are av ailable separately, part numbers are listed. chapter 1. introduction revised: may 2007 part number: sii51001-4.2 chapter 2. stratix ii architecture revised: may 2007 part number: sii51002-4.3 chapter 3. configuration & testing revised: may 2007 part number: sii51003-4.2 chapter 4. hot socketing & power-on reset revised: may 2007 part number: sii51004-3.2 chapter 5. dc & switching characteristics revised: april 2011 part number: sii51005-4.5 chapter 6. reference & ordering information revised: april 2011 part number: sii51006-2.2
viii altera corporation chapter revision dates stratix ii device handbook, volume 1
altera corporation i preliminary about this handbook this handbook provides comprehe nsive information about the altera ? stratix ? ii family of devices. how to contact altera for the most up-to-date information about altera products, refer to the following table. typographic conventions this document uses the typogr aphic conventions shown below. contact (1) contact method address technical support website www.altera.com/support technical training website www.altera.com/training email custrain@altera.com product literature email www.altera.com/literature altera literature services website literature@altera.com non-technical support (general) (software licensing) email nacomp@altera.com email authorization@altera.com note to table: (1) you can also contact your local altera sales office or sales representative. visual cue meaning bold type with initial capital letters command names, dialog box titles, checkbox options, and dialog box options are shown in bold, initial capital letters. example: save as dialog box. bold type external timing parameters, directory names, project names, disk drive names, filenames, filename extensions, and softw are utility names are shown in bold type. examples: f max , \qdesigns directory, d: drive, chiptrip.gdf file. italic type with initial capital letters document titles are shown in italic ty pe with initial capital letters. example: an 75: high-speed board design.
ii altera corporation preliminary typographic conventions stratix ii device handbook, volume 1 italic type internal timing parameters and variables are shown in italic type. examples: t pia , n + 1. variable names are enclosed in angle br ackets (< >) and shown in italic type. example: , .pof file. initial capital letters keyboard keys and menu names ar e shown with initial capital letters. examples: delete key, the options menu. ?subheading title? references to sections within a document and titles of on-line help topics are shown in quotation marks. example: ?typographic conventions.? courier type signal and port names are shown in lowercase courier type. examples: data1 , tdi , input. active-low signals are denoted by suffix n , e.g., resetn . anything that must be typed exactly as it appears is shown in courier type. for example: c:\qdesigns\tutorial\chiptrip.gdf . also, sections of an actual file, such as a report file, refere nces to parts of files (e.g., the ahdl keyword subdesign ), as well as logic function names (e.g., tri ) are shown in courier. 1., 2., 3., and a., b., c., etc. numbered steps are used in a list of items when the sequence of the items is important, such as the steps listed in a procedure. ? bullets are used in a list of items when the sequence of the items is not important. v the checkmark indicates a procedur e that consists of one step only. 1 the hand points to information that requires special attention. c the caution indicates required informati on that needs special consideration and understanding and should be read prior to starting or continuing with the procedure or process. w the warning indicates information that should be read prior to starting or continuing the proce dure or processes r the angled arrow indicates you should press the enter key. f the feet direct you to more information on a particular topic. visual cue meaning
altera corporation section i?1 section i. stratix ii device family data sheet this section provides the data sheet specifications for stratix ? ii devices. this section contains feature defini tions of the internal architecture, configuration and jtag boundary-scan testing information, dc operating conditions, ac timing parameters, a reference to power consumption, and ordering information for stratix ii devices. this section contains the following chapters: chapter 1, introduction chapter 2, stratix ii architecture chapter 3, configuration & testing chapter 4, hot socketing & power-on reset chapter 5, dc & switching characteristics chapter 6, reference & ordering information revision history refer to each chapter for its own specific revision history. for information on when each chapter was updated, refer to the chapter revision dates section, which appears in the full handbook.
section i?2 altera corporation stratix ii device family data sheet stratix ii device handbook, volume 1
altera corporation 1?1 may 2007 1. introduction introduction the stratix ? ii fpga family is based on a 1.2-v, 90-nm, all-layer copper sram process and features a new logic structure that maximizes performance, and enables device densities approaching 180,000 equivalent logic elements (les). stra tix ii devices offer up to 9 mbits of on-chip, trimatrix? memory for demanding, memory intensive applications and has up to 96 dsp bl ocks with up to 384 (18-bit 18-bit) multipliers for efficient implementati on of high performance filters and other dsp functions. various high-spe ed external memory interfaces are supported, including double data rate (ddr) sdram and ddr2 sdram, rldram ii, quad data rate (qdr) ii sram, and single data rate (sdr) sdram. stratix ii devices support various i/o standards along with support for 1-gigabit per second (gbps) source synchronous signaling with dpa circuitry. strati x ii devices offer a complete clock management solution with internal clock frequency of up to 550 mhz and up to 12 phase-locked loops (plls). stratix ii devices are also the industry?s first fpgas with the ability to de crypt a configuration bitstream using the advanced encryp tion standard (aes) algorithm to protect designs. features the stratix ii family offers the following features: 15,600 to 179,400 equivalent les; see table 1?1 new and innovative adaptive logic module (alm), the basic building block of the stratix ii architecture, maximizes performance and resource usage efficiency up to 9,383,040 ram bits (1,172, 880 bytes) available without reducing logic resources trimatrix memory consisting of three ram block sizes to implement true dual-port memory and firs t-in first-out (fifo) buffers high-speed dsp blocks provide dedicated implementation of multipliers (at up to 450 mhz), multi ply-accumulate functions, and finite impulse resp onse (fir) filters up to 16 global clocks with 24 clocking resources per device region clock control blocks support dyna mic clock network enable/disable, which allows clock networks to power down to reduce power consumption in user mode up to 12 plls (four enhanced plls and eight fast plls) per device provide spread spectrum, programmable bandwidth, clock switch- over, real-time pll reconfiguratio n, and advanced multiplication and phase shifting sii51001-4.2
1?2 altera corporation stratix ii device handbook, volume 1 may 2007 features support for numerous single-ended and differential i/o standards high-speed differential i/o suppor t with dpa circuitry for 1-gbps performance support for high-speed networking and communications bus standards including parallel rapidio, spi-4 phase 2 (pos-phy level 4), hypertransport ? technology, and sfi-4 support for high-speed external memory, including ddr and ddr2 sdram, rldram ii, qdr ii sram, and sdr sdram support for multiple intellectual property megafunctions from altera megacore ? functions and altera megafunction partners program (ampp sm ) megafunctions support for design security using configuration bitstream encryption support for remote configuration updates table 1?1. stratix ii fpga family features feature ep2s15 ep2s30 ep2s60 ep2s90 ep2s130 ep2s180 alms 6,240 13,552 24,176 36,384 53,016 71,760 adaptive look-up tables (aluts) (1) 12,480 27,104 48,352 72,768 106,032 143,520 equivalent les (2) 15,600 33,880 60,440 90,960 132,540 179,400 m512 ram blocks 104 202 329 488 699 930 m4k ram blocks 78 144 255 408 609 768 m-ram blocks 012469 total ram bits 419,328 1,369,728 2,544,192 4,520,488 6,747,840 9,383,040 dsp blocks 12 16 36 48 63 96 18-bit 18-bit multipliers (3) 48 64 144 192 252 384 enhanced plls 2 2 4 4 4 4 fast plls 448888 maximum user i/o pins 366 500 718 902 1,126 1,170 notes to ta b l e 1 ? 1 : (1) one alm contains two aluts. the al ut is the cell used in the quartus ? ii software for logic synthesis. (2) this is the equivalent number of les in a st ratix device (four-input lut-based architecture). (3) these multipliers are imple mented using the dsp blocks.
altera corporation 1?3 may 2007 stratix ii device handbook, volume 1 introduction stratix ii devices are available in space-saving fineline bga ? packages (see tables 1?2 and 1?3 ). all stratix ii devices support vertical migration within the same package (for example, you can migrate betw een the ep2s15, ep2s30, and ep2s60 devices in the 672-pin fineline bga package). vertical migration means that you can migrate to devices whose dedicated pins, configuration pins, and power pins are the same for a give n package across device densities. to ensure that a board layout supports migratable densities within one package offering, enable the applicable vertical migration path within the quartus ii software (assignments menu > device > migration devices). table 1?2. stratix ii package options & i/o pin counts notes (1) , (2) device 484-pin fineline bga 484-pin hybrid fineline bga 672-pin fineline bga 780-pin fineline bga 1,020-pin fineline bga 1,508-pin fineline bga ep2s15 342 366 ep2s30 342 500 ep2s60 (3) 334 492 718 ep2s90 (3) 308 534 758 902 ep2s130 (3) 534 742 1,126 ep2s180 (3) 742 1,170 notes to ta b l e 1 ? 2 : (1) all i/o pin counts include ei ght dedicated clock input pins ( clk1p , clk1n , clk3p , clk3n , clk9p , clk9n , clk11p , and clk11n ) that can be used for data inputs. (2) the quartus ii software i/o pin co unts include one additional pin, pll_ena , which is not available as general- purpose i/o pins. the pll_ena pin can only be used to enab le the plls within the device. (3) the i/o pin counts for the ep2s60, ep2s90, ep2s130, and ep2s180 devices in the 1020-pin and 1508-pin packages include eight dedicated fa st pll clock inputs ( fpll7clkp/n , fpll8clkp/n , fpll9clkp/n , and fpll10clkp/n ) that can be used for data inputs. table 1?3. stratix ii fineline bga package sizes dimension 484 pin 484-pin hybrid 672 pin 780 pin 1,020 pin 1,508 pin pitch (mm) 1.00 1.00 1.00 1.00 1.00 1.00 area (mm2) 529 729 729 841 1,089 1,600 length width (mm mm) 23 23 27 27 27 27 29 29 33 33 40 40
1?4 altera corporation stratix ii device handbook, volume 1 may 2007 features after compilation, check the information messages for a full list of i/o, dq, lvds, and other pins that are no t available because of the selected migration path. table 1?4 lists the stratix ii device package offerings and shows the total number of non-migratable user i /o pins when migrating from one density device to a larger density de vice. additional i/ o pins may not be migratable if migrating from the larger device to the smaller density device. 1 when moving from one density to a larger density, the larger density device may have fewer user i/o pins. the larger device requires more power and ground pins to support the additional logic within the device. use the quartus ii pin planner to determine which user i/o pins are migratable between the two devices. 1 to determine if your user i/o assignments are correct, run the i/o assignment analysis comman d in the quartus ii software (processing > start > start i/o assignment analysis). f refer to the i/o management chapter in volume 2 of the quartus ii handbook for more information on pin migration. table 1?4. total number of non-migratable i/o pins for stratix ii ver tical migration paths vertical migration path 484-pin fineline bga 672-pin fineline bga 780-pin fineline bga 1020-pin fineline bga 1508-pin fineline bga ep2s15 to ep2s30 0 (1) 0 ep2s15 to ep2s60 8 (1) 0 ep2s30 to ep2s60 8 (1) 8 ep2s60 to ep2s90 0 ep2s60 to ep2s130 0 ep2s60 to ep2s180 0 ep2s90 to ep2s130 0 (1) 16 17 ep2s90 to ep2s180 16 0 ep2s130 to ep2s180 0 0 note to ta b l e 1 ? 4 : (1) some of the dq/dqs pins are not migratable. refer to the quartus ii software information messages for more detailed information.
altera corporation 1?5 may 2007 stratix ii device handbook, volume 1 introduction stratix ii devices are available in up to three speed grades, -3, -4, and -5, with -3 being the fastest. table 1?5 shows stratix ii device speed-grade offerings. table 1?5. stratix ii device speed grades device temperature grade 484-pin fineline bga 484-pin hybrid fineline bga 672-pin fineline bga 780-pin fineline bga 1,020-pin fineline bga 1,508-pin fineline bga ep2s15 commercial -3, -4, -5 -3, -4, -5 industrial -4 -4 ep2s30 commercial -3, -4, -5 -3, -4, -5 industrial -4 -4 ep2s60 commercial -3, -4, -5 -3, -4, -5 -3, -4, -5 industrial -4 -4 -4 ep2s90 commercial -4, -5 -4, -5 -3, -4, -5 -3, -4, -5 industrial -4 -4 ep2s130 commercial -4, -5 -3, -4, -5 -3, -4, -5 industrial -4 -4 ep2s180 commercial -3, -4, -5 -3, -4, -5 industrial -4 -4
1?6 altera corporation stratix ii device handbook, volume 1 may 2007 document revision history document revision history table 1?6 shows the revision history for this chapter. table 1?6. document revision history date and document version changes made summary of changes may 2007, v4.2 moved document revision history to the end of the chapter. ? april 2006, v4.1 updated ?features? section. removed note 4 from table 1?2. updated table 1?4. ? december 2005, v4.0 updated tables 1?2, 1?4, and 1?5. updated figure 2?43. ? july 2005, v3.1 added vertical migration information, including table 1?4. updated table 1?5. ? may 2005, v3.0 updated ?features? section. updated table 1?2. ? march 2005, v2.1 updated ?introduction? and ?features? sections. ? january 2005, v2.0 added note to table 1?2. ? october 2004, v1.2 updated tables 1?2, 1?3, and 1?5. ? july 2004, v1.1 updated tables 1?1 and 1?2. updated ?features? section. ? february 2004, v1.0 added document to the stratix ii device handbook. ?
altera corporation 2?1 may 2007 2. stratix ii architecture functional description stratix ? ii devices contain a two-dimensional row- and column-based architecture to implement custom logic. a series of column and row interconnects of varying length and speed provides signal interconnects between logic array blocks (labs), me mory block structures (m512 ram, m4k ram, and m-ram blocks), and digital signal processing (dsp) blocks. each lab consists of eight adaptive logic modules (alms). an alm is the stratix ii device family?s basic building block of logic providing efficient implementation of user lo gic functions. labs are grouped into rows and columns across the device. m512 ram blocks are simple dual-port memory blocks with 512 bits plus parity (576 bits). these blocks prov ide dedicated simple dual-port or single-port memory up to 18-bits wide at up to 500 mhz. m512 blocks are grouped into columns across the device in between certain labs. m4k ram blocks are true dual-port me mory blocks with 4k bits plus parity (4,608 bits). these blocks provide dedicated true dual-port, simple dual-port, or single-por t memory up to 36-bits wide at up to 550 mhz. these blocks are grouped into columns across the device in between certain labs. m-ram blocks are true dual-port memo ry blocks with 512k bits plus parity (589,824 bits). these blocks provide dedicated true dual-port, simple dual-port, or single-port me mory up to 144-bits wide at up to 420 mhz. several m-ram blocks are located individually in the device's logic array. dsp blocks can implement up to eith er eight full-precision 9 9-bit multipliers, four full -precision 18 18-bit multipliers, or one full-precision 36 36-bit multiplier wi th add or subtract features. the dsp blocks support q1.15 format rounding and saturation in the multiplier and accumulator stages. these blocks also contain shift registers for digital signal processing applications, including finite impulse response (fir) and infinite impulse response (i ir) filters. dsp blocks are grouped into columns across the device and operate at up to 450 mhz. sii51002-4.3
2?2 altera corporation stratix ii device handbook, volume 1 may 2007 functional description each stratix ii device i/o pin is fed by an i/o element (ioe) located at the end of lab rows and columns ar ound the periphery of the device. i/o pins support numerous single-end ed and differential i/o standards. each ioe contains a bidirectional i/o buffer and six registers for registering input, output, and output -enable signals. when used with dedicated clocks, these registers provide exceptional performance and interface support with external me mory devices such as ddr and ddr2 sdram, rldram ii, and qdr ii sram devices. high-speed serial interface channels with dynamic ph ase alignment (dpa) support data transfer at up to 1 gbps using lvds or hypertransport tm technology i/o standards. figure 2?1 shows an overview of the stratix ii device. figure 2?1. stratix ii block diagram m512 ram blocks for dual-port memory, shift registers, & fifo buffers dsp blocks for multiplication and full implementation of fir filters m4k ram blocks for true dual-port memory & other embedded memory functions ioes support ddr, pci, pci-x, sstl-3, sstl-2, hstl-1, hstl-2, lvds, hypertransport & other i/o standards ioes ioes ioes ioes ioes ioes ioes ioes ioes ioes ioes ioes ioes ioes ioes ioes ioes labs labs ioes labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs ioes labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs ioes ioes labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs dsp block m-ram block
altera corporation 2?3 may 2007 stratix ii device handbook, volume 1 stratix ii architecture the number of m512 ram, m4k ram, and dsp blocks varies by device along with row and column numbers and m-ram blocks. table 2?1 lists the resources available in stratix ii devices. logic array blocks each lab consists of eight alms, carry chains, shared arithmetic chains, lab control signals, local interconnect, and register chain connection lines. the local interconnect transfer s signals between alms in the same lab. register chain connections transfer the output of an alm register to the adjacent alm register in an lab. the quartus ? ii compiler places associated logic in an lab or adjacent labs, allowing the use of local, shared arithmetic chain, and regist er chain connections for performance and area efficiency. figure 2?2 shows the stratix ii lab structure. table 2?1. stratix ii device resources device m512 ram columns/blocks m4k ram columns/blocks m-ram blocks dsp block columns/blocks lab columns lab rows ep2s15 4 / 104 3 / 78 0 2 / 12 30 26 ep2s30 6 / 202 4 / 144 1 2 / 16 49 36 ep2s60 7 / 329 5 / 255 2 3 / 36 62 51 ep2s90 8 / 488 6 / 408 4 3 / 48 71 68 ep2s130 9 / 699 7 / 609 6 3 / 63 81 87 ep2s180 11 / 930 8 / 768 9 4 / 96 100 96
2?4 altera corporation stratix ii device handbook, volume 1 may 2007 logic array blocks figure 2?2. stratix ii lab structure lab interconnects the lab local interconnect can drive alms in the same lab. it is driven by column and row interconnects and alm outputs in the same lab. neighboring labs, m512 ram bl ocks, m4k ram blocks, m-ram blocks, or dsp blocks from the left and right can also drive an lab's local interconnect through the direct link connection. the direct link connection feature minimizes the use of row and column interconnects, providing higher performance and flexibility. each alm can drive 24 alms through fast local and direct link interconnects. figure 2?3 shows the direct link connection. direct link interconnect from adjacent block direct link interconnect to adjacent block row interconnects of variable speed & length column interconnects of variable speed & length local interconnect is driven from either side by columns & labs, & from above by rows local interconnect lab direct link interconnect from adjacent block direct link interconnect to adjacent block alms
altera corporation 2?5 may 2007 stratix ii device handbook, volume 1 stratix ii architecture figure 2?3. direct link connection lab control signals each lab contains dedicated logic for driving control signals to its alms. the control signals include three clocks, three clock enables, two asynchronous clears, synchronous clea r, asynchronous preset/load, and synchronous load control signals. this gives a maximum of 11 control signals at a time. although synchr onous load and clear signals are generally used when implementing coun ters, they can also be used with other functions. each lab can use three clocks and th ree clock enable signals. however, there can only be up to two unique cl ocks per lab, as shown in the lab control signal generation circuit in figure 2?4 . each lab's clock and clock enable signals are linked. for exam ple, any alm in a particular lab using the labclk1 signal also uses labclkena1 . if the lab uses both the rising and falling edges of a cloc k, it also uses two lab-wide clock signals. de-asserting the clock enable signal turns off the corresponding lab-wide clock. each lab can use two asynchronous clear signals and an asynchronous load/preset signal. by default, the quartus ii software uses a not gate push-back technique to achieve preset. if you disable the not gate push-up option or assign a given register to power up high using the quartus ii software, the preset is ac hieved using the asynchronous load alms direct link interconnect to right direct link interconnect from right lab, trimatrix memory block, dsp block, or ioe output direct link interconnect from left lab, trimatrix memory block, dsp block, or ioe output local interconnect direct link interconnect to left
2?6 altera corporation stratix ii device handbook, volume 1 may 2007 adaptive logic modules signal with asynchronous load data input tied high. when the asynchronous load/prese t signal is used, the labclkena0 signal is no longer available. the lab row clocks [5..0] and lab local interconnect generate the lab-wide control signals. the multitrack tm interconnect's inherent low skew allows clock and control signal distribution in addition to data. figure 2?4 shows the lab control signal generation circuit. figure 2?4. lab-wide control signals adaptive logic modules the basic building block of logic in the stratix ii architecture, the adaptive logic module (alm), provides advanced features with efficient logic utilization. each alm contains a variety of look-up table (lut)-based resources that can be divided between two adaptive luts (aluts). with up to eight inputs to the two al uts, one alm can implement various combinations of two functions. this adaptability allo ws the alm to be dedicated row lab clocks local interconnect local interconnect local interconnect local interconnect local interconnect local interconnect labclk2 syncload labclkena0 or asyncload or labpreset labclk0 labclk1 labclr1 labclkena1 labclkena2 labclr0 synclr 6 6 6 there are two unique clock signals per lab.
altera corporation 2?7 may 2007 stratix ii device handbook, volume 1 stratix ii architecture completely backward-compatible with four-input lut architectures. one alm can also implement any function of up to six inputs and certain seven-input functions. in addition to the adaptive lut-base d resources, each alm contains two programmable registers, two dedicate d full adders, a carry chain, a shared arithmetic chain, and a regi ster chain. through these dedicated resources, the alm can efficientl y implement various arithmetic functions and shift registers. each al m drives all types of interconnects: local, row, column, carry chain, shared arithmetic chain, register chain, and direct link interconnects. figure 2?5 shows a high-level block diagram of the stratix ii alm while figure 2?6 shows a detailed view of all the connections in the alm. figure 2?5. high-level block di agram of the stratix ii alm dq to general or local routing reg0 to general or local routing datae0 dataf0 shared_arith_in shared_arith_out reg_chain_in reg_chain_out adder0 dataa datab datac datad combinational logic datae1 dataf1 dq to general or local routing reg1 to general or local routing adder1 carry_in carry_out
2?8 altera corporation stratix ii device handbook, volume 1 may 2007 adaptive logic modules figure 2?6. stratix ii alm details prn/ald clrn d a data ena q prn/ald clrn d a data ena q 4-input lut 3-input lut 3-input lut 4-input lut 3-input lut 3-input lut dataa datac datae0 dataf0 dataf1 datae1 datab datad v cc reg_chain_in sclr asyncload syncload ena[2..0] shared_arith_in carry_in carry_out clk[2..0] local interconnect row, column & direct link routing row, column & direct link routing local interconnect row, column & direct link routing row, column & direct link routing reg_chain_out shared_arith_out aclr[1..0] local interconnect local interconnect local interconnect local interconnect local interconnect local interconnect local interconnect local interconnect
altera corporation 2?9 may 2007 stratix ii device handbook, volume 1 stratix ii architecture one alm contains two programmable registers. each register has data, clock, clock enable, synchronous and asynchronous clear, asynchronous load data, and synchronous and as ynchronous load /preset inputs. global signals, general-purpose i/o pi ns, or any internal logic can drive the register's clock and clear control signals. either general-purpose i/o pins or internal logic can drive th e clock enable, preset, asynchronous load, and asynchronous load data. the asynchronous load data input comes from the datae or dataf input of the alm, which are the same inputs that can be used for register packing. for combinational functions, the register is bypassed and the output of the lut drives directly to the outputs of the alm. each alm has two sets of outputs that drive the local, row, and column routing resources. the lut, adder, or register output can drive these output drivers independently (see figure 2?6 ). for each set of output drivers, two alm outputs can drive co lumn, row, or direct link routing connections, and one of these al m outputs can also drive local interconnect resources. this allows the lut or adder to drive one output while the register drives another outp ut. this feature, called register packing, improves device utilization because the device can use the register and the combinational logi c for unrelated functions. another special packing mode allows the regist er output to feed back into the lut of the same alm so that the register is packed with its own fan-out lut. this provides another mechanism for improved fitting. the alm can also drive out registered and unregistered versions of the lut or adder output. f see the performance & logic efficiency analysis of stratix ii devices white paper for more information on the efficiencies of the stratix ii alm and comparisons with previous architectures. alm operating modes the stratix ii alm can operate in one of the following modes: normal mode extended lut mode arithmetic mode shared arithmetic mode each mode uses alm resources differently. in each mode, eleven available inputs to the alm--the eigh t data inputs from the lab local interconnect; carry-in from the previous alm or lab; the shared arithmetic chain connection from th e previous alm or lab; and the register chain connection--are directed to different destinations to implement the desired logic function. lab-wide signals provide clock, asynchronous clear, asynchronous preset/load, synchronous clear,
2?10 altera corporation stratix ii device handbook, volume 1 may 2007 adaptive logic modules synchronous load, and clock enable control for the register. these lab- wide signals are available in all alm modes. see the ?lab control signals? section for more information on the lab-wide control signals. the quartus ii software and supported third-party synthesis tools, in conjunction with parameterized functions such as library of parameterized modules (lpm) func tions, automatic ally choose the appropriate mode for common func tions such as counters, adders, subtractors, and arithmetic functions. if required, you can also create special-purpose functions that spec ify which alm operating mode to use for optimal performance. normal mode the normal mode is suitable for general logic applications and combinational functions. in this mode , up to eight data inputs from the lab local interconnect are inputs to the combinational logic. the normal mode allows two functions to be im plemented in one stratix ii alm, or an alm to implement a sing le function of up to six inputs. the alm can support certain combinations of co mpletely independent functions and various combinations of functi ons which have common inputs. figure 2?7 shows the supported lut combinations in normal mode.
altera corporation 2?11 may 2007 stratix ii device handbook, volume 1 stratix ii architecture figure 2?7. alm in normal mode note (1) note to figure 2?7 : (1) combinations of functions with fewe r inputs than those shown are also su pported. for example, combinations of functions with the following number of inputs are supported: 4 and 3, 3 and 3, 3 and 2, 5 and 2, etc. the normal mode provides complete backward compatibility with four- input lut architectures. two independen t functions of four inputs or less can be implemented in one stratix i i alm. in addition, a five-input function and an independent three- input function can be implemented without sharing inputs. 6-input lut dataf0 datae0 dataf0 datae0 dataa datab dataa datab datab datac datac dataf0 datae0 dataa datac 6-input lut datad datad datae1 combout0 combout1 combout0 combout1 combout0 combout1 dataf1 datae1 dataf1 datad datae1 dataf1 4-input lut 4-input lut 4-input lut 6-input lut dataf0 datae0 dataa datab datac datad combout0 5-input lut 5-input lut dataf0 datae0 dataa datab datac datad combout0 combout1 datae1 dataf1 5-input lut dataf0 datae0 dataa datab datac datad combout0 combout1 datae1 dataf1 5-input lut 3-input lut
2?12 altera corporation stratix ii device handbook, volume 1 may 2007 adaptive logic modules for the packing of two five-input fu nctions into one alm, the functions must have at least two common inputs. the common inputs are dataa and datab . the combination of a four-input function with a five-input function requires one common input (either dataa or datab ). in the case of implementing two si x-input functions in one alm, four inputs must be shared and the combin ational function must be the same. for example, a 4 2 crossbar switch (two 4-to-1 multiplexers with common inputs and unique select lines) can be implemented in one alm, as shown in figure 2?8 . the shared inputs are dataa , datab , datac , and datad , while the unique select lines are datae0 and dataf0 for function0 , and datae1 and dataf1 for function1 . this crossbar switch consumes four luts in a four-input lut-based architecture. figure 2?8. 4 2 crossbar switch example in a sparsely used device, function s that could be placed into one alm may be implemented in separate al ms. the quartus ii compiler spreads a design out to achieve the best possible performance. as a device begins to fill up, the quartus ii software auto matically utilizes the full potential of the stratix ii alm. the quartus ii compiler automatically searches for functions of common inputs or comple tely independent functions to be placed into one alm and to make efficien t use of the device resources. in addition, you can manually control re source usage by setting location assignments. any six-input function can be implemented utilizing inputs dataa, datab , datac , datad , and either datae0 and dataf0 or datae1 and dataf1 . if datae0 and dataf0 are utilized, the output is driven to register0 , and/or register0 is bypassed and the data drives out to the interconnect using the top set of output drivers (see figure 2?9 ). if six-input lut (function0) dataf0 datae0 dataa datab datac six-input lut (function1) datad datae1 combout0 combout1 dataf1 inputa sel0[1..0] sel1[1..0] inputb inputc inputd out0 out1 4 2 crossbar switch implementation in 1 alm
altera corporation 2?13 may 2007 stratix ii device handbook, volume 1 stratix ii architecture datae1 and dataf1 are utilized, the output drives to register1 and/or bypasses register1 and drives to the interconnect using the bottom set of output drivers. th e quartus ii compiler automatically selects the inputs to the lut. asynch ronous load data for the register comes from the datae or dataf input of the alm. alms in normal mode support register packing. figure 2?9. 6-input function in normal mode notes (1) , (2) notes to figure 2?9 : (1) if datae1 and dataf1 are used as inputs to the six-input function, then datae0 and dataf0 are available for register packing. (2) the dataf1 input is available for register packing only if the six-input function is un-registered. extended lut mode the extended lut mode is used to implement a specific set of seven-input functions. the set must be a 2-to-1 multiplexer fed by two arbitrary five-inp ut functions sharing four inputs. figure 2?10 shows the template of supported seven-input functions utilizing extended lut mode. in this mode, if the seven-in put function is unregistered, the unused eighth input is available for register packing. functions that fit into the template shown in figure 2?10 occur naturally in designs. these functions often appear in designs as ?if-else? statements in verilog hdl or vhdl code. 6-input lut dataf0 datae0 dataa datab datac datad datae1 dataf1 dq dq to general or local routing to general or local routing to general or local routing reg0 reg1 these inputs are available for register packing. (2)
2?14 altera corporation stratix ii device handbook, volume 1 may 2007 adaptive logic modules figure 2?10. template for supported sev en-input functions in extended lut mode note to figure 2?10 : (1) if the seven-input function is unregistered, the unused eighth input is available for register packing. the second register, reg1 , is not available. arithmetic mode the arithmetic mode is ideal for implementing adders, counters, accumulators, wide pari ty functions, and comp arators. an alm in arithmetic mode uses two sets of two four-input luts along with two dedicated full adders. the dedicated adders allow the luts to be available to perform pre-adder logic; therefore, each adder can add the output of two four-input functions. the four luts share the dataa and datab inputs. as shown in figure 2?11 , the carry-in signal feeds to adder0 , and the carry-out from adder0 feeds to carry-in of adder1 . the carry-out from adder1 drives to adder0 of the next alm in the lab. alms in arithmetic mode can drive out registered and/or unregistered versions of the adder outputs. datae0 combout0 5-input lut 5-input lut datac dataa datab datad dataf0 datae1 dataf1 dq to general or local routing to general or local routing reg0 this input is available for register packing. (1)
altera corporation 2?15 may 2007 stratix ii device handbook, volume 1 stratix ii architecture figure 2?11. alm in arithmetic mode while operating in arithmetic mode, the alm can support simultaneous use of the adder's carry output along with combinational logic outputs. in this operation, the adder output is ig nored. this usage of the adder with the combinational logic output provides resource savings of up to 50% for functions that can use this ability. an example of such functionality is a conditional operation, such as the one shown in figure 2?12 . the equation for this example is: r = (x < y) ? y : x to implement this function, the adder is used to subtract ?y? from ?x.? if ?x? is less than ?y,? the carry_out signal is ?1.? the carry_out signal is fed to an adder where it drives out to the lab local interconnect. it then feeds to the lab-wide syncload signal. when asserted, syncload selects the syncdata input. in this case, the data ?y? drives the syncdata inputs to the registers. if ?x? is greater than or equal to ?y,? the syncload signal is de-asserted and ?x? drives the data port of the registers. dataf0 datae0 carry_in carry_out dataa datab datac datad datae1 dataf1 dq dq to general or local routing to general or local routing reg0 reg1 to general or local routing to general or local routing 4-input lut 4-input lut 4-input lut 4-input lut adder1 adder0
2?16 altera corporation stratix ii device handbook, volume 1 may 2007 adaptive logic modules figure 2?12. conditional operation example the arithmetic mode also offers clock enable, counter enable, synchronous up/down control, add/subtract control, synchronous clear, synchronous load. the lab local interconnect data inputs generate the clock enable, counter enable, sync hronous up/down and add/subtract control signals. these control signals are good candidates for the inputs that are shared between the four luts in the alm. the synchronous clear and synchronous load options are lab-wide signals that affect all registers in the lab. the quartus ii software automatically places any registers that are not used by the counter into other labs. carry chain the carry chain provides a fast ca rry function between the dedicated adders in arithmetic or shared arithmetic mode. carry chains can begin in either the first alm or th e fifth alm in an lab. the final carry-out signal is routed to an alm, where it is fed to local, row, or column interconnects. y[1] y[0] x[0] x[0] carry_out x[2] x[2] x[1] x[1] y[2] dq to general or local routing reg0 comb & adder logic comb & adder logic comb & adder logic comb & adder logic dq to general or local routing reg1 dq to general or local routing to local routing & then to lab-wide syncload reg0 syncload syncload syncload alm 1 alm 2 r[0] r[1] r[2] carry chain adder output is not used. syncdata
altera corporation 2?17 may 2007 stratix ii device handbook, volume 1 stratix ii architecture the quartus ii compiler automatically creates carry chain logic during design processing, or you can create it manually during design entry. parameterized functions such as lpm functions autom atically take advantage of carry chains for the appropriate functions. the quartus ii compiler creates carry chains longer than 16 (8 alms in arithmetic or shared arithmetic mode) by linking labs together automatically. for enhanced fitting, a long carry chain runs vertically allowing fast horizontal connec tions to trimatrix memory and dsp blocks. a carry chain can contin ue as far as a full column. to avoid routing congestion in one sm all area of the device when a high fan-in arithmetic function is implemented, the lab can support carry chains that only utilize either the top half or the bottom half of the lab before connecting to the next lab. this leaves the other half of the alms in the lab available for implementing narrower fan-in functions in normal mode. carry chains that use the top four alms in the first lab carry into the top half of the alms in the next lab within the column. carry chains that use the bottom four alms in the first lab carry into the bottom half of the alms in the next lab within the column. every other column of labs is top-half bypassab le, while the other lab columns are bottom-half bypassable. see the ?multitrack interconnect? on page 2?22 section for more information on carry chain interconnect. shared arithmetic mode in shared arithmetic mode, the alm can implement a three-input add. in this mode, the alm is configured with four 4-input luts. each lut either computes the sum of three inpu ts or the carry of three inputs. the output of the carry computation is fed to the next adder (either to adder1 in the same alm or to adder0 of the next alm in the lab) via a dedicated connection called the shared arithmetic chain. this shared arithmetic chain can significantly im prove the performance of an adder tree by reducing the number of summ ation stages required to implement an adder tree. figure 2?13 shows the alm in shared arithmetic mode.
2?18 altera corporation stratix ii device handbook, volume 1 may 2007 adaptive logic modules figure 2?13. alm in shared arithmetic mode note to figure 2?13 : (1) inputs dataf0 and dataf1 are available for register pack ing in shared arithmetic mode. adder trees can be found in many diff erent applications. for example, the summation of the partial products in a logic-based multiplier can be implemented in a tree structure. another example is a corr elator function that can use a large adder tree to sum filtered data samples in a given time frame to recover or to de-spread data which was transmitted utilizing spread spectrum technology. an example of a three-bit add operation utilizing the shared arithmetic mode is shown in figure 2?14 . the partial sum (s[2..0]) and the partial carry (c[2..0]) is obtained using the luts, while the result (r[2..0]) is computed using the dedicated adders. datae0 carry_in shared_arith_in shared_arith_out carry_out dataa datab datac datad datae1 dq dq to general or local routing to general or local routing reg0 reg1 to general or local routing to general or local routing 4-input lut 4-input lut 4-input lut 4-input lut
altera corporation 2?19 may 2007 stratix ii device handbook, volume 1 stratix ii architecture figure 2?14. example of a 3-bit add utilizing shared arithmetic mode shared arithmetic chain in addition to the dedicated carry chai n routing, the shared arithmetic chain available in shared arithmetic mode allows the alm to implement a three-input add. this significantly reduces the resources necessary to implement large adder trees or correlator functions. the shared arithmetic chains can begin in either the first or fifth alm in an lab. the quartus ii compiler create s shared arithmetic chains longer than 16 (8 alms in arithmetic or sh ared arithmetic mode) by linking labs together automatically. for e nhanced fitting, a long shared carry_in = '0' shared_arith_in = '0' z0 y0 x0 binary add decimal equivalents + z1 x1 r0 c0 s0 s1 s2 c1 c2 '0' r1 y1 3-input lut 3-input lut 3-input lut 3-input lut z2 y2 x2 r2 r3 3-input lut 3-input lut 3-input lut 3-input lut alm 1 3-bit add example alm implementation alm 2 x2 x1 x0 y2 y1 y0 z2 z1 z0 s2 s1 s0 c2 c1 c0 r3 r2 r1 r0 + + 1 1 0 1 0 1 0 1 0 0 0 1 1 1 0 1 1 0 1 + + 6 5 2 1 2 x 6 13 + 2nd stage add is implemented in adders. 1st stage add is implemented in luts.
2?20 altera corporation stratix ii device handbook, volume 1 may 2007 adaptive logic modules arithmetic chain runs vertically allo wing fast horizontal connections to trimatrix memory and dsp blocks. a shared arithmetic chain can continue as far as a full column. similar to the carry chains, the shared arithmetic chains are also top- or bottom-half bypassable. th is capability allows the shared arithmetic chain to cascade through half of the alms in a lab while leaving the other half available for narrower fan-in functionality. every other lab column is top-half bypassable, wh ile the other lab columns are bottom- half bypassable. see the ?multitrack interconnect? on page 2?22 section for more information on shared arit hmetic chain interconnect. register chain in addition to the general routing ou tputs, the alms in an lab have register chain outputs. the register chain routing allows registers in the same lab to be cascaded together. th e register chain interconnect allows an lab to use luts for a single combinational function and the registers to be used for an unrelated shift re gister implementation. these resources speed up connections between alms while saving local interconnect resources (see figure 2?15 ). the quartus ii compil er automatically takes advantage of these resources to im prove utilization and performance.
altera corporation 2?21 may 2007 stratix ii device handbook, volume 1 stratix ii architecture figure 2?15. register c hain within an lab note (1) note to figure 2?15 : (1) the combinational or adder logic can be utilized to implement an unrelated, un-registered function. see the ?multitrack interconnect? on page 2?22 section for more information on register chain interconnect. dq to general or local routing reg0 to general or local routing reg_chain_in adder0 dq to general or local routing reg1 to general or local routing adder1 dq to general or local routing reg0 to general or local routing reg_chain_out adder0 dq to general or local routing reg1 to general or local routing adder1 from previous alm within the lab to next alm within the lab combinational logic combinational logic
2?22 altera corporation stratix ii device handbook, volume 1 may 2007 multitrack interconnect clear & preset logic control lab-wide signals control the logic for the register's clear and load/preset signals. the alm directly supports an asynchronous clear and preset function. the register preset is achi eved through the asynchronous load of a logic high. the direct asynchro nous preset does not require a not- gate push-back technique. stratix ii devices support simultaneous asynchronous load/preset, and clea r signals. an asynchronous clear signal takes precedence if both signals are asserted simultaneously. each lab supports up to two clears and one load/preset signal. in addition to the clear and load/pre set ports, stratix ii devices provide a device-wide reset pin ( dev_clrn ) that resets all registers in the device. an option set before compilation in the quartus ii software controls this pin. this device-wide reset overrides all other control signals. multitrack interconnect in the stratix ii architecture, co nnections between alms, trimatrix memory, dsp blocks, and device i/o pi ns are provided by the multitrack interconnect structur e with directdrive tm technology. the multitrack interconnect consists of continuous , performance-optimi zed routing lines of different lengths and speeds used for inter- and intra-design block connectivity. the quartus ii compiler au tomatically places critical design paths on faster interconnects to improve design performance. directdrive technology is a deterministic routing technology that ensures identical routing resource usage for any function regardless of placement in the device. the multitrack interconnect and directdrive technology simplify the integration stage of bloc k-based designing by eliminating the re-optimization cycles that typi cally follow desi gn changes and additions. the multitrack interconnect consists of row and column interconnects that span fixed distances. a routing structure with fixed length resources for all devices allows predictable and repeatable performance when migrating through different device densities. dedicated row interconnects route signals to and from labs, dsp blocks, and trimatrix memory in the same row. these row resources include: direct link interconnects between labs and adjacent blocks r4 interconnects traversing fo ur blocks to the right or left r24 row interconnects for high-speed access across the length of the device
altera corporation 2?23 may 2007 stratix ii device handbook, volume 1 stratix ii architecture the direct link interconnect allows an lab, dsp block, or trimatrix memory block to drive into the local in terconnect of its left and right neighbors and then back into itself. this provides fast communication between adjacent labs and/or bloc ks without using row interconnect resources. the r4 interconnects span four labs, three labs and one m512 ram block, two labs and one m4k ram block, or two labs and one dsp block to the right or left of a source lab. these resources are used for fast row connections in a four-lab region . every lab has its own set of r4 interconnects to drive either left or right. figure 2?16 shows r4 interconnect connections from an lab. r4 interconnects can drive and be driven by dsp blocks and ram blocks and row ioes. for lab interfacing, a primary lab or lab neighbor can drive a given r4 interconnect. for r4 interconnects th at drive to the right, the primary lab and right neighbor can drive on to the interconnect. for r4 interconnects that drive to the left, the primary lab and its left neighbor can drive on to the interconnect. r4 interconnects can drive other r4 interconnects to extend the range of labs they can drive. r4 interconnects can also drive c4 an d c16 interconnects for connections from one row to another. additional ly, r4 interconnects can drive r24 interconnects. figure 2?16. r4 interconnect connections notes (1) , (2) , (3) notes to figure 2?16 : (1) c4 and c16 interconnects can drive r4 interconnects. (2) this pattern is repeated for every lab in the lab row. (3) the labs in figure 2?16 show the 16 possible logical outputs per lab. primary lab (2) r4 interconnect driving left adjacent lab can drive onto another lab's r4 interconnect c4 and c16 column interconnects (1) r4 interconnect driving right lab neighbor lab neighbor
2?24 altera corporation stratix ii device handbook, volume 1 may 2007 multitrack interconnect r24 row interconnects span 24 labs and provide the fastest resource for long row connections between labs, trimatrix memory, dsp blocks, and row ioes. the r24 row interconnects can cross m-ram blocks. r24 row interconnects drive to other row or column interconnects at every fourth lab and do not drive directly to lab local interconnects. r24 row interconnects drive lab local interconnects via r4 and c4 interconnects. r24 interconnects can drive r24, r4, c16, and c4 interconnects. the column interconnect operates si milarly to the row interconnect and vertically routes signals to and from labs, trimatrix memory, dsp blocks, and ioes. each column of labs is served by a dedicated column interconnect. these column resources include: shared arithmetic chain interconnects in an lab carry chain interconnects in an lab and from lab to lab register chain interconnects in an lab c4 interconnects traversing a distance of four blocks in up and down direction c16 column interconnects for high -speed vertical routing through the device stratix ii devices include an enhanced interconnect structure in labs for routing shared arithmetic chains and carry chains for efficient arithmetic functions. the register chain connection allows the register output of one alm to connect directly to the regist er input of the next alm in the lab for fast shift registers. these alm to alm connections bypass the local interconnect. the quartus ii compiler automatically takes advantage of these resources to improve utilization and performance. figure 2?17 shows the shared arithmetic chain, carry chain and register chain interconnects.
altera corporation 2?25 may 2007 stratix ii device handbook, volume 1 stratix ii architecture figure 2?17. shared arithmetic chain, carry chain & register chain interconnects the c4 interconnects span four labs , m512, or m4k blocks up or down from a source lab. every lab has its own set of c4 interconnects to drive either up or down. figure 2?18 shows the c4 interc onnect connections from an lab in a column. the c4 interconnects can drive and be driven by all types of architecture bloc ks, including dsp blocks, trimatrix memory blocks, and column and row ioes. for lab interconnection, a primary lab or its lab neighbor can drive a given c4 interconnect. c4 interconnects can drive each other to extend their range as well as drive row interconnects for colu mn-to-column connections. alm 1 alm 2 alm 3 alm 4 alm 5 alm 6 alm 8 alm 7 carry chain & shared arithmetic chain routing to adjacent alm local interconnect register chain routing to adjacent alm's register inpu local interconnect routing among alms in the lab
2?26 altera corporation stratix ii device handbook, volume 1 may 2007 multitrack interconnect figure 2?18. c4 inte rconnect connections note (1) note to figure 2?18 : (1) each c4 interconnect can drive either up or down four rows. c4 interconnect drives local and r4 interconnects up to four rows adjacent lab can drive onto neighboring lab's c4 interconnect c4 interconnect driving up c4 interconnect driving down lab row interconnect local interconnect
altera corporation 2?27 may 2007 stratix ii device handbook, volume 1 stratix ii architecture c16 column interconnects span a length of 16 labs and provide the fastest resource for long column connections between labs, trimatrix memory blocks, dsp blocks, and ioes. c16 interconnects can cross m-ram blocks and also drive to row and column interconnects at every fourth lab. c16 interconnects drive lab local interconnects via c4 and r4 interconnects and do not drive lab local interconnects directly. all embedded blocks communicate with the logic array similar to lab- to-lab interfaces. each block (that is, trimatrix memory and dsp blocks) connects to row and column interconnects and has local interconnect regions driven by row and column interconnects. these blocks also have direct link interconnects for fast co nnections to and from a neighboring lab. all blocks are fed by the row lab clocks, labclk[5..0] . table 2?2 shows the stratix ii device?s routing scheme. table 2?2. stratix ii device routing scheme (part 1 of 2) source destination shared arithmetic chain carry chain register chain local interconnect direct link interconnect r4 interconnect r24 interconnect c4 interconnect c16 interconnect alm m512 ram block m4k ram block m-ram block dsp blocks column ioe row ioe shared arithmetic chain v carry chain v register chain v local interconnect vvvvvvv direct link interconnect v r4 interconnect v vvvv r24 interconnect vvvv c4 interconnect vvv c16 interconnect vvvv alm vvvvvv v m512 ram block vvv v m4k ram block vvv v m-ram block vvvv dsp blocks vv v
2?28 altera corporation stratix ii device handbook, volume 1 may 2007 trimatrix memory trimatrix memory trimatrix memory consists of three types of ram blocks: m512, m4k, and m-ram. although thes e memory blocks are different, they can all implement various types of memory with or without parity, including true dual-port, simple dual-port, and single-port ram, rom, and fifo buffers. table 2?3 shows the size and features of the different ram blocks. column ioe vvv row ioe vvvv table 2?2. stratix ii device routing scheme (part 2 of 2) source destination shared arithmetic chain carry chain register chain local interconnect direct link interconnect r4 interconnect r24 interconnect c4 interconnect c16 interconnect alm m512 ram block m4k ram block m-ram block dsp blocks column ioe row ioe table 2?3. trimatrix memory features (part 1 of 2) memory feature m512 ram block (32 18 bits) m4k ram block (128 36 bits) m-ram block (4k 144 bits) maximum performance 500 mhz 550 mhz 420 mhz true dual-port memory vv simple dual-port memory vvv single-port memory vvv shift register vv rom vv (1) fifo buffer vvv pack mode vv byte enable vvv address clock enable vv parity bits vvv mixed clock mode vvv memory initialization ( .mif ) vv
altera corporation 2?29 may 2007 stratix ii device handbook, volume 1 stratix ii architecture memory block size trimatrix memory provides three different memory sizes for efficient application support. the quartus ii soft ware automatically partitions the user-defined memory into the embedded memory blocks using the most efficient size combinations. you can also manually assign the memory to a specific block size or a mixture of block sizes. when applied to input registers, the asynchronous clear signal for the trimatrix embedded memory immediately clears the input registers. however, the output of the memory block does not show the effects until the next clock edge. when applied to output registers, the asynchronous clear signal clears the output registers and the effects are seen immediately. simple dual-port memory mixed width support vvv true dual-port memory mixed width support vv power-up conditions outputs cleared outputs cleared outputs unknown register clears output registers output registers output registers mixed-port read-during-write unknown output/old data unknown output/old data unknown output configurations 512 1 256 2 128 4 64 8 64 9 32 16 32 18 4k 1 2k 2 1k 4 512 8 512 9 256 16 256 18 128 32 128 36 64k 8 64k 9 32k 16 32k 18 16k 32 16k 36 8k 64 8k 72 4k 128 4k 144 notes to ta b l e 2 ? 3 : (1) the m-ram block does not support memory initiali zations. however, the m-ram block can emulate a rom function using a dual-port ram bock. the stratix ii devi ce must write to the dual-port memory once and then disable the write-enable ports afterwards. table 2?3. trimatrix memory features (part 2 of 2) memory feature m512 ram block (32 18 bits) m4k ram block (128 36 bits) m-ram block (4k 144 bits)
2?30 altera corporation stratix ii device handbook, volume 1 may 2007 trimatrix memory m512 ram block the m512 ram block is a simple dual-port memory block and is useful for implementing small fifo buffers, dsp, and clock domain transfer applications. each block contains 576 ram bits (includin g parity bits). m512 ram blocks can be configured in the following modes: simple dual-port ram single-port ram fifo rom shift register 1 violating the setup or hold time on the memory block address registers could corrupt memory contents. this applies to both read and write operations. when configured as ram or rom, you can use an initialization file to pre-load the memory contents. m512 ram blocks can have different cl ocks on its inputs and outputs. the wren, datain, and write address registers are all clocked together from one of the two clocks feeding th e block. the read address, rden, and output registers can be clocked by ei ther of the two cl ocks driving the block. this allows the ram block to operate in read/write or input/output clock modes. only the ou tput register can be bypassed. the six labclk signals or local interconnect can drive the inclock , outclock , wren , rden , and outclr signals. because of the advanced interconnect between the lab and m512 ram blocks, alms can also control the wren and rden signals and the ram clock, clock enable, and asynchronous clear signals. figure 2?19 shows the m512 ram block control signal generation logic. the ram blocks in stratix ii devices have local interconnects to allow alms and interconnects to drive into ram blocks. the m512 ram block local interconnect is driven by the r4, c4, and direct link interconnects from adjacent labs. the m512 ram bl ocks can communicate with labs on either the left or right side through these row interconnects or with lab columns on the left or right side with the column interconnects. the m512 ram block has up to 16 direct li nk input connections from the left adjacent labs and another 16 from the right adjacent lab. m512 ram outputs can also connect to left an d right labs through direct link interconnect. the m512 ram block has equal opportunity for access and performance to and from labs on either its left or right side. figure 2?20 shows the m512 ram block to logic array interface.
altera corporation 2?31 may 2007 stratix ii device handbook, volume 1 stratix ii architecture figure 2?19. m512 ram block control signals inclocken outclock inclock outclocken rden wren dedicated row lab clocks local interconnect local interconnect local interconnect local interconnect local interconnect local interconnect outclr 6 local interconnect local interconnect
2?32 altera corporation stratix ii device handbook, volume 1 may 2007 trimatrix memory figure 2?20. m512 ram block lab row interface m4k ram blocks the m4k ram block includes support for true dual-port ram. the m4k ram block is used to implement buffer s for a wide variety of applications such as storing processor code, im plementing lookup schemes, and implementing larger memory applic ations. each block contains 4,608 ram bits (including parity bits). m4 k ram blocks can be configured in the following modes: true dual-port ram simple dual-port ram single-port ram fifo rom shift register when configured as ram or rom, you can use an initialization file to pre-load the memory contents. dataout m512 ram block datain clocks 16 direct link interconnect from adjacent lab direct link interconnect to adjacent lab direct link interconnect from adjacent lab direct link interconnect to adjacent lab m512 ram block local interconnect region c4 interconnect r4 interconnect control signals address lab row clocks 2 6
altera corporation 2?33 may 2007 stratix ii device handbook, volume 1 stratix ii architecture the m4k ram blocks allow for differ ent clocks on their inputs and outputs. either of the two clocks feeding the block can clock m4k ram block registers (renwe, address, byte enable, datain, and output registers). only the output register can be bypassed. the six labclk signals or local interconnects can drive the control signals for the a and b ports of the m4k ram block. alms can also control the clock_a , clock_b , renwe_a , renwe_b , clr_a , clr_b , clocken_a , and clocken_b signals, as shown in figure 2?21 . the r4, c4, and direct link interconnects from adjacent labs drive the m4k ram block local interconnect. the m4k ram blocks can communicate with labs on either the left or righ t side through these row resources or with lab columns on either the right or left with the column resources. up to 16 direct link input connections to the m4k ram block are possible from the left adjacent labs and another 16 possible from the right adjacent lab. m4k ram block outputs can also connect to left and right labs through direct link interconnect. figure 2?22 shows the m4k ram block to logic array interface. figure 2?21. m4k ram bl ock control signals clock_b clocken_a clock_a clocken_b aclr_b aclr_a dedicated row lab clocks local interconnect local interconnect local interconnect local interconnect local interconnect local interconnect local interconnect local interconnect renwe_b renwe_a 6
2?34 altera corporation stratix ii device handbook, volume 1 may 2007 trimatrix memory figure 2?22. m4k ram block lab row interface m-ram block the largest trimatrix memory block, the m-ram block, is useful for applications where a large volume of data must be stored on-chip. each block contains 589,824 ram bits (inc luding parity bits). the m-ram block can be configured in the following modes: true dual-port ram simple dual-port ram single-port ram fifo you cannot use an initialization file to initialize the contents of an m-ram block. all m-ram block contents powe r up to an undefined value. only synchronous operation is supported in the m-ram block, so all inputs are registered. output registers can be bypassed. dataout m4k ram block datain address 16 36 direct link interconnect from adjacent lab direct link interconnect to adjacent lab direct link interconnect from adjacent lab direct link interconnect to adjacent lab m4k ram block local interconnect region c4 interconnect r4 interconnect lab row clocks clocks byte enable control signals 6
altera corporation 2?35 may 2007 stratix ii device handbook, volume 1 stratix ii architecture similar to all ram blocks, m-ram bloc ks can have different clocks on their inputs and outputs. either of the two clocks feeding the block can clock m-ram block registers (renwe, address, byte enable, datain, and output registers). the output re gister can be bypassed. the six labclk signals or local interconnect can drive the control signals for the a and b ports of the m-ram block. alms can also control the clock_a , clock_b , renwe_a , renwe_b , clr_a , clr_b , clocken_a , and clocken_b signals as shown in figure 2?23 . figure 2?23. m-ram block control signals the r4, r24, c4, and direct link interconnects from adjacent labs on either the right or left side drive the m-ram block local interconnect. up to 16 direct link input connections to the m-ram block are possible from the left adjacent labs and another 16 possible from the right adjacent lab. m-ram block outputs can also connect to left and right labs through direct link interconnect. figure 2?24 shows an example floorplan for the ep2s130 device and the loca tion of the m-ram interfaces. figures 2?25 and 2?26 show the interface between the m-ram block and the logic array. clock_a clock_b clocken_a clocken_b aclr_a aclr_b dedicated row lab clocks local interconnect local interconnect local interconnect local interconnect renwe_a renwe_b 6 local interconnect local interconnect local interconnect local interconnect local interconnect local interconnect local interconnect local interconnect
2?36 altera corporation stratix ii device handbook, volume 1 may 2007 trimatrix memory figure 2?24. ep2s130 device with m-ram interface locations note (1) note to figure 2?24 : (1) the device shown is an ep2s130 device. the number and position of m-ram bloc ks varies in other devices. dsp blocks dsp blocks m4k blocks m512 blocks labs m-ram block m-ram block m-ram block m-ram block m-ram block m-ram block m-ram blocks interface to labs on right and left sides for easy access to horizontal i/o pins
altera corporation 2?37 may 2007 stratix ii device handbook, volume 1 stratix ii architecture figure 2?25. m-ram block lab row interface note (1) note to figure 2?25 : (1) only r24 and c16 interconnects cross the m-ram block boundaries. m-ram block port b port a row unit interface allows lab rows to drive port b datain, dataout, address and control signals to and from m-ram block row unit interface allows lab rows to drive port a datain, dataout, address and control signals to and from m-ram block labs in row m-ram boundary labs in row m-ram boundary lab interface blocks l0 l1 l2 l3 l4 l5 r0 r1 r2 r3 r4 r5
2?38 altera corporation stratix ii device handbook, volume 1 may 2007 trimatrix memory figure 2?26. m-ram row unit interface to interconnect table 2?4 shows the input and output data signal connections along with the address and control signal input co nnections to the ro w unit interfaces (l0 to l5 and r0 to r5). lab row interface block m-ram block 16 up to 28 datain_a[ ] addressa[ ] addr_ena_a renwe_a byteena a [ ] clocken_a clock_a aclr_a m-ram block to lab row interface block interconnect region r4 and r24 interconnects c4 interconnect direct link interconnects dataout_a[ ] up to 16
altera corporation 2?39 may 2007 stratix ii device handbook, volume 1 stratix ii architecture f see the trimatrix embedded memory blocks in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii device handbook or the stratix ii gx device handbook for more information on trimatrix memory. table 2?4. m-ram row interface unit signals unit interface block input signals output signals l0 datain_a[14..0] byteena_a[1..0] dataout_a[11..0] l1 datain_a[29..15] byteena_a[3..2] dataout_a[23..12] l2 datain_a[35..30] addressa[4..0] addr_ena_a clock_a clocken_a renwe_a aclr_a dataout_a[35..24] l3 addressa[15..5] datain_a[41..36] dataout_a[47..36] l4 datain_a[56..42] byteena_a[5..4] dataout_a[59..48] l5 datain_a[71..57] byteena_a[7..6] dataout_a[71..60] r0 datain_b[14..0] byteena_b[1..0] dataout_b[11..0] r1 datain_b[29..15] byteena_b[3..2] dataout_b[23..12] r2 datain_b[35..30] addressb[4..0] addr_ena_b clock_b clocken_b renwe_b aclr_b dataout_b[35..24] r3 addressb[15..5] datain_b[41..36] dataout_b[47..36] r4 datain_b[56..42] byteena_b[5..4] dataout_b[59..48] r5 datain_b[71..57] byteena_b[7..6] dataout_b[71..60]
2?40 altera corporation stratix ii device handbook, volume 1 may 2007 digital signal processing block digital signal processing block the most commonly used dsp functions are fir filters, complex fir filters, iir filters, fast fourier tr ansform (fft) functions, direct cosine transform (dct) functions, and correlators. all of these use the multiplier as the fundamental building block. ad ditionally, some applications need specialized operations such as mul tiply-add and multiply-accumulate operations. stratix ii devices provide dsp blocks to meet the arithmetic requirements of these functions. each stratix ii device has from two to four columns of dsp blocks to efficiently implement dsp functions faster than alm-based implementations. stratix i i devices have up to 24 dsp blocks per column (see table 2?5 ). each dsp block can be configured to support up to: eight 9 9-bit multipliers four 18 18-bit multipliers one 36 36-bit multiplier as indicated, the stratix ii dsp block can support one 36 36-bit multiplier in a single dsp block. th is is true for any combination of signed, unsigned, or mixed sign multiplications. 1 this list only shows functions that can fit into a single dsp block. multiple dsp blocks can support larger multiplication functions.
altera corporation 2?41 may 2007 stratix ii device handbook, volume 1 stratix ii architecture figure 2?27 shows one of the columns with surrounding lab rows. figure 2?27. dsp blocks arranged in columns dsp block column 4 lab rows dsp block
2?42 altera corporation stratix ii device handbook, volume 1 may 2007 digital signal processing block table 2?5 shows the number of dsp bloc ks in each stratix ii device. dsp block multipliers can optionally feed an adder/subtractor or accumulator in the block depending on the configuration. this makes routing to alms easier, saves alm routing resources, and increases performance, because all connections and blocks are in the dsp block. additionally, the dsp block input regi sters can efficiently implement shift registers for fir filter applications, and dsp blocks support q1.15 format rounding and saturation. figure 2?28 shows the top-level diagram of the dsp block configured for 18 18-bit multiplier mode. table 2?5. dsp blocks in stratix ii devices note (1) device dsp blocks total 9 9 multipliers total 18 18 multipliers total 36 36 multipliers ep2s15 12 96 48 12 ep2s30 16 128 64 16 ep2s60 36 288 144 36 ep2s90 48 384 192 48 ep2s130 63 504 252 63 ep2s180 96 768 384 96 note to ta b l e 2 ? 5 : (1) each device has either the numbers of 9 9-, 18 18-, or 36 36-bit multipliers shown. the total number of multipliers for each device is not the sum of all the multipliers.
altera corporation 2?43 may 2007 stratix ii device handbook, volume 1 stratix ii architecture figure 2?28. dsp block diagram fo r 18 18-bit configuration adder/ subtractor/ accumulator 1 adder multiplier block prn clrn dq ena prn clrn dq ena prn clrn dq ena prn clrn dq ena prn clrn dq ena prn clrn dq ena prn clrn dq ena prn clrn dq ena prn clrn dq ena prn clrn dq ena prn clrn dq ena prn clrn dq ena summation block adder output block adder/ subtractor/ accumulator 2 q1.15 round/ saturate q1.15 round/ saturate q1.15 round/ saturate q1.15 round/ saturate to multitrack interconnect clrn dq ena from the row interface block optional serial shift register inputs from previous dsp block optional serial shift register outputs to next dsp block in the column optional input register stage with parallel input or shift register configuration optional pipline register stage summation stage for adding four multipliers together optional stage configurable as accumulator or dynamic adder/subtractor output selection multiplexer q1.15 round/ saturate q1.15 round/ saturate
2?44 altera corporation stratix ii device handbook, volume 1 may 2007 digital signal processing block modes of operation the adder, subtractor, and accumulate functions of a dsp block have four modes of operation: simple multiplier multiply-accumulator two-multipliers adder four-multipliers adder table 2?6 shows the different number of multipliers possible in each dsp block mode according to size. thes e modes allow the dsp blocks to implement numerous applications for dsp including ffts, complex fir, fir, and 2d fir filters, equalizers, iir, correlators, matrix multiplication and many other functions. the dsp blocks also support mixed modes and mixed multiplier sizes in the same block. for example, half of one dsp block can implement one 18 18-bit multiplier in multiply- accumulator mode, while the other half of the dsp block implements four 9 9-bit multipliers in simple multiplier mode. dsp block interface stratix ii device dsp block input register s can generate a shift register that can cascade down in the same dsp block column. dedicated connections between dsp blocks provide fast connections between the shift register inputs to cascade the shift register chains. you can cascade registers within multiple dsp blocks for 9 9- or 18 18-bit fir filters larger than four taps, with additional adder stag es implemented in alms. if the dsp block is configured as 36 36 bits, th e adder, subtractor, or accumulator stages are implemented in alms. each dsp block can route the shift register chain out of the block to ca scade multiple columns of dsp blocks. table 2?6. multiplier size & c onfigurations per dsp block dsp block mode 9 9 18 18 36 36 multiplier eight multipliers with eight product outputs four multipliers with four product outputs one multiplier with one product output multiply-accumulator - two 52-bit multiply- accumulate blocks - two-multipliers adder four two-multiplier adder (two 9 9 complex multiply) two two-multiplier adder (one 18 18 complex multiply) - four-multipliers adder two four-multi plier adder one four-multiplier adder -
altera corporation 2?45 may 2007 stratix ii device handbook, volume 1 stratix ii architecture the dsp block is divided into four bl ock units that interface with four lab rows on the left and right. each block unit can be considered one complete 18 18-bit multiplier with 36 inputs and 36 outputs. a local interconnect region is associated with each dsp block. like an lab, this interconnect region can be fed with 16 direct link interconnects from the lab to the left or right of the dsp block in the same row. r4 and c4 routing resources can access the dsp block's local interconnect region. the outputs also work si milarly to lab outputs as well. eighteen outputs from the dsp block can drive to th e left lab through direct link interconnects and eighteen can drive to the right lab though direct link interconnects. all 36 outputs can drive to r4 and c4 routing interconnects. outputs can drive right- or left-column routing. figures 2?29 and 2?30 show the dsp block interfaces to lab rows. figure 2?29. dsp block interconnect interface a1[17..0] b1[17..0] a2[17..0] b2[17..0] a3[17..0] b3[17..0] a4[17..0] b4[17..0] oa[17..0] ob[17..0] oc[17..0] od[17..0] oe[17..0] of[17..0] og[17..0] oh[17..0] dsp block r4, c4 & direct link interconnects r4, c4 & direct link interconnects
2?46 altera corporation stratix ii device handbook, volume 1 may 2007 digital signal processing block figure 2?30. dsp block interface to interconnect a bus of 44 control signals feeds the entire dsp block. these signals include clocks, asynchronous clears, clock enables, signed/unsigned control signals, addition and subtraction control signals, rounding and saturation control signals, and accumulator synchronous loads. the clock signals are routed from lab row cloc ks and are generated from specific lab rows at the dsp block interface. lab lab row interface block dsp block row structure 16 oa[17..0] ob[17..0] a[17..0] b[17..0] dsp block to lab row interface block interconnect region 36 inputs per row 36 outputs per row r4 interconnect c4 interconnect direct link interconnect from adjacent lab direct link outputs to adjacent labs direct link interconnect from adjacent lab 36 36 36 36 control 12 16 18
altera corporation 2?47 may 2007 stratix ii device handbook, volume 1 stratix ii architecture the lab row source for control signals, data inputs, and outputs is shown in table 2?7 . f see the dsp blocks in stratix i i & stratix ii gx devices chapter in volume 2 of the stratix ii device handbook or the stratix ii gx device handbook, for more information on dsp blocks. table 2?7. dsp block signal sources & destinations lab row at interface control signals generated data inputs data outputs 0clock0 aclr0 ena0 mult01_saturate addnsub1_round/ accum_round addnsub1 signa sourcea sourceb a1[17..0] b1[17..0] oa[17..0] ob[17..0] 1clock1 aclr1 ena1 accum_saturate mult01_round accum_sload sourcea sourceb mode0 a2[17..0] b2[17..0] oc[17..0] od[17..0] 2clock2 aclr2 ena2 mult23_saturate addnsub3_round/ accum_round addnsub3 sign_b sourcea sourceb a3[17..0] b3[17..0] oe[17..0] of[17..0] 3clock3 aclr3 ena3 accum_saturate mult23_round accum_sload sourcea sourceb mode1 a4[17..0] b4[17..0] og[17..0] oh[17..0]
2?48 altera corporation stratix ii device handbook, volume 1 may 2007 plls & clock networks plls & clock networks stratix ii devices provide a hierarchical clock structure and multiple plls with advanced features. the large number of clocking resources in combination with the clock synthesi s precision provid ed by enhanced and fast plls provides a comple te clock management solution. global & hierarchical clocking stratix ii devices provide 16 dedicat ed global clock networks and 32 regional clock networks (eight per device quadrant). these clocks are organized into a hierarch ical clock structure that allows for up to 24 clocks per device region with low skew and delay. this hierarchical clocking scheme provides up to 48 un ique clock domains in stratix ii devices. there are 16 dedicated clock pins ( clk[15..0] ) to drive either the global or regional clock networks . four clock pins drive each side of the device, as shown in figures 2?31 and 2?32 . internal logic and enhanced and fast pll outputs can also driv e the global and regional clock networks. each global and regional clock has a cloc k control block, which controls the selection of the clock source and dynamically enables/disables the clock to reduce power consumption. table 2?8 shows global and regional clock features. global clock network these clocks drive throughout the entire device, feeding all device quadrants. the global clock networks can be used as clock sources for all resources in the device-ioes, alms, dsp blocks, and all memory blocks. these resources can also be used for control signals, such as clock enables and synchronous or asynch ronous clears fed from the external pin. the table 2?8. global & regional clock features feature global clocks regional clocks number per device 16 32 number available per quadrant 16 8 sources clk pins, pll outputs, or internal logic clk pins, pll outputs, or internal logic dynamic clock source selection v (1) dynamic enable/disable vv note to ta b l e 2 ? 8 : (1) dynamic source clock selection is supported for selecting between clkp pins and pll outputs only.
altera corporation 2?49 may 2007 stratix ii device handbook, volume 1 stratix ii architecture global clock networks can also be driv en by internal logic for internally generated global clocks and asynchrono us clears, clock enables, or other control signals with large fanout. figure 2?31 shows the 16 dedicated clk pins driving global clock networks. figure 2?31. global clocking regional clock network there are eight regional clock networks rclk[7..0] in each quadrant of the stratix ii device that are driven by the dedicated clk[15..0] input pins, by pll outputs, or by internal logic. the regional clock networks provide the lowest clock delay and skew for logic contained in a single quadrant. the clk clock pins symmetrically drive the rclk networks in a particular quadra nt, as shown in figure 2?32 . global clock [15..0] clk[15..12] clk[3..0] clk[7..4] clk[11..8] global clock [15..0]
2?50 altera corporation stratix ii device handbook, volume 1 may 2007 plls & clock networks figure 2?32. regional clocks dual-regional clock network a single source ( clk pin or pll output) can generate a dual-regional clock by driving two regi onal clock network lines in adjacent quadrants (one from each quadrant). this allows logic that spans multiple quadrants to utilize the same low skew clock. the routing of this clock signal on an entire side has approximately the same speed but slightly higher clock skew when compared with a clock signal that drives a single quadrant. internal logic-array routing can also drive a dual-regional clock. clock pins and enhanced pl l outputs on the top and bottom can drive horizontal dual-regional clocks. clock pins and fast pll outputs on the left and right can drive vertical dual-regional clocks, as shown in figure 2?33 . corner plls cannot drive dual-regional clocks. rclk[3..0] rclk[7..4] rclk[11..8] rclk[15..12] rclk[31..28] rclk[27..24] rclk[19..16] rclk[23..20] clk[15..12] clk[3..0] clk[7..4] clk[11..8] regional clocks only drive a device quadrant from specified clk pins, plls or core logic within that quadrant
altera corporation 2?51 may 2007 stratix ii device handbook, volume 1 stratix ii architecture figure 2?33. dual-regional clocks combined resources within each quadrant, there are 24 distinct dedicated clocking resources consisting of 16 global clock line s and eight regional clock lines. multiplexers are used with these cl ocks to form busses to drive lab row clocks, column ioe clocks, or row ioe clocks. another multiplexer is used at the lab level to select three of the six row clocks to feed the alm registers in the lab (see figure 2?34 ). figure 2?34. hierarchical clock networks per quadrant clock pins or pll clock outputs can drive dual-regional network clk[15..12] clk[11..8] clk[7..4] clk[3..0] plls plls clock pins or pll clock outputs can drive dual-regional network clk[15..12] clk[11..8] clk[7..4] clk[3..0] clock [23..0] column i/o cell io_clk[7..0] lab row clock [5..0] row i/o cell io_clk[7..0] global clock network [15..0] regional clock network [7..0] clocks available to a quadrant or half-quadrant
2?52 altera corporation stratix ii device handbook, volume 1 may 2007 plls & clock networks ioe clocks have row and column bloc k regions that are clocked by eight i/o clock signals chosen from th e 24 quadrant clock resources. figures 2?35 and 2?36 show the quadrant relati onship to the i/o clock regions. figure 2?35. ep2s15 & ep2s30 device i/o clock groups io_clkc[7:0] io_clkf[7:0] io_clke[7:0] io_clka[7:0] io_clkb[7:0] io_clkd[7:0] io_clkh[7:0] io_clkg[7:0] 8 8 24 clocks in the quadrant 24 clocks in the quadrant 24 clocks in the quadrant 24 clocks in the quadrant 8 8 8 8 8 8 i/o clock regions
altera corporation 2?53 may 2007 stratix ii device handbook, volume 1 stratix ii architecture figure 2?36. ep2s60, ep2s90, ep2s130 & ep2s180 device i/o clock groups you can use the quartus ii software to control whether a clock input pin drives either a global, regional, or dual-regional clock network. the quartus ii software automatically sele cts the clocking resources if not specified. clock control block each global clock, regional clock, and pll external cl ock output has its own clock control block. the co ntrol block has two functions: clock source selection (dynamic selection for global clocks) clock power-down (dynamic clock enable/disable) io_clkj[7:0] io_clki[7:0] io_clka[7:0] io_clkb[7:0] 8 24 clocks in the quadrant 24 clocks in the quadrant 24 clocks in the quadrant 24 clocks in the quadrant 8 8 8 i/o clock regions io_clkl[7:0] io_clkk[7:0] io_clkc[7:0] io_clkd[7:0] 888 8 8 8 8 8 8 8 8 8 io_clke[7:0] io_clkf[7:0] io_clkg[7:0] io_clkh[7:0] io_clkn[7:0] io_clkm[7:0] io_clkp[7:0] io_clko[7:0]
2?54 altera corporation stratix ii device handbook, volume 1 may 2007 plls & clock networks 1 when using the global or regi onal clock control blocks in stratix ii devices to select between multiple clocks or to enable and disable clock networks, be aw are of possible narrow pulses or glitches when switching from one clock signal to another. a glitch or runt pulse has a width th at is less than the width of the highest frequency input clock si gnal. to prevent logic errors within the fpga, altera recomm ends that you build circuits that filter out glitches and runt pulses. figures 2?37 through 2?39 show the clock control block for the global clock, regional clock, and pll ex ternal clock outp ut, respectively. figure 2?37. global clock control blocks notes to figure 2?37 : (1) these clock select signals can be dynamically controlled through internal logic when the device is operating in user mode. (2) these clock select signals can only be set through a configuration file ( .sof or .pof ) and cannot be dynamically controlled during user mode operation. clkp pins pll counter outputs internal logic clkn pin enable/ disable gclk internal logic static clock select this multiplexer supports user-controllable dynamic switching clkselect[1..0] (1) (2) 2 2 2
altera corporation 2?55 may 2007 stratix ii device handbook, volume 1 stratix ii architecture figure 2?38. regional clock control blocks notes to figure 2?38 : (1) these clock select signals can only be set through a configuration file ( .sof or .pof ) and cannot be dynamically controlled during user mode operation. (2) only the clkn pins on the top and bottom of the de vice feed to regional clock select blocks.the clock outputs from corner plls cannot be dynamically selected through the global clock control block. (3) the clock outputs from corner plls ca nnot be dynamically selected through the global clock control block. clkp pin pll counter outputs internal logic clkn pin enable/ disable rclk internal logic static clock select (1 ) 2 (2) (3)
2?56 altera corporation stratix ii device handbook, volume 1 may 2007 plls & clock networks figure 2?39. external pll output clock control blocks notes to figure 2?39 : (1) these clock select signals can only be set through a configuration file ( .sof or .pof ) and cannot be dynamically controlled during user mode operation. (2) the clock control block feed s to a multiplexer within the pll_out pin?s ioe. the pll_out pin is a dual-purpose pin. therefore, this multiplexer selects either an internal signal or the output of the clock control block. for the global clock control block, the clock source selection can be controlled either statically or dynami cally. the user has the option of statically selecting the clock source by using the quartus ii software to set specific configuration bits in the configuration file ( .sof or .pof ) or the user can control the selection dynamically by using internal logic to drive the multiplexor select inputs. when selecting statically, the clock source can be set to any of the inputs to th e select multiplexor. when selecting the clock source dynamically, you can either select between two pll outputs (such as the c0 or c1 outputs from one pll), between two plls (such as the c0/c1 clock output of on e pll or the c0/c1 c1ock output of the other pll), between tw o clock pins (such as clk0 or clk1 ), or between a combination of clock pins or pll outputs. the clock outputs from corner plls cannot be dynami cally selected through the global control block. for the regional and pll_out clock control block, the clock source selection can only be controlled statically using configuration bits. any of the inputs to the clock select multiplex or can be set as the clock source. pll counter outputs (c[5..0]) enable/ disable pll_out pin internal logic static clock select ioe (1) static clock select (1) 6 internal logic (2)
altera corporation 2?57 may 2007 stratix ii device handbook, volume 1 stratix ii architecture the stratix ii clock networks can be disabled (powered down) by both static and dynamic approaches. when a clock net is powered down, all the logic fed by the clock net is in an off-state thereby reducing the overall power consumption of the device. the global and regional clock networks can be powered down statically through a setting in the configuration ( .sof or .pof ) file. clock networks that are not used are automatically powered down through configuration bit settings in the configuration file generated by the quartus ii software. the dynamic clock enable/disable fe ature allows the internal logic to control power up/down synchronously on gclk and rclk nets and pll_out pins. this function is independent of the pll and is applied directly on the clock network or pll_out pin, as shown in figures 2?37 through 2?39 . 1 the following restrictions for the input clock pins apply: ? clk0 pin -> inclk[0] of clkctrl ? clk1 pin -> inclk[1] of clkctrl ? clk2 pin -> inclk[0] of clkctrl ? clk3 pin -> inclk[1] of clkctrl in general, even clk numbers connect to the inclk[0] port of clkctrl , and odd clk numbers connect to the inclk[1] port of clkctrl . failure to comply with these restrictions will result in a no-fit error. enhanced & fast plls stratix ii devices provide robust clock management and synthesis using up to four enhanced plls and eigh t fast plls. these plls increase performance and provid e advanced clock interfacing and clock- frequency synthesis. with features such as clock switchover, spread-spectrum clocking, reconfigurab le bandwidth, phase control, and reconfigurable phase shifting, the stratix ii device?s enhanced plls provide you with complete control of clocks and system timing. the fast plls provide general purpose clocki ng with multiplication and phase shifting as well as high-speed outp uts for high-speed differential i/o support. enhanced and fast plls work together with the stratix ii high-speed i/o and advanc ed clock architecture to provide significant improvements in system performance and bandwidth.
2?58 altera corporation stratix ii device handbook, volume 1 may 2007 plls & clock networks the quartus ii software enables the plls and their fe atures without requiring any external devices. table 2?9 shows the plls available for each stratix ii device and their type. table 2?9. stratix ii devi ce pll availability device fast plls enhanced plls 123478910561112 ep2s15 vvvv vv ep2s30 vvvv vv ep2s60 (1) vvvvvvvvvvvv ep2s90 (2) vvvvvvvvvvvv ep2s130 (3) vvvvvvvvvvvv ep2s180 vvvvvvvvvvvv notes to ta b l e 2 ? 9 : (1) ep2s60 devices in the 1020-pin package contain 12 plls. ep2s60 devices in the 484-pin and 672-pin packages contain fast plls 1?4 and enhanced plls 5 and 6. (2) ep2s90 devices in the 1020-pin and 1508-pin packages contain 12 plls. ep2s90 devices in the 484-pin and 780-pin packages contain fast plls 1?4 and enhanced plls 5 and 6. (3) ep2s130 devices in the 1020-pin and 1508-pin packages contain 12plls. the ep2s130 device in the 780-pin package contains fast plls 1?4 and enhanced plls 5 and 6.
altera corporation 2?59 may 2007 stratix ii device handbook, volume 1 stratix ii architecture table 2?10 shows the enhanced pll and fast pll features in stratix ii devices. table 2?10. stratix ii pll features feature enhanced pll fast pll clock multiplication and division m /( n post-scale counter) (1) m /( n post-scale counter) (2) phase shift down to 125-ps increments (3) , (4) down to 125-ps increments (3) , (4) clock switchover vv (5) pll reconfiguration vv reconfigurable bandwidth vv spread spectrum clocking v programmable duty cycle vv number of internal clock outputs 6 4 number of external clock output s three differential/six single-ended (6) number of feedback clock inputs o ne single-ended or differential (7) , ( 8 ) notes to table 2?10 : (1) for enhanced plls, m ranges from 1 to 256, while n and post-scale counters range from 1 to 512 with 50% duty cycle. (2) for fast plls, m , and post-scale counters range from 1 to 32. the n counter ranges from 1 to 4. (3) the smallest phase shif t is determined by the voltage controlle d oscillator (vco) period divided by 8. (4) for degree increments, stratix ii device s can shift all output frequencies in in crements of at least 45. smaller degree increments are possible depending on the frequency and divide parameters. (5) stratix ii fast plls only support manual clock switchover. (6) fast plls can drive to any i/o pin as an external clock. for high-speed differential i/o pins, the device uses a data channel to generate txclkout. (7) if the feedback input is used, you lose one (or two, if fbin is differential) external clock output pin. (8) every stratix ii device has at least two enhanced plls wi th one single-ended or differential external feedback input per pll.
2?60 altera corporation stratix ii device handbook, volume 1 may 2007 plls & clock networks figure 2?40 shows a top-level diagram of the stratix ii device and pll floorplan. figure 2?40. pll locations figures 2?41 and 2?42 shows the global and regi onal clocking from the fast pll outputs and the side clock pins. fpll7clk fpll10clk fpll9clk clk[8..11] fpll8clk clk[3..0] 7 1 2 8 10 4 3 9 5 11 6 12 clk[7..4] clk[15..12] plls
altera corporation 2?61 may 2007 stratix ii device handbook, volume 1 stratix ii architecture figure 2?41. global & regional clock c onnections from cent er clock pins & fast pll outputs note (1) notes to figure 2?41 : (1) ep2s15 and ep2s30 devices only have four fast plls (1, 2, 3, and 4), but the connectivity from these four plls to th e global and regional clock networks remains the same as shown. (2) the global or regional clocks in a fast pll's quadrant can drive the fast pll input. the global or regional clock input can be driven by an output from another pll, a pin-driven dedicated global or regional clock, or through a clock control block, provided the clock control block is fed by an output from another pll or a pin-driven dedicated global or regional clock. an internally generated global signal cannot drive the pll. c0 c1 c2 c3 fast pll 1 rck0 rck2 rck1 rck3 gck0 gck2 gck9 gck11 gck1 gck3 gck8 gck10 rck4 rck6 rck5 rck7 rck17 rck16 rck18 rck19 rck21 rck23 rck20 rck22 c0 c1 c2 c3 fast pll 2 logic array signal input to clock network clk0 clk1 clk2 clk3 c0 c1 c2 c3 fast pll 4 c0 c1 c2 c3 fast pll 3 clk11 clk10 clk9 clk8
2?62 altera corporation stratix ii device handbook, volume 1 may 2007 plls & clock networks figure 2?42. global & regional clock c onnections from corn er clock pins & fast pll outputs note (1) note to figure 2?42 : (1) the corner fast plls can also be driv en through the global or regional clock networks. the global or regional clock in put can be driven by an output from another pll, a pin-driven dedicated global or regional clock, or through a clock control block, provided the clock control block is fed by an output from another pll or a pin-driven dedicated global or regional clock. an internally generated global signal cannot drive the pll. c0 c1 c2 c3 fast pll 7 rck0 rck2 rck1 rck3 gck0 gck2 gck9 gck11 gck1 gck3 gck8 gck10 rck4 rck6 rck5 rck7 rck17 rck16 rck18 rck19 rck21 rck23 rck20 rck22 c0 c1 c2 c3 fast pll 8 c0 c1 c2 c3 fast pll 10 c0 c1 c2 c3 fast pll 9 fpll 7clk fpll 8clk fpll 10cl k fpll 9cl k
altera corporation 2?63 may 2007 stratix ii device handbook, volume 1 stratix ii architecture figure 2?43 shows the global and regional clocking from enhanced pll outputs and top and bottom clk pins. the connections to the global and regional clocks from the top clock pins and enhanced pll outputs is shown in table 2?11 . the connections to the cloc ks from the bottom clock pins is shown in table 2?12 .
2?64 altera corporation stratix ii device handbook, volume 1 may 2007 plls & clock networks figure 2?43. global & regional clock connections from top & bottom cl ock pins & enhanced pll outputs notes (1) , (2) , and (3) notes to figure 2?43 : (1) ep2s15 and ep2s30 devices only have two enhanced plls (5 and 6), but the connectivity from these two plls to the global and regional clock networks remains the same as shown. (2) if the design uses the feedback inpu t, you lose one (or two, if fbin is dif ferential) external clock output pin. (3) the enhanced plls can also be driven through the global or regional clock netowrks. the global or regional clock input can be driven by an output from another pll, a pi n-driven dedicated global or regional clock, or through a clock control block provided the clock control block is fed by an output from another pll or a pin-driven dedicated global or regional clock. an internally generated global signal cannot drive the pll. g15 g14 g13 g12 rclk31 rclk30 rclk29 rclk28 rclk27 rclk26 rclk25 rclk24 g7 g6 g5 g4 rclk15 rclk14 rclk13 rclk12 rclk11 rclk10 rclk9 rclk8 pll 6 clk7 clk6 clk5 clk4 pll 12 pll 5 c0 c1 c2 c3 c4 c5 c0 c1 c2 c3 c4 c5 c0 c1 c2 c3 c4 c5 c0 c1 c2 c3 c4 c5 clk14 clk15 clk13 clk12 pll 11 pll11_fb pll5_out[2..0]p pll5_out[2..0]n pll11_out[2..0]p pll11_out[2..0]n pll12_out[2..0]p pll12_out[2..0]n pll6_out[2..0]p pll6_out[2..0]n pll5_fb pll12_fb pll6_fb global clocks regional clocks regional clocks
altera corporation 2?65 may 2007 stratix ii device handbook, volume 1 stratix ii architecture table 2?11. global & regional clock connections from top clock pi ns & enhanced pll outputs (part 1 of 2) top side global & regional clock network connectivity dllclk clk12 clk13 clk14 clk15 rclk24 rclk25 rclk26 rclk27 rclk28 rclk29 rclk30 rclk31 clock pins clk12p vvv v v clk13p vvv v v clk14p vvvv v clk15p vvv vv clk12n vvv clk13n vv v clk14n vvv clk15n vvv drivers from internal logic gclkdrv0 v gclkdrv1 v gclkdrv2 v gclkdrv3 v rclkdrv0 vv rclkdrv1 vv rclkdrv2 vv rclkdrv3 vv rclkdrv4 vv rclkdrv5 vv rclkdrv6 vv rclkdrv7 vv enhanced pll 5 outputs c0 vvv v v c1 vvv v v c2 vvvv v c3 vvvvv
2?66 altera corporation stratix ii device handbook, volume 1 may 2007 plls & clock networks c4 vvvvv c5 v vvvv enhanced pll 11 outputs c0 vv v v c1 vv v v c2 vv v v c3 vvvv c4 vvvv c5 vvvv table 2?11. global & regional clock connections from top clock pi ns & enhanced pll outputs (part 2 of 2) top side global & regional clock network connectivity dllclk clk12 clk13 clk14 clk15 rclk24 rclk25 rclk26 rclk27 rclk28 rclk29 rclk30 rclk31 table 2?12. global & regional clock connections from bott om clock pins & enhanced pll outputs (part 1 of 2) bottom side global & regional clock network connectivity dllclk clk4 clk5 clk6 clk7 rclk8 rclk9 rclk10 rclk11 rclk12 rclk13 rclk14 rclk15 clock pins clk4p vvv v v clk5p vvv v v clk6p vvvv v clk7p vvvvv clk4n vvv clk5n vvv clk6n vvv clk7n vvv drivers from internal logic gclkdrv0 v gclkdrv1 v gclkdrv2 v
altera corporation 2?67 may 2007 stratix ii device handbook, volume 1 stratix ii architecture gclkdrv3 v rclkdrv0 vv rclkdrv1 vv rclkdrv2 vv rclkdrv3 vv rclkdrv4 vv rclkdrv5 vv rclkdrv6 vv rclkdrv7 vv enhanced pll 6 outputs c0 vvv v v c1 vvv v v c2 vvvv v c3 vvvvv c4 vvvvv c5 v vvvv enhanced pll 12 outputs c0 vv v v c1 vv v v c2 vv v v c3 vvvv c4 vvvv c5 vvvv table 2?12. global & regional clock connections from bott om clock pins & enhanced pll outputs (part 2 of 2) bottom side global & regional clock network connectivity dllclk clk4 clk5 clk6 clk7 rclk8 rclk9 rclk10 rclk11 rclk12 rclk13 rclk14 rclk15
2?68 altera corporation stratix ii device handbook, volume 1 may 2007 plls & clock networks enhanced plls stratix ii devices contain up to four enhanced plls with advanced clock management features. figure 2?44 shows a diagram of the enhanced pll. figure 2?44. stratix ii enhanced pll note (1) notes to figure 2?44 : (1) each clock source can come from any of the four clock pins that are physically located on the same side of the device as the pll. (2) if the feedback input is used, you lose one (or two, if fbin is differential) external clock output pin. (3) each enhanced pll has three differential external cloc k outputs or six single-ended external clock outputs. (4) the global or regional clock input can be driven by an output from another pll, a pi n-driven dedicated global or regional clock, or through a clock control block, provided the clock control block is fed by an output from another pll or a pin-driven dedicated global or regional clock. an internally generated global signal cannot drive the pll. /n charge pump vco /c2 /c3 /c4 /c0 8 4 6 4 global clocks /c1 lock detect to i/o or general routing inclk[3..0] fbin global or regional clock pfd /c5 from adjacent pll /m spread spectrum i/o buffers (3) (2) loop filter & filter post-scale counters clock switchover circuitry phase frequency detector vco phase selection selectable at each pll output port vco phase selection affecting all outputs shaded portions of the pll are reconfigurable regional clocks 8 6 (4)
altera corporation 2?69 may 2007 stratix ii device handbook, volume 1 stratix ii architecture fast plls stratix ii devices contain up to eight fast plls with high-speed serial interfacing ability. figure 2?45 shows a diagram of the fast pll. figure 2?45. stratix ii device fast pll notes (1) , (2) , (3) notes to figure 2?45 : (1) the global or regional clock input can be driven by an output from another pll, a pi n-driven dedicated global or regional clock, or through a clock control block, provided the clock control block is fed by an output from another pll or a pin-driven dedicated global or regional clock. an internally generated global signal cannot drive the pll. (2) in high-speed differential i/o support mode, this high-s peed pll clock feeds the serdes circuitry. stratix ii devices only support one rate of da ta transfer per fast pll in high-s peed differential i/o support mode. (3) this signal is a differential i/o serdes control signal. (4) stratix ii fast plls only support manual clock switchover. (5) if the design enables this 2 counter, then the device can use a vco frequency range of 150 to 520 mhz. f see the plls in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii device handbook or the stratix ii gx device handbook for more information on enha nced and fast plls. see ?high-speed differential i/o with dpa support? on page 2?96 for more information on high-speed differential i/o support. i/o structure the stratix ii ioes provide many features, including: dedicated differential and single-ended i/o buffers 3.3-v, 64-bit, 66-mhz pci compliance 3.3-v, 64-bit, 133-mhz pci-x 1.0 compliance joint test action group (jtag) boundary-scan test (bst) support on-chip driver series termination on-chip parallel termination on-chip termination for differential standards programmable pull-up during configuration charge pump vco c1 8 8 4 4 8 clock input pfd c0 m loop filter phase frequency detector vco phase selection selectable at each pll output port post-scale counters global clocks diffioclk1 load_en1 load_en0 diffioclk0 regional clocks to dpa block global or regional clock (1) global or regional clock (1) c2 k c3 n 4 clock switchover circuitry (4) shaded portions of the pll are reconfigurable (2) (2) (3) (3) (5)
2?70 altera corporation stratix ii device handbook, volume 1 may 2007 i/o structure output drive strength control tri-state buffers bus-hold circuitry programmable pull-up resistors programmable input and output delays open-drain outputs dq and dqs i/o pins double data rate (ddr) registers the ioe in stratix ii devices contains a bidirectional i/o buffer, six registers, and a latch for a complete embedded bidirectional single data rate or ddr transfer. figure 2?46 shows the stratix ii ioe structure. the ioe contains two input registers (plus a latch), two output registers, and two output enable registers. the desi gn can use both input registers and the latch to capture ddr input and both output registers to drive ddr outputs. additionally, the design can use the output enable (oe) register for fast clock-to-output enable timi ng. the negative edge-clocked oe register is used for ddr sdram interfacing. the quartus ii software automatically duplicates a single oe register that controls multiple output or bidirectional pins.
altera corporation 2?71 may 2007 stratix ii device handbook, volume 1 stratix ii architecture figure 2?46. stratix ii ioe structure the ioes are located in i/o blocks around the periphery of the stratix ii device. there are up to four ioes per row i/o block and four ioes per column i/o block. the row i/o blocks drive row, column, or direct link interconnects. the column i/o blocks drive column interconnects. figure 2?47 shows how a row i/o block connects to the logic array. figure 2?48 shows how a column i/o bloc k connects to th e logic array. dq output register output a dq output register output b input a input b dq oe register oe dq oe register dq input register dq input register dq input latch logic array clk ena
2?72 altera corporation stratix ii device handbook, volume 1 may 2007 i/o structure figure 2?47. row i/o block c onnection to the interconnect note (1) note to figure 2?47 : (1) the 32 data and control signals consist of eight data out lines: four lines each for ddr applications io_dataouta[3..0] and io_dataoutb[3..0] , four output enables io_oe[3..0] , four input clock enables io_ce_in[3..0] , four output clock enables io_ce_out[3..0] , four clocks io_clk[3..0] , four asynchronous clear and preset signals io_aclr/apreset[3..0] , and four synchronous clear and preset signals io_sclr/spreset[3..0] . 32 r4 & r24 interconnects c4 interconnect i/o block local interconnect 32 data & control signals from logic array (1) io_dataina[3..0] io_datainb[3..0] io_clk[7:0] horizontal i/o block contains up to four ioes direct link interconnect to adjacent lab direct link interconnect to adjacent lab lab local interconnect lab horizontal i/o block
altera corporation 2?73 may 2007 stratix ii device handbook, volume 1 stratix ii architecture figure 2?48. column i/o block connection to the interconnect note (1) note to figure 2?48 : (1) the 32 data and control signals consist of eight data out lines: four lines each for ddr applications io_dataouta[3..0] and io_dataoutb[3..0] , four output enables io_oe[3..0] , four input clock enables io_ce_in[3..0] , four output clock enables io_ce_out[3..0] , four clocks io_clk[3..0] , four asynchronous clear and preset signals io_aclr/apreset[3..0] , and four synchronous clear and preset signals io_sclr/spreset[3..0] . 32 data & control signals from logic array (1) vertical i/o block contains up to four ioes i/o block local interconnect io_dataina[3:0] io_datainb[3:0] r4 & r24 interconnects lab local interconnect c4 & c16 interconnects 32 lab lab lab io_clk[7..0] vertical i/o block
2?74 altera corporation stratix ii device handbook, volume 1 may 2007 i/o structure there are 32 control and data signals that feed each row or column i/o block. these control and data signals are driven from the logic array. the row or column ioe clocks, io_clk[7..0] , provide a dedicated routing resource for low-skew, high-speed cl ocks. i/o clocks are generated from global or regional clocks (see the ?plls & cloc k networks? section). figure 2?49 illustrates the signal pa ths through the i/o block. figure 2?49. signal path through the i/o block each ioe contains its own control signal selection for the following control signals: oe , ce_in , ce_out , aclr/apreset , sclr/spreset , clk_in , and clk_out . figure 2?50 illustrates the control signal selection. row or column io_clk[7..0] io_dataina io_datainb io_dataouta io_dataoutb io_oe oe ce_in ce_out io_ce_in aclr/apreset io_ce_out sclr/spreset io_sclr io_aclr clk_in io_clk clk_out control signal selection ioe to logic array from logic array to other ioes
altera corporation 2?75 may 2007 stratix ii device handbook, volume 1 stratix ii architecture figure 2?50. control signal selection per ioe notes to figure 2?50 : (1) control signals ce_in , ce_out , aclr/apreset , sclr/spreset , and oe can be global signals even though their control selection multiplexers are not directly fed by the ioe_clk[7..0] signals. the ioe_clk signals can drive the i/o local interconnect, which then dri ves the control selection multiplexers. in normal bidirectional operation, the input register can be used for input data requiring fast setup times. the input register can have its own clock input and clock enable separate from the oe and output registers. the output register can be used for da ta requiring fast clock-to-output performance. the oe register can be used for fast clock-to-output enable timing. the oe and output register share the same clock source and the same clock enable source from local interconnect in the associated lab, dedicated i/o clocks, and the column and row interconnects. clk_out ce_in clk_in ce_out aclr/apreset sclr/spreset dedicated i/o clock [7..0] local interconnect local interconnect local interconnect local interconnect local interconnect oe io_oe io_aclr local interconnect io_sclr io_ce_out io_ce_in io_clk
2?76 altera corporation stratix ii device handbook, volume 1 may 2007 i/o structure figure 2?51 shows the ioe in bidirectional configuration. figure 2?51. stratix ii io e in bidirectional i/o configuration note (1) notes to figure 2?51 : (1) all input signals to the io e can be inverted at the ioe. (2) the optional pci clamp is only available on column i/o pins. clrn/prn dq ena chip-wide reset oe register clrn/prn dq ena output register v ccio v ccio pci clamp (2) programmable pull-up resistor column, row, or local interconnect ioe_clk[7..0] bus-hold circuit oe register t co delay clrn/prn dq ena input register input pin to input register delay input pin to logic array delay drive strength control open-drain output on-chip termination sclr/spreset oe clkout ce_out aclr/apreset clkin ce_in output pin delay
altera corporation 2?77 may 2007 stratix ii device handbook, volume 1 stratix ii architecture the stratix ii device ioe includes programmable delays that can be activated to ensure input ioe register -to-logic array register transfers, input pin-to-logic array register transf ers, or output ioe register-to-pin transfers. a path in which a pin directly drives a register may require the delay to ensure zero hold time, whereas a path in which a pin drives a register through combinational logic may n ot require the delay. programmable delays exist for decreasing input-pin-to-logic-array and ioe input register delays. the quartus ii comp iler can program these delays to automatically mini mize setup time while prov iding a zero hold time. programmable delays can increase the register-to-pin delays for output and/or output enable registers. programmable delays are no longer required to ensure zero hold times fo r logic array register-to-ioe register transfers. the quartus ii compiler can create the zero hold time for these transfers. table 2?13 shows the programmable delays for stratix ii devices. the ioe registers in stratix ii devices share the same source for clear or preset. you can program preset or clea r for each individual ioe. you can also program the registers to power up high or low after configuration is complete. if programmed to power up low, an asynchronous clear can control the registers. if programmed to power up high, an asynchronous preset can control the registers. this feature prevents the inadvertent activation of another device's acti ve-low input upon power-up. if one register in an ioe uses a preset or clear signal then all registers in the ioe must use that same signal if they require preset or clear. additionally, a synchronous reset signal is available for the ioe registers. double data rate i/o pins stratix ii devices have six registers in the ioe, which support ddr interfacing by clocking data on both positive and negative clock edges. the ioes in stratix ii devices support ddr inputs, ddr outputs, and bidirectional ddr modes. table 2?13. stratix ii progr ammable delay chain programmable delays quartus ii logic option input pin to logic array delay input delay from pin to internal cells input pin to input register delay inpu t delay from pin to input register output pin delay delay from output register to output pin output enable register t co delay delay to output enable pin
2?78 altera corporation stratix ii device handbook, volume 1 may 2007 i/o structure when using the ioe for ddr inputs, th e two input registers clock double rate input data on alternating edges. an input latch is also used in the ioe for ddr input acquisition. the latch ho lds the data that is present during the clock high times. this allows both bits of data to be synchronous with the same clock edge (eit her rising or falling). figure 2?52 shows an ioe configured for ddr input. figure 2?53 shows the ddr input timing diagram. figure 2?52. stratix ii ioe in ddr input i/o configuration notes (1) , (2) , (3) notes to figure 2?52 : (1) all input signals to the io e can be inverted at the ioe. (2) this signal connection is only al lowed on dedicated dq function pins. (3) this signal is for dedicated dqs function pins only. (4) the optional pci clamp is only available on column i/o pins. clrn/prn dq ena chip-wide reset input register clrn/prn dq ena input register vccio vccio pci clamp (4) programmable pull-up resistor column, row, or local interconnect dqs local bus (2) to dqs logic block (3) ioe_clk[7..0] bus-hold circuit clrn/prn dq ena latch i nput pin to input registerdelay sclr/spreset clkin aclr/apreset on-chip termination ce_in
altera corporation 2?79 may 2007 stratix ii device handbook, volume 1 stratix ii architecture figure 2?53. input timing diagram in ddr mode when using the ioe for ddr output s, the two output registers are configured to clock two data paths from alms on risi ng clock edges. these output registers are multiplexed by the clock to drive the output pin at a 2 rate. one output register clocks the first bi t out on the clock high time, while the other output regist er clocks the second bit out on the clock low time. figure 2?54 shows the ioe configured for ddr output. figure 2?55 shows the ddr output timing diagram. data at input pin clk a0 b0 b1 a1 a1 b2 a2 a3 a2 a3 b1 a0 b0 b2 b3 b3 b4 input to logic array
2?80 altera corporation stratix ii device handbook, volume 1 may 2007 i/o structure figure 2?54. stratix ii ioe in ddr output i/o configuration notes (1) , (2) notes to figure 2?54 : (1) all input signals to the io e can be inverted at the ioe. (2) the tri-state buffer is active low. the ddio megafuncti on represents the tri-state buffer as active-high with an inverter at the oe register data port. similarly, the aclr and apreset signals are also active-high at the input ports of the ddio megafunction. (3) the optional pci clamp is only available on column i/o pins. clrn/prn dq ena chip-wide reset oe register clrn/prn dq ena oe register clrn/prn dq ena output register v ccio v ccio pci clamp (3) programmable pull-up resistor column, row, or local interconnect ioe_clk[7..0] bus-hold circuit oe register t co delay clrn/prn dq ena output register drive strength control open-drain output used for ddr, ddr2 sdram sclr/spreset aclr/apreset clkout output pin delay on-chip termination oe ce_out clk
altera corporation 2?81 may 2007 stratix ii device handbook, volume 1 stratix ii architecture figure 2?55. output timing diagram in ddr mode the stratix ii ioe operates in bidire ctional ddr mode by combining the ddr input and ddr output configur ations. the negative-edge-clocked oe register holds the oe si gnal inactive until the fa lling edge of the clock. this is done to meet ddr sdram timing requirements. external ram interfacing in addition to the si x i/o registers in each ioe, stratix ii devices also have dedicated phase-shift circuitry for interfacing with external memory interfaces. stratix ii devices support ddr and ddr2 sdram, qdr ii sram, rldram ii, and sdr sdram memory interfaces. in every stratix ii device, the i/o banks at the top (banks 3 and 4) and bottom (banks 7 and 8) of the device support dq and dqs signals with dq bus modes of 4, 8/9, 16/18, or 32/36. table 2?14 shows the number of dq and dqs buses that are supported per device. from internal registers ddr output clk b1 a1 b2 a2 b3 a3 b4 a4 a2 a1 a3 a4 b1 b2 b3 b4 table 2?14. dqs & dq bus mode support (part 1 of 2) note (1) device package number of 4 groups number of 8/9 groups number of 16/18 groups number of 32/36 groups ep2s15 484-pin fineline bga 8 4 0 0 672-pin fineline bga 18 8 4 0 ep2s30 484-pin fineline bga 8 4 0 0 672-pin fineline bga 18 8 4 0 ep2s60 484-pin fineline bga 8 4 0 0 672-pin fineline bga 18 8 4 0 1,020-pin fineline bga 36 18 8 4
2?82 altera corporation stratix ii device handbook, volume 1 may 2007 i/o structure a compensated delay element on ea ch dqs pin automatically aligns input dqs synchronization signals with the data window of their corresponding dq data signals. the dqs signals drive a local dqs bus in the top and bottom i/o banks. this dq s bus is an additional resource to the i/o clocks and is used to cloc k dq input registers with the dqs signal. the stratix ii device has two phase-shif ting reference circuits, one on the top and one on the bottom of the device. the circuit on the top controls the compensated delay elements for a ll dqs pins on the top. the circuit on the bottom controls the compensated delay elements for all dqs pins on the bottom. each phase-shifting reference circuit is driven by a system reference clock, which must have the same frequenc y as the dqs signal. clock pins clk[15..12]p feed the phase circuitry on the top of the device and clock pins clk[7..4]p feed the phase circuitr y on the bottom of the device. in addition, pll clock outputs can also feed the phase-shifting reference circuits. figure 2?56 illustrates the phase-shift reference circuit control of each dqs delay shift on the top of the devi ce. this same circuit is duplicated on the bottom of the device. ep2s90 484-pin hybrid fineline bga 8 4 0 0 780-pin fineline bga 18 8 4 0 1,020-pin fineline bga 36 18 8 4 1,508-pin fineline bga 36 18 8 4 ep2s130 780-pin fineline bga 18 8 4 0 1,020-pin fineline bga 36 18 8 4 1,508-pin fineline bga 36 18 8 4 ep2s180 1,020-pin fineline bga 36 18 8 4 1,508-pin fineline bga 36 18 8 4 notes to table 2?14 : (1) check the pin table for each dq s/dq group in the different modes. table 2?14. dqs & dq bus mode support (part 2 of 2) note (1) device package number of 4 groups number of 8/9 groups number of 16/18 groups number of 32/36 groups
altera corporation 2?83 may 2007 stratix ii device handbook, volume 1 stratix ii architecture figure 2?56. dqs phase- shift circuitry notes (1) , (2) , (3) , (4) notes to figure 2?56 : (1) there are up to 18 pairs of dqs and dqsn pins available on the top or the bottom of the stratix ii device. there are up to 10 pairs on the right side and 8 pairs on the left side of the dqs phase-shift circuitry. (2) the t module represents the dqs logic block. (3) clock pins clk[15..12]p feed the phase-shift circuitry on the top of the device and clock pins clk[7..4]p feed the phase circuitry on the bottom of the device. you can also use a pll clock output as a reference clock to the phase- shift circuitry. (4) you can only use pll 5 to feed the dqs phase-shift circ uitry on the top of the device and pll 6 to feed the dqs phase-shift circuitry on the bottom of the device. these dedicated circuits combined with enhanced pll clocking and phase-shift ability provide a complete hardware solution for interfacing to high-speed memory. f for more information on external memory interfaces, refer to the external memory inte rfaces in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii device handbook or the stratix ii gx device handbook . programmable drive strength the output buffer for each stratix i i device i/o pin has a programmable drive strength control for certain i/o standards. the lvttl, lvcmos, sstl, and hstl standards have several levels of drive strength that the user can control. the default setting us ed in the quartus ii software is the maximum current strength setting that is used to achieve maximum i/o performance. for all i/o standards, the minimum setting is the lowest drive strength that guarantees the i oh /i ol of the standard. using minimum settings provides signal sl ew rate control to reduce system noise and signal overshoot. dqs pin dqsn pin dqsn pin dqs pin dqs pin dqsn pin dqs pin dqsn pin from pll 5 (3) clk[15..12]p (2) to ioe to ioe to ioe to ioe to ioe to ioe to ioe t t t t t t t to ioe dqs phase-shift circuitry t dqs logic blocks
2?84 altera corporation stratix ii device handbook, volume 1 may 2007 i/o structure table 2?15 shows the possible settings fo r the i/o standards with drive strength control. open-drain output stratix ii devices provide an optional open-drain (equivalent to an open- collector) output for each i/o pin. this open-drain output enables the device to provide system-level control signals (e.g., interrupt and write- enable signals) that can be asse rted by any of several devices. bus hold each stratix ii device i/o pin provides an optional bus-hold feature. the bus-hold circuitry can weakly hold the signal on an i/o pin at its last-driven state. since the bus-hold feature holds the last-driven state of the pin until the next input signal is present, you do not need an external pull-up or pull-down resistor to hold a signal level when the bus is tri-stated. table 2?15. programmable drive strength note (1) i/o standard i oh / i ol current strength setting (ma) for column i/o pins i oh / i ol current strength setting (ma) for row i/o pins 3.3-v lvttl 24, 20, 16, 12, 8, 4 12, 8, 4 3.3-v lvcmos 24, 20, 16, 12, 8, 4 8, 4 2.5-v lvttl/lvcmos 16, 12, 8, 4 12, 8, 4 1.8-v lvttl/lvcmos 12, 10, 8, 6, 4, 2 8, 6, 4, 2 1.5-v lvcmos 8, 6, 4, 2 4, 2 sstl-2 class i 12, 8 12, 8 sstl-2 class ii 24, 20, 16 16 sstl-18 class i 12, 10, 8, 6, 4 10, 8, 6, 4 sstl-18 class ii 20, 18, 16, 8 - hstl-18 class i 12, 10, 8, 6, 4 12, 10, 8, 6, 4 hstl-18 class ii 20, 18, 16 - hstl-15 class i 12, 10, 8, 6, 4 8, 6, 4 hstl-15 class ii 20, 18, 16 - note to table 2?15 : (1) the quartus ii software default current setting is the maximum setting for each i/o standard.
altera corporation 2?85 may 2007 stratix ii device handbook, volume 1 stratix ii architecture the bus-hold circuitry also pulls undriven pins away from the input threshold voltage where noise can cause unintended high-frequency switching. you can select this featur e individually for each i/o pin. the bus-hold output drives no higher than v ccio to prevent overdriving signals. if the bus-hold feature is enabled, the programmable pull-up option cannot be used. disable the bu s-hold feature when the i/o pin has been configured for differential signals. the bus-hold circuitry uses a resistor with a nominal resistance (r bh ) of approximately 7 k to weakly pull the signal level to the last-driven state. see the dc & switching characteristics chapter in the stratix ii device handbook, volume 1 , for the specific sustaining current driven through this resistor and overdrive current used to identify the next-driven input level. this information is provided for each v ccio voltage level. the bus-hold circuitry is active only after configuration. when going into user mode, the bus-hold circuit captures the value on the pin present at the end of configuration. programmable pull-up resistor each stratix ii device i/o pin pr ovides an optional programmable pull-up resistor during user mode. if you enable this feature for an i/o pin, the pull-up resistor (typically 25 k ) weakly holds the output to the v ccio level of the output pin?s bank. programmable pull-up resistors are only supported on user i/o pins, and are not supported on dedicated co nfiguration pins, jtag pins or dedicated clock pins. advanced i/o standard support stratix ii device ioes support the following i/o standards: 3.3-v lvttl/lvcmos 2.5-v lvttl/lvcmos 1.8-v lvttl/lvcmos 1.5-v lvcmos 3.3-v pci 3.3-v pci-x mode 1 lvds lvpecl (on input and output clocks only) hypertransport technology differential 1.5-v hstl class i and ii differential 1.8-v hstl class i and ii differential sstl-18 class i and ii differential sstl-2 class i and ii
2?86 altera corporation stratix ii device handbook, volume 1 may 2007 i/o structure 1.5-v hstl class i and ii 1.8-v hstl class i and ii 1.2-v hstl sstl-2 class i and ii sstl-18 class i and ii table 2?16 describes the i/o standards supported by stratix ii devices. table 2?16. stratix ii supported i/o standards (part 1 of 2) i/o standard type input reference voltage (v ref ) (v) output supply voltage (v ccio ) (v) board termination voltage (v tt ) (v) lvttl single-ended - 3.3 - lvcmos single-ended - 3.3 - 2.5 v single-ended - 2.5 - 1.8 v single-ended - 1.8 - 1.5-v lvcmos single-ended - 1.5 - 3.3-v pci single-ended - 3.3 - 3.3-v pci-x mode 1 single-ended - 3.3 - lvds differential - 2.5 (3) - lvpecl (1) differential - 3.3 - hypertransport technology differential - 2.5 - differential 1.5-v hstl class i and ii (2) differential 0.75 1.5 0.75 differential 1.8-v hstl class i and ii (2) differential 0.90 1.8 0.90 differential sstl-18 class i and ii (2) differential 0.90 1.8 0.90 differential sstl-2 class i and ii (2) differential 1.25 2.5 1.25 1.2-v hstl (4) voltage-referenced 0.6 1.2 0.6 1.5-v hstl class i and ii voltage-referenced 0.75 1.5 0.75 1.8-v hstl class i and ii voltage-referenced 0.9 1.8 0.9 sstl-18 class i and ii voltage-referenced 0.90 1.8 0.90
altera corporation 2?87 may 2007 stratix ii device handbook, volume 1 stratix ii architecture f for more information on i/o stan dards supported by stratix ii i/o banks, refer to the selectable i/o standards in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii device handbook or the stratix ii gx device handbook . stratix ii devices contain eight i/o ba nks and four enhanced pll external clock output banks, as shown in figure 2?57 . the four i/o banks on the right and left of the device contai n circuitry to su pport high-speed differential i/o for lvds and hypert ransport inputs an d outputs. these banks support all stratix ii i/o standards except pci or pci-x i/o pins, and sstl-18 class ii and hstl outputs. the top and bottom i/o banks support all single-ended i/o standards. additionally, enhanced pll external clock output banks allow clock output capabilities such as differential support for sstl and hstl. sstl-2 class i and ii voltage-referenced 1.25 2.5 1.25 notes to table 2?16 : (1) this i/o standard is only available on input and output column clock pins. (2) this i/o standard is only available on input clock pins and dqs pins in i/o banks 3, 4, 7, and 8, and output clock pins in i/o banks 9,10, 11, and 12. (3) v ccio is 3.3 v when using this i/o standard in input and ou tput column clock pins (in i/o banks 9, 10, 11, and 12). the clock input pins supporting lvds on banks 3, 4, 7, and 8 use v ccint for lvds input operations and have no dependency on the v ccio level of the bank. (4) 1.2-v hstl is only support ed in i/o banks 4,7, and 8. table 2?16. stratix ii supported i/o standards (part 2 of 2) i/o standard type input reference voltage (v ref ) (v) output supply voltage (v ccio ) (v) board termination voltage (v tt ) (v)
2?88 altera corporation stratix ii device handbook, volume 1 may 2007 i/o structure figure 2?57. strati x ii i/o banks notes (1) , (2) , (3) , (4) notes to figure 2?57 : (1) figure 2?57 is a top view of the silicon die that corresponds to a reverse view for flip-chip packages. it is a graphical representation only. (2) depending on the size of the device, differen t device members have different numbers of v ref groups. refer to the pin list and the quartus ii so ftware for exact locations. (3) banks 9 through 12 are enhanced pll external cloc k output banks. these pll banks utilize the adjacent v ref group when voltage-referenced standards ar e implemented. for example, if an sstl input is implemented in pll bank 10, the voltage level at vrefb7 is the reference voltage level for the sstl input. (4) horizontal i/o banks feature serdes and dpa circuitr y for high speed differenti al i/o standards. see the high speed differential i/o interfaces in stratix ii & stratix ii gx devices chapter of the stratix ii device handbook, volume 2 or the stratix ii gx device handbook, volume 2 for more information on differential i/o standards. bank 3 bank 4 bank 11 bank 9 pll11 pll5 pll7 pll1 pll2 pll4 pll3 pll10 i/o banks 7, 8, 10 & 12 support all single-ended i/o standards and differential i/o standards except for hypertransport technology for both input and output operations. i/o banks 3, 4, 9 & 11 support all single-ended i/o standards and differential i/o standards except for hypertransport technology for both input and output operations. vref0b3 vref1b3 vref2b3 vref3b3 vref4b3 vref0b4 vref1b4 vref2b4 vref3b4 vref4b4 bank 8 bank 7 bank 12 bank 10 pll12 pll6 pll8 pll9 vref4b8 vref3b8 vref2b8 vref1b8 vref0b8 vref4b7 vref3b7 vref2b7 vref1b7 vref0b7 vref3b 2 vref2b2 vref1b2 vref0b2 bank 2 vref3b1 vref2b1 vref1b1 vref0b1 bank 1 vref1b 5 vref2b5 vref3b5 vref4b5 bank 5 vref1b6 vref2b6 vref3b6 vref4b6 bank 6 vref4b2 vref0b5 vref4b1 vref0b6 dqs4t dqs3t dqs2t dqs1t dqs0t dqs4b dqs3b dqs2b dqs1b dqs0b dqs8b dqs7b dqs6b dqs5b dqs8t dqs7t dqs6t dqs5t this i/o bank supports lvds and lvpecl standards for input clock operations. differential hstl and differential sstl standards are supported for both input and output operations. this i/o bank supports lvds and lvpecl standards for input clock operations. differential hstl and differential sstl standards are supported for both input and output operations. this i/o bank supports lvds and lvpecl standards for input clock operations. differential hstl and differential sstl standards are supported for both input and output operations. this i/o bank supports lvds and lvpecl standards for input clock operations. differential hstl and differential sstl standards are supported for both input and output operations. i/o banks 1, 2, 5 & 6 support lvttl, lvcmos, 2.5-v, 1.8-v, 1.5-v, sstl-2, sstl-18 class i, hstl-18 class i, hstl-15 class i, lvds, and hypertransport standards for input and output operations. hstl-18 class ii, hstl-15-class ii, sstl-18 class ii standards are only supported for input operations.
altera corporation 2?89 may 2007 stratix ii device handbook, volume 1 stratix ii architecture each i/o bank has its own vccio pins. a single de vice can support 1.5-, 1.8-, 2.5-, and 3.3-v interfaces ; each bank can support a different v ccio level independently. each bank also has dedicated vref pins to support the voltage-referenced stan dards (such as sstl-2). the pll banks utilize the adjacent vref group when voltage-referenced standards are implemented. for example, if an sstl input is implemented in pll bank 10, the voltage level at vrefb7 is the reference voltage level for the sstl input. i/o pins that reside in pll banks 9 through 12 are powered by the vcc_pll < 5, 6, 11, or 12 > _out pins, respectively. the ep2s60f484, ep2s60f780, ep2s90h484, ep2s90f780, and ep2s130f780 devices do not support plls 11 and 12. therefore, any i/o pins that reside in bank 11 are powered by the vccio3 pin, and any i/o pins that reside in bank 12 are powered by the vccio8 pin. each i/o bank can support multiple standards with the same v ccio for input and output pins. each bank can support one v ref voltage level. for example, when v ccio is 3.3 v, a bank can support lvttl, lvcmos, and 3.3-v pci for inputs and outputs. on-chip termination stratix ii devices provide differential (for the lvds or hypertransport technology i/o standard), series, and parallel on-chip termination to reduce reflections and maintain signal integrity. on-chip termination simplifies board design by minimizing the number of external termination resistors required. termination can be placed inside the package, eliminating small stubs that can still lead to reflections. stratix ii devices provide four types of termination: differential termination (r d ) series termination (r s ) without calibration series termination (r s ) with calibration parallel termination (r t ) with calibration
2?90 altera corporation stratix ii device handbook, volume 1 may 2007 i/o structure table 2?17 shows the stratix ii on-chip te rmination support per i/o bank. table 2?17. on-chip termination support by i/o banks (part 1 of 2) on-chip termination support i /o standard support top & bottom banks left & right banks series termination without calibration 3.3-v lvttl vv 3.3-v lvcmos vv 2.5-v lvttl vv 2.5-v lvcmos vv 1.8-v lvttl vv 1.8-v lvcmos vv 1.5-v lvttl vv 1.5-v lvcmos vv sstl-2 class i and ii vv sstl-18 class i v v sstl-18 class ii v 1.8-v hstl class i vv 1.8-v hstl class ii v 1.5-v hstl class i vv 1.2-v hstl v
altera corporation 2?91 may 2007 stratix ii device handbook, volume 1 stratix ii architecture series termination with calibration 3.3-v lvttl v 3.3-v lvcmos v 2.5-v lvttl v 2.5-v lvcmos v 1.8-v lvttl v 1.8-v lvcmos v 1.5-v lvttl v 1.5-v lvcmos v sstl-2 class i and ii v sstl-18 class i and ii v 1.8-v hstl class i v 1.8-v hstl class ii v 1.5-v hstl class i v 1.2-v hstl v parallel termination with calibration sstl-2 class i and ii v sstl-18 class i and ii v 1.8-v hstl class i v 1.8-v hstl class ii v 1.5-v hstl class i and ii v 1.2-v hstl v differential termination (1) lv d s v hypertransport technology v note to table 2?17 : (1) clock pins clk1 , clk3 , clk9 , clk11 , and pins fpll[7..10]clk do not support differential on-chip termination. clock pins clk0 , clk2 , clk8 , and clk10 do support differential on-chi p termination. clock pins in the top and bottom banks ( clk[4..7, 12..15] ) do not support differential on-chip termination. table 2?17. on-chip termination support by i/o banks (part 2 of 2) on-chip termination support i /o standard support top & bottom banks left & right banks
2?92 altera corporation stratix ii device handbook, volume 1 may 2007 i/o structure differential on-chip termination stratix ii devices support internal differential termination with a nominal resistance value of 100 for lvds or hypertransport technology input receiver buffers. lvpecl input signals (supported on clock pins only) require an external termination resis tor. differential on-chip termination is supported across the full range of su pported differential data rates as shown in the dc & switching characteristics chapter in volume 1 of the stratix ii device handbook . f for more information on differential on-chip termination, refer to the high-speed differential i/ o interfaces with dpa in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii device handbook or the stratix ii gx device handbook . f for more information on tolerance specifications for differential on-chip termination, refer to the dc & switching characteristics chapter in volume 1 of the stratix ii device handbook. on-chip series termination without calibration stratix ii devices support driver impedance matching to provide the i/o driver with controlled output im pedance that closely matches the impedance of the transmission line . as a result, reflections can be significantly reduced. stratix ii devices support on-chip series termination for single-ended i/o standards with typical r s values of 25 and 50 . once matching impedance is selected, current drive strength is no longer selectable. table 2?17 shows the list of output standards that support on-chip series term ination without calibration. on-chip series termination with calibration stratix ii devices support on-chip series termination with calibration in column i/o pins in top and bottom bank s. there is one calibration circuit for the top i/o banks and one circui t for the bottom i/o banks. each on-chip series termination calibr ation circuit compares the total impedance of each i/o buffer to the external 25- or 50- resistors connected to the rup and rdn pins, and dynamically enables or disables the transistors until they match. cali bration occurs at the end of device configuration. once the calibration ci rcuit finds the correct impedance, it powers down and stops changing th e characteristics of the drivers. f for more information on series on-chip termination supported by stratix ii devices, refer to the selectable i/o standards in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii device handbook or the stratix ii gx device handbook .
altera corporation 2?93 may 2007 stratix ii device handbook, volume 1 stratix ii architecture f for more information on tolerance sp ecifications for on-chip termination with calibration, refer to the dc & switching characteristics chapter in volume 1 of the stratix ii device handbook . on-chip parallel termination with calibration stratix ii devices support on-chip para llel termination with calibration for column i/o pins only. there is one calibration circuit for the top i/o banks and one circuit for the bottom i/o banks. each on-chip parallel termination calibration circuit compar es the total impedance of each i/o buffer to the external 50- resistors connected to the rup and rdn pins and dynamically enables or disables the transistors until they match. calibration occurs at the end of device configuration. once the calibration circuit finds the correct impedance, it powers down and stops changing the characteristic s of the drivers. 1 on-chip parallel termination with calibration is only supported for input pins. f for more information on on-chip te rmination supported by stratix ii devices, refer to the selectable i/o standards in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii device handbook or the stratix ii gx device handbook . f for more information on tolerance sp ecifications for on-chip termination with calibration, refer to the dc & switching characteristics chapter in volume 1 of the stratix ii device handbook. multivolt i/o interface the stratix ii architecture supports the multivolt i/o interface feature that allows stratix ii devices in all packages to interface with systems of different supply voltages. the stratix ii vccint pins must always be co nnected to a 1.2-v power supply. with a 1.2-v v ccint level, input pins are 1.5-, 1.8-, 2.5-, and 3.3-v tolerant. the vccio pins can be connected to either a 1.5-, 1.8-, 2.5-, or 3.3-v power supply, depending on th e output requirements. the output levels are compatible with systems of the same voltage as the power supply (for example, when vccio pins are connected to a 1.5-v power supply, the output levels are co mpatible with 1.5-v systems). the stratix ii vccpd power pins must be co nnected to a 3.3-v power supply. these power pins are used to supply the pre-driver power to the output buffers, which increases the performance of the output pins. the vccpd pins also power configuration input pins and jtag input pins.
2?94 altera corporation stratix ii device handbook, volume 1 may 2007 i/o structure table 2?18 summarizes stratix ii multivolt i/o support. the tdo and nceo pins are powered by v ccio of the bank that they reside in. tdo is in i/o bank 4 and nceo is in i/o bank 7. ideally, the v cc supplies for the i/o buffers of any two connected pins are at the same voltage level. this may not always be possible depending on the v ccio level of tdo and nceo pins on master devices and the configuration voltage level chosen by vccsel on slave devices. master and slave devices can be in any position in the chain. master indicates that it is driving out tdo or nceo to a slave device. for multi-device passive configuration schemes, the nceo pin of the master device drives the nce pin of the slave device. the vccsel pin on the slave device selects which input buffer is used for nce . when vccsel is logic high, it selects the 1. 8-v/1.5-v buffer powered by v ccio . when vccsel is logic low it selects the 3.3-v/2.5-v input buffer powered by v ccpd . the ideal case is to have the v ccio of the nceo bank in a master device match the vccsel settings for the nce input buffer of the slave device it is connected to, but that may not be possible depending on the application. table 2?19 contains board design recommendations to ensure that nceo can successfully drive nce for all power supply combinations. table 2?18. stratix ii mu ltivolt i/o support note (1) v ccio (v) input signal (v) output signal (v) 1.2 1.5 1.8 2.5 3.3 1.2 1.5 1.8 2.5 3.3 5.0 1.2 (4) v (2) v (2) v (2) v (2) v (4) 1.5 (4) vvv (2) v (2) v (3) v 1.8 (4) v vv (2) v (2) v (3) v (3) v 2.5 (4) vvv (3) v (3) v (3) v 3.3 (4) v vv (3) v (3) v (3) v (3) vv notes to table 2?18 : (1) to drive inputs higher than v ccio but less than 4.0 v, disable the pci clamping diode and select the allow lvttl and lvcmos input levels to overdrive input buffer option in the quartus ii software. (2) the pin current may be slightly higher than the de fault value. you must verify that the driving device?s v ol maximum and v oh minimum voltages do not viol ate the applicable stratix ii v il maximum and v ih minimum voltage specifications. (3) although v ccio specifies the voltage necessary for the stratix ii de vice to drive out, a receiving device powered at a different level can still interface with the stratix ii device if it has inputs that tolerate the v ccio value. (4) stratix ii devices do not support 1.2-v lvttl and 1.2-v lvcmos. stratix ii de vices support 1.2-v hstl.
altera corporation 2?95 may 2007 stratix ii device handbook, volume 1 stratix ii architecture for jtag chains, the tdo pin of the first device drives the tdi pin of the second device in the chain. the v ccsel input on jtag input i/o cells ( tck , tms , tdi , and trst ) is internally hardwired to gnd selecting the 3.3-v/2.5-v input buffer powered by v ccpd . the ideal case is to have the v ccio of the tdo bank from the first device to match the v ccsel settings for tdi on the second device, but that may not be possible depending on the application. table 2?20 contains board design recommendations to ensure proper jtag chain operation. table 2?19. board design recommendations for nceo nce input buffer power in i/o bank 3 stratix ii nceo v ccio voltage level in i/o bank 7 v ccio = 3.3 v v ccio = 2.5 v v ccio = 1.8 v v ccio = 1.5 v v ccio = 1.2 v vccsel high (v ccio bank 3 = 1.5 v) v (1) , (2) v (3) , (4) v (5) vv vccsel high (v ccio bank 3 = 1.8 v) v (1) , (2) v (3) , (4) vv level shifter required vccsel low (nce powered by v ccpd = 3.3v) v v (4) v (6) level shifter required level shifter required notes to table 2?19 : (1) input buffer is 3.3-v tolerant. (2) the nceo output buffer meets v oh (min) = 2.4 v. (3) input buffer is 2.5-v tolerant. (4) the nceo output buffer meets v oh (min) = 2.0 v. (5) input buffer is 1.8-v tolerant. (6) an external 250- pull-up resistor is not required, but recommended if signal levels on the board are not optimal. table 2?20. supported tdo/tdi voltage combinations (part 1 of 2) device tdi input buffer power stratix ii tdo v ccio voltage level in i/o bank 4 v ccio = 3.3 v v ccio = 2.5 v v ccio = 1.8 v v ccio = 1.5 v v ccio = 1.2 v stratix ii always v ccpd (3.3v) v (1) v (2) v (3) level shifter required level shifter required
2?96 altera corporation stratix ii device handbook, volume 1 may 2007 high-speed differential i/o with dpa support high-speed differential i/o with dpa support stratix ii devices contain dedicated circuitry for supporting differential standards at speeds up to 1 gbps. the lvds and hypertransport differential i/o standards are supported in the stratix ii device. in addition, the lvpecl i/o standard is supported on input and output clock pins on the top and bottom i/o banks. the high-speed differential i/o ci rcuitry supports the following high speed i/o interconnect standards and applications: spi-4 phase 2 (pos-phy level 4) sfi-4 parallel rapidio hypertransport technology there are four dedicated high-spe ed plls in the ep2s15 to ep2s30 devices and eight dedicated high-speed plls in the ep2s60 to ep2s180 devices to multiply reference clocks and drive high-speed differential serdes channels. tables 2?21 through 2?26 show the number of channels that each fast pll can clock in each of the stratix ii devices. in tables 2?21 through 2?26 the first row for each transmitter or receiv er provides the number of channels driven directly by the pll. the second row below it shows the maximum channels a pll can drive if cross bank channels are used from the adjacent center pll. for example, in the 484-pin fineline bga ep2s15 non-stratix ii vcc = 3.3 v v (1) v (2) v (3) level shifter required level shifter required vcc = 2.5 v v (1) , (4) v (2) v (3) level shifter required level shifter required vcc = 1.8 v v (1) , (4) v (2) , (5) v level shifter required level shifter required vcc = 1.5 v v (1) , (4) v (2) , (5) v (6) vv notes to table 2?20 : (1) the tdo output buffer meets v oh (min) = 2.4 v. (2) the tdo output buffer meets v oh (min) = 2.0 v. (3) an external 250- pull-up resistor is not required, but recommended if signal levels on the board are not optimal. (4) input buffer must be 3.3-v tolerant. (5) input buffer must be 2.5-v tolerant. (6) input buffer must be 1.8-v tolerant. table 2?20. supported tdo/tdi voltage combinations (part 2 of 2) device tdi input buffer power stratix ii tdo v ccio voltage level in i/o bank 4 v ccio = 3.3 v v ccio = 2.5 v v ccio = 1.8 v v ccio = 1.5 v v ccio = 1.2 v
altera corporation 2?97 may 2007 stratix ii device handbook, volume 1 stratix ii architecture device, pll 1 can drive a maximum of 10 transmitter channels in i/o bank 1 or a maximum of 19 transmitter channels in i/o banks 1 and 2. the quartus ii software may also merge re ceiver and transmitter plls when a receiver is driving a transmitter. in this case, one fast pll can drive both the maximum numbers of receiver and transmitter channels. table 2?21. ep2s15 device differential channels note (1) package transmitter/ receiver total channels center fast plls pll 1 pll 2 pll 3 pll 4 484-pin fineline bga transmitter 38 (2) 10 9 9 10 (3) 19 19 19 19 receiver 42 (2) 11 10 10 11 (3) 21 21 21 21 672-pin fineline bga transmitter 38 (2) 10 9 9 10 (3) 19 19 19 19 receiver 42 (2) 11 10 10 11 (3) 21 21 21 21 table 2?22. ep2s30 device differential channels note (1) package transmitter/ receiver total channels center fast plls pll 1 pll 2 pll 3 pll 4 484-pin fineline bga transmitter 38 (2) 10 9 9 10 (3) 19 19 19 19 receiver 42 (2) 11 10 10 11 (3) 21 21 21 21 672-pin fineline bga transmitter 58 (2) 16 13 13 16 (3) 29 29 29 29 receiver 62 (2) 17 14 14 17 (3) 31 31 31 31
2?98 altera corporation stratix ii device handbook, volume 1 may 2007 high-speed differential i/o with dpa support table 2?23. ep2s60 differential channels note (1) package transmitter/ receiver total channels center fast plls corner fast plls (4) pll 1 pll 2 pll 3 pll 4 pll 7 pll 8 pll 9 pll 10 484-pin fineline bga transmitter 38 (2) 10 9 9 10 10 9 9 10 (3) 19 19 19 19 - - - - receiver 42 (2) 11 10 10 11 11 10 10 11 (3) 21 21 21 21 - - - - 672-pin fineline bga transmitter 58 (2) 16 13 13 16 16 13 13 16 (3) 29 29 29 29 - - - - receiver 62 (2) 17 14 14 17 17 14 14 17 (3) 31 31 31 31 - - - - 1,020-pin fineline bga transmitter 84 (2) 21 21 21 21 21 21 21 21 (3) 42 42 42 42 - - - - receiver 84 (2) 21 21 21 21 21 21 21 21 (3) 42 42 42 42 - - - - table 2?24. ep2s90 differential channels note (1) package transmitter/ receiver total channels center fast plls corner fast plls (4) pll 1 pll 2 pll 3 pll 4 pll 7 pll 8 pll 9 pll 10 484-pin hybrid fineline bga transmitter 38 (2) 10 9 9 10 - - - - (3) 19 19 19 19 - - - - receiver 42 (2) 11 10 10 11 - - - - (3) 21 21 21 21 - - - - 780-pin fineline bga transmitter 64 (2) 16 16 16 16 - - - (3) 32 32 32 32 - - - - receiver 68 (2) 17 17 17 17 - - - - (3) 34 34 34 34 - - - 1,020-pin fineline bga transmitter 90 (2) 23 22 22 23 23 22 22 23 (3) 45 45 45 45 - - - - receiver 94 (2) 23 24 24 23 23 24 24 23 (3) 46 46 46 46 - - - - 1,508-pin fineline bga transmitter 118 (2) 30 29 29 30 30 29 29 30 (3) 59 59 59 59 - - - - receiver 118 (2) 30 29 29 30 30 29 29 30 (3) 59 59 59 59 - - - -
altera corporation 2?99 may 2007 stratix ii device handbook, volume 1 stratix ii architecture table 2?25. ep2s130 differential channels note (1) package transmitter/ receiver total channels center fast plls corner fast plls (4) pll 1 pll 2 pll 3 pll 4 pll 7 pll 8 pll 9 pll 10 780-pin fineline bga transmitter 64 (2) 16 16 16 16 - - - (3) 32 32 32 32 - - - - receiver 68 (2) 17 17 17 17 - - - - (3) 34 34 34 34 - - - 1,020-pin fineline bga transmitter 88 (2) 22 22 22 22 22 22 22 22 (3) 44 44 44 44 - - - - receiver 92 (2) 23 23 23 23 23 23 23 23 (3) 46 46 46 46 - - - - 1,508-pin fineline bga transmitter 156 (2) 37 41 41 37 37 41 41 37 (3) 78 78 78 78 - - - - receiver 156 (2) 37 41 41 37 37 41 41 37 (3) 78 78 78 78 - - - - table 2?26. ep2s180 differential channels note (1) package transmitter/ receiver total channels center fast plls corner fast plls (4) pll 1 pll 2 pll 3 pll 4 pll 7 pll 8 pll 9 pll 10 1,020-pin fineline bga transmitter 88 (2) 22 22 22 22 22 22 22 22 (3) 44 44 44 44 - - - - receiver 92 (2) 23 23 23 23 23 23 23 23 (3) 46 46 46 46 - - - - 1,508-pin fineline bga transmitter 156 (2) 37 41 41 37 37 41 41 37 (3) 78 78 78 78 - - - - receiver 156 (2) 37 41 41 37 37 41 41 37 (3) 78 78 78 78 - - - - notes to tables 2?21 to 2?26 : (1) the total number of receiver channels includes the four non-dedicated clock channels that can be optionally used as data channels. (2) this is the maximum number of channels the plls can directly drive. (3) this is the maximum number of channels if the device uses cross bank channels from the adjacent center pll. (4) the channels accessible by the cent er fast pll overlap with the channels accessible by the corner fast pll. therefore, the total number of channels is not the addition of the number of channels accessible by plls 1, 2, 3, and 4 with the number of channels accessible by plls 7, 8, 9, and 10.
2?100 altera corporation stratix ii device handbook, volume 1 may 2007 high-speed differential i/o with dpa support dedicated circuitry with dpa support stratix ii devices support source-synchronous interfacing with lvds or hypertransport signaling at up to 1 gbps. stratix ii devices can transmit or receive serial channels along with a low-speed or high-speed clock. the receiving device pll multiplies the clock by an integer factor w = 1 through 32. for example, a hypert ransport technology application where the data rate is 1,000 mbps and the clock rate is 500 mhz would require that w be set to 2. the serdes factor j determines the parallel data width to deserialize from receiv ers or to serialize for transmitters. the serdes factor j can be set to 4, 5, 6, 7, 8, 9, or 10 and does not have to equal the pll clock-multiplication w value. a design using the dynamic phase aligner also supports all of these j factor values. for a j factor of 1, the stratix ii device bypasses the serdes block. for a j factor of 2, the stratix ii device bypasses the serd es block, and the ddr input and output registers are used in the ioe. figure 2?58 shows the block diagram of the stratix ii transmitter channel. figure 2?58. stratix ii transmitter channel each stratix ii receiver channel features a dpa block for phase detection and selection, a serdes, a synchronizer , and a data realigner circuit. you can bypass the dynamic phase aligner without affecting the basic source- synchronous operation of the channel. in addition, you can dynamically switch between using the dpa block or bypassing the block via a control signal from the logic array. figure 2?59 shows the block diagram of the stratix ii receiver channel. fast pll refclk diffioclk dedicated transmitter interface local interconnect 10 + ? up to 1 gbps load_en regional or global clock data from r4, r24, c4, or direct link interconnect 10
altera corporation 2?101 may 2007 stratix ii device handbook, volume 1 stratix ii architecture figure 2?59. stratix ii receiver channel an external pin or global or regional clock can drive the fast plls, which can output up to three clocks: two mu ltiplied high-speed clocks to drive the serdes block and/or external pin, and a low-speed clock to drive the logic array. in addition, eight phase- shifted clocks from the vco can feed to the dpa circuitry. f for more information on the fast pll, see the plls in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii device handbook or the stratix ii gx device handbook . the eight phase-shifted clocks from th e fast pll feed to the dpa block. the dpa block selects the closest phase to the center of the serial data eye to sample the incoming data. this allows the source-synchronous circuitry to capture incoming data co rrectly regardless of the channel-to- channel or clock-to-channel skew. th e dpa block locks to a phase closest to the serial data phase. the phase- aligned dpa clock is used to write the data into the synchronizer. the synchronizer sits between the dpa block and the data realignment and serdes circuitry. since every channel utilizing the dpa block can have a different phase selected to sa mple the data, the synchronizer is needed to synchronize th e data to the high-speed clock domain of the data realignment and the serdes circuitry. + ? fast pll refclk load_en diffioclk regional or global clock data to r4, r24, c4, or direct link interconnect up to 1 gbps 10 dedicated receiver interface eight phase clocks data retimed_data dpa_clk dpa synchronizer 8 dq data realignment circuitry
2?102 altera corporation stratix ii device handbook, volume 1 may 2007 high-speed differential i/o with dpa support for high-speed source synchronous interfaces such as pos-phy 4, parallel rapidio, and hypertransport , the source synchr onous clock rate is not a byte- or serdes-rate multiple of the data rate. byte alignment is necessary for these protocols since th e source synchronous clock does not provide a byte or word boundary since the clock is one half the data rate, not one eighth. the stratix ii device ?s high-speed differential i/o circuitry provides dedicated data realignment circuitry for user- controlled byte boundary shifting. this simplifies designs while saving alm resources. you can use an alm-based state machine to signal the shift of receiver byte boundaries until a specified pattern is detected to indicate byte alignment. fast pll & channel layout the receiver and transmitter channels are interleaved such that each i/o bank on the left and right side of th e device has one receiver channel and one transmitter channel per lab row. figure 2?60 shows the fast pll and channel layout in the ep 2s15 and ep2s30 devices. figure 2?61 shows the fast pll and channel layout in the ep2s60 to ep2s180 devices. figure 2?60. fast pll & channel layout in the ep2s15 & ep2s30 devices note (1) note to figure 2?60 : (1) see table 2?21 for the number of channels each device supports. lvds clock dpa clock fast pll 1 fast pll 2 lvds clock dpa clock lvds clock dpa clock fast pll 4 fast pll 3 lvds clock dpa clock quadrant quadrant quadrant quadrant 4 4 4 4 4 4 2 2 2 2
altera corporation 2?103 may 2007 stratix ii device handbook, volume 1 stratix ii architecture figure 2?61. fast pll & channel layout in the ep2s60 to ep2s180 devices note (1) note to figure 2?61 : (1) see tables 2?22 through 2?26 for the number of channe ls each device supports. lvds clock dpa clock fast pll 1 fast pll 2 lvds clock dpa clock lvds clock dpa clock fast pll 4 fast pll 7 fast pll 10 fast pll 3 lvds clock dpa clock quadrant quadrant quadrant quadrant 4 4 2 4 4 4 4 2 2 2 2 2 fast pll 8 fast pll 9 2 2
2?104 altera corporation stratix ii device handbook, volume 1 may 2007 document revision history document revision history table 2?27 shows the revision history for this chapter. table 2?27. document revision history (part 1 of 2) date and document version changes made summary of changes may 2007, v4.3 updated ?clock control block? section. ? updated note in the ?clock control block? section. ? deleted tables 2-11 and 2-12. ? updated notes to: figure 2?41 figure 2?42 figure 2?43 figure 2?45 ? updated notes to table 2?18 . ? moved document revision history to end of the chapter. ? august 2006, v4.2 updated table 2?18 with note. ? april 2006, v4.1 updated table 2?13. removed note 2 from table 2?16. updated ?on-chip termination? section and table 2?19 to include parallel termination wi th calibration information. added new ?on-chip parallel termination with calibration? section. updated figure 2?44. added parallel on- chip termination description and specification. changed rclk names to match the quartus ii software in table 2?13. december 2005, v4.0 updated ?clock control block? section. ? july 2005, v3.1 updated hypertransport technology information in table 2?18. updated hypertransport technology information in figure 2?57. added information on the a synchronous clear signal. ? may 2005, v3.0 updated ?functional description? section. updated table 2?3. updated ?clock control block? section. updated tables 2?17 through 2?19. updated tables 2?20 through 2?22. updated figure 2?57. ? march 2005, 2.1 updated ?functional description? section. updated table 2?3. ?
altera corporation 2?105 may 2007 stratix ii device handbook, volume 1 stratix ii architecture january 2005, v2.0 updated the ?multivolt i/o interface? and ?trimatrix memory? sections. updated tables 2?3, 2?17, and 2?19. ? october 2004, v1.2 updated tables 2?9, 2?16, 2?26, and 2?27. ? july 2004, v1.1 updated note to tables 2?9 and 2?16. updated tables 2?16, 2?17, 2?18, 2?19, and 2?20. updated figures 2?41, 2?42, and 2?57. removed 3 from list of serdes factor j . updated ?high-speed differential i/o with dpa support? section. in ?dedicated circuitry with dpa support? section, removed xsbi and changed rapidio to parallel rapidio. ? february 2004, v1.0 added document to the stratix ii device handbook. ? table 2?27. document revision history (part 2 of 2) date and document version changes made summary of changes
2?106 altera corporation stratix ii device handbook, volume 1 may 2007 document revision history
altera corporation 3?1 may 2007 3. configuration & testing ieee std. 1149.1 jtag boundary- scan support all stratix ? ii devices provide joint test action group (jtag) boundary-scan test (bst) circuitry that complies with the ieee std. 1149.1. jtag boundary-scan testing can be performed either before or after, but not during configuratio n. stratix ii devices can also use the jtag port for configuration with the quartus ? ii software or hardware using either jam files ( .jam ) or jam byte-code files ( .jbc ). stratix ii devices support ioe i/o standard setting reconfiguration through the jtag bst chain. the jtag chain can update the i/o standard for all input and output pins any time before or during user mode through the config_io instruction. you can use this capability for jtag testing before configuratio n when some of the stratix ii pins drive or receive from other devices on the board using voltage-referenced standards. because the stratix ii devi ce may not be configured before jtag testing, the i/o pins may not be configured for appropriate electrical standards for chip-to-chip communication. programming those i/o standards via jtag allows you to fully test i/o connections to other devices. a device operating in jtag mode uses four required pins, tdi , tdo , tms , and tck , and one optional pin, trst . the tck pin has an internal weak pull-down resistor, while the tdi , tms and trst pins have weak internal pull-ups. the jtag input pins are powered by the 3.3-v vccpd pins. the tdo output pin is powered by the v ccio power supply of bank 4. stratix ii devices also use the jtag po rt to monitor the logic operation of the device with the signaltap ? ii embedded logic analyzer. stratix ii devices support the jtag instructions shown in table 3?1 . 1 stratix ii, stra tix, cyclone ? ii, and cyclone devices must be within the first 17 devices in a jt ag chain. all of these devices have the same jtag controller. if any of the stratix ii, stratix, cyclone ii, or cyclone devices are in the 18th of further position, they fail configuration. this does not affect signaltap ii. the stratix ii device instruction re gister length is 10 bits and the usercode register length is 32 bits. tables 3?2 and 3?3 show the boundary-scan register length and device idcode information for stratix ii devices. sii51003-4.2
3?2 altera corporation stratix ii device handbook, volume 1 may 2007 ieee std. 1149.1 jtag boundary-scan support table 3?1. stratix ii jtag instructions jtag instruction instr uction code description sample/preload 00 0000 0101 allows a snapshot of signals at t he device pins to be captured and examined during normal device operation, and permits an initial data pattern to be output at the device pins. also used by the signaltap ii embedded logic analyzer. extest (1) 00 0000 1111 allows the external circuitry and board-level interconnects to be tested by forcing a test pattern at the output pins and capturing test results at the input pins. bypass 11 1111 1111 places the 1-bit bypass register between the tdi and tdo pins, which allows the bst data to pass synchronously through selected devices to adjacent devices during normal device operation. usercode 00 0000 0111 selects the 32-bit usercode register and places it between the tdi and tdo pins, allowing the usercode to be serially shifted out of tdo . idcode 00 0000 0110 selects the idcode register and places it between tdi and tdo , allowing the idcode to be serially shifted out of tdo . highz (1) 00 0000 1011 places the 1-bit bypass register between the tdi and tdo pins, which allows the bst data to pass synchronously through selected devices to adjacent devices during normal device operation, while tri-stating all of the i/o pins. clamp (1) 00 0000 1010 places the 1-bit bypass register between the tdi and tdo pins, which allows the bst data to pass synchronously through selected devices to adjacent devices during normal device operation while holding i/o pins to a state defined by the data in the boundary-scan register. icr instructions used when configuring a stra tix ii device via the jtag port with a usb blaster, masterblaster?, byteblastermv?, or byteblaster ii download cable, or when using a .jam or .jbc via an embedded processor or jrunner. pulse_nconfig 00 0000 0001 emulates pulsing the nconfig pin low to trigger reconfiguration even though the physical pin is unaffected. config_io (2) 00 0000 1101 allows configuration of i/o standards through the jtag chain for jtag testing. can be executed before, during, or after configuration. stops configuration if executed during configuration. once issued, the config_io instruction holds nstatus low to reset the configuration device. nstatus is held low until the ioe configuration register is loaded and the tap controller state machine transitions to the update_dr state. signaltap ii instructions monitors internal device oper ation with the signaltap ii embedded logic analyzer. notes to ta b l e 3 ? 1 : (1) bus hold and weak pull-up resistor feat ures override the high-impedance state of highz , clamp , and extest . (2) for more informa tion on using the config_io instruction, see the morphio: an i/o reconfiguration solution for altera devices white paper .
altera corporation 3?3 may 2007 stratix ii device handbook, volume 1 configuration & testing the quartus ii software has an auto usercode feature where you can choose to use the checksum value of a programming file as the jtag user code. if selected, the checksum is automatically loaded to the usercode register. turn on the auto usercode option by clicking device & pin options , then general, in the settings dialog box (ass ignments menu). 1 stratix, stratix ii, cyclone, and cyclone ii devices must be within the first 17 devices in a jt ag chain. all of these devices have the same jtag controller. if any of the stratix, stratix ii, cyclone, and cyclone ii devices are in the 18th or after they fail configuration. this does not affect signaltap ii. table 3?2. stratix ii boundary-scan register length device boundary-scan register length ep2s15 1,140 ep2s30 1,692 ep2s60 2,196 ep2s90 2,748 ep2s130 3,420 ep2s180 3,948 table 3?3. 32-bit stratix ii device idcode device idcode (32 bits) (1) version (4 bits) part number (16 bits) manufacturer identity (11 bits) lsb (1 bit) (2) ep2s15 0000 0010 0000 1001 0001 000 0110 1110 1 ep2s30 0000 0010 0000 1001 0010 000 0110 1110 1 ep2s60 0001 0010 0000 1001 0011 000 0110 1110 1 ep2s90 0000 0010 0000 1001 0100 000 0110 1110 1 ep2s130 0000 0010 0000 1001 0101 000 0110 1110 1 ep2s180 0000 0010 0000 1001 0110 000 0110 1110 1 notes to ta b l e 3 ? 3 : (1) the most significant bit (msb) is on the left. (2) the idcode's least significant bit (lsb) is always 1.
3?4 altera corporation stratix ii device handbook, volume 1 may 2007 signaltap ii embedded logic analyzer f for more information on jtag, see the following documents: the ieee std. 1149.1 (jtag) boundary -scan testing for stratix ii & stratix ii gx devices chapter of the stratix ii devi ce handbook, volume 2 or the stratix ii gx device handbook, volume 2 jam programming & test language specification signaltap ii embedded logic analyzer stratix ii devices feature the signaltap ii embedded logic analyzer, which monitors design operation over a period of time through the ieee std. 1149.1 (jtag) circuitry. you can analyze internal logic at speed without bringing intern al signals to the i/o pi ns. this feature is particularly important for advanced packages, such as fineline bga ? packages, because it can be difficul t to add a connection to a pin during the debugging process after a board is designed and manufactured. configuration the logic, circuitry, and interconnect s in the stratix ii architecture are configured with cmos sram elements. altera ? fpga devices are reconfigurable and every device is tested with a high coverage production test program so you do not have to perform fault testing and can instead focus on simulation and design verification. stratix ii devices are configured at system power-up with data stored in an altera configuration device or provid ed by an external controller (e.g., a max ? ii device or microprocessor). stra tix ii devices can be configured using the fast passive parallel (fpp), ac tive serial (as), passive serial (ps), passive parallel asynchronous (ppa), and jtag configuration schemes. the stratix ii device?s optimized in terface allows microprocessors to configure it serially or in parallel , and synchronously or asynchronously. the interface also enables microproce ssors to treat stratix ii devices as memory and configure them by writ ing to a virtual memory location, making reconfiguration easy. in addition to the number of conf iguration methods su pported, stratix ii devices also offer the design security, decompression, and remote system upgrade features. the design securi ty feature, using configuration bitstream encryption and aes tech nology, provides a mechanism to protect your designs. the decompress ion feature allows stratix ii fpgas to receive a compressed configuration bitstream and decompress this data in real-time, reducing storage requirements and configuration time. the remote system upgrade feature allows real-time system upgrades from remote locations of your strati x ii designs. for more information, see ?configuration schemes? on page 3?7 .
altera corporation 3?5 may 2007 stratix ii device handbook, volume 1 configuration & testing operating modes the stratix ii architecture uses sram configuration elements that require configuration data to be loaded each time the circuit powers up. the process of physically loading the sr am data into the device is called configuration. during initialization, which occurs immediately after configuration, the device resets regist ers, enables i/o pins, and begins to operate as a logic device. the i/o pins are tri-stated during power-up, and before and during configuration. together, the configuration and initialization processes are called command mode. normal device operation is called user mode. sram configuration elements allow stratix ii devices to be reconfigured in-circuit by loading new configuratio n data into the device. with real- time reconfiguration, the device is forced into command mode with a device pin. the configuration process loads different configuration data, reinitializes the device, and resumes user-mode operation. you can perform in-field upgrades by distribu ting new configuration files either within the system or remotely. porsel is a dedicated input pin used to select por delay times of 12 ms or 100 ms during power-up. when the porsel pin is connected to ground, the por time is 100 ms; when the porsel pin is connected to v cc , the por time is 12 ms. the nio pullup pin is a dedicated input that chooses whether the internal pull-ups on the user i/o pins and dual-purpose configuration i/o pins ( ncso , asdo , data[7..0] , nws , nrs , rdynbsy , ncs , cs , runlu , pgm[2..0] , clkusr , init_done , dev_oe , dev_clr ) are on or off before and during configuration. a lo gic high (1.5, 1.8, 2.5, 3.3 v) turns off the weak internal pull-ups, while a logic low turns them on. stratix ii devices also of fer a new power supply, v ccpd , which must be connected to 3.3 v in order to power the 3.3-v/2.5-v buffer available on the configuration input pins and jtag pins. v ccpd applies to all the jtag input pins ( tck , tms , tdi , and trst ) and the configuration input pins when vccsel is connected to ground. see table 3?4 for more information on the pins affected by vccsel . the vccsel pin allows the v ccio setting (of the banks where the configuration inputs reside) to be independent of the voltage required by the configuration inputs. therefore, when selecting the v ccio , the v il and v ih levels driven to the configuration in puts do not have to be a concern.
3?6 altera corporation stratix ii device handbook, volume 1 may 2007 configuration the pll_ena pin and the configuration input pins ( table 3?4 ) have a dual buffer design: a 3.3-v/2.5-v in put buffer and a 1.8-v/1.5-v input buffer. the vccsel input pin selects which input buffer is used. the 3.3- v/2.5-v input buffer is powered by v ccpd, while the 1.8-v/1.5-v input buffer is powered by v ccio . table 3?4 shows the pins affected by vccsel . vccsel is sampled during power-up. therefore, the vccsel setting cannot change on the fly or during a reconfiguration. the vccsel input buffer is powered by v ccint and must be hardwired to v ccpd or ground. a logic high vccsel connection selects the 1.8-v/1.5-v input buffer, and a logic low selects the 3.3-v/2.5-v input buffer. vccsel should be set to comply with the logic levels driven out of the configuration device or max ? ii/microprocessor. if you need to support configuration input voltages of 3.3 v/2.5 v, you should set the vccsel to a logic low; you can set the v ccio of the i/o bank that contains the configuration inputs to any supported voltage. if table 3?4. pins affected by the voltage level at vccsel pin vccsel = low (connected to gnd) vccsel = high (connected to v ccpd ) nstatus (when used as an input) 3.3/2.5-v input buffer is selected. input buffer is powered by v ccpd . 1.8/1.5-v input buffer is selected. input buffer is powered by v ccio of the i/o bank. nconfig conf_done (when used as an input) data[7..0] nce dclk (when used as an input) cs nws nrs ncs clkusr dev_oe dev_clrn runlu pll_ena
altera corporation 3?7 may 2007 stratix ii device handbook, volume 1 configuration & testing you need to support configuration input voltages of 1.8 v/1.5 v, you should set the vccsel to a logic high and the v ccio of the bank that contains the configuration inputs to 1.8 v/1.5 v. f for more information on multi-volt support, including information on using tdo and nceo in multi-volt systems, refer to the stratix ii architecture chapter in volume 1 of the stratix ii device handbook . configuration schemes you can load the configuration data for a stratix ii device with one of five configuration schemes (see table 3?5 ), chosen on the basis of the target application. you can use a configuration device, intelligent controller, or the jtag port to configure a stratix i i device. a configuration device can automatically configure a stratix i i device at system power-up. you can configure multiple stratix ii devices in any of the five configuration schemes by connect ing the configuration enable ( nce ) and configuration enable output ( nceo ) pins on each device. stratix ii fpgas offer the following: configuration data decompression to reduce configuration file storage design security using configuratio n data encryption to protect your designs remote system upgrades for rem otely updating your stratix ii designs table 3?5 summarizes which configuration features can be used in each configuration scheme. table 3?5. stratix ii configur ation features (part 1 of 2) configuration scheme configuration method desi gn security decompression remote system upgrade fpp max ii device or microprocessor and flash device v (1) v (1) v enhanced configuration device v (2) v as serial configuration device vvv (3) ps max ii device or microprocessor and flash device vvv enhanced configuration device vvv download cable (4) vv
3?8 altera corporation stratix ii device handbook, volume 1 may 2007 configuration f see the configuring stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii device handbook or the stratix ii gx device handbook for more information about configur ation schemes in stratix ii and stratix ii gx devices. device security using configuration bitstream encryption stratix ii fpgas are the industry?s fi rst fpgas with the ability to decrypt a configuration bitstream using th e advanced encryption standard (aes) algorithm. when using the de sign security feature, a 128-bit security key is stored in the stratix ii fpga. to successfully configure a stratix ii fpga that has the design se curity feature enabled, it must be configured with a configuration file that was encrypted using the same 128-bit security key. the security ke y can be stored in non-volatile memory inside the stratix ii device. this non-volatile memory does not require any external devices, such as a battery back-up, for storage. ppa max ii device or microprocessor and flash device v jtag download cable (4) max ii device or microprocessor and flash device notes for ta b l e 3 ? 5 : (1) in these modes, the host system must send a dclk that is 4 the data rate. (2) the enhanced configuration device decompression featur e is available, while the stratix ii decompression feature is not available. (3) only remote update mode is supported when using the as configuration scheme. local update mode is not supported. (4) the supported download cables inc lude the altera usb blaster universal se rial bus (usb) port download cable, masterblaster serial/usb communications cable, by teblaster ii parallel port download cable, and the byteblastermv parallel port download cable. table 3?5. stratix ii configur ation features (part 2 of 2) configuration scheme configuration method desi gn security decompression remote system upgrade
altera corporation 3?9 may 2007 stratix ii device handbook, volume 1 configuration & testing 1 an encryption configuration file is the same size as a non- encryption configuration file. wh en using a serial configuration scheme such as passive serial (ps) or active serial (as), configuration time is the same whether or not the design security feature is enabled. if the fast passive parallel (fpp) scheme us used with the design security or decompression feature, a 4 dclk is required. this results in a slower configuration time when compared to the configuration time of an fpga that has neither the design security, nor decompression feature enabled. for more information about this feature, refer to an 341: using the design security feature in stratix ii devices . contact your local altera sales representative to request this document. device configuration data decompression stratix ii fpgas support decompress ion of configuration data, which saves configuration memory space an d time. this feature allows you to store compressed configuration data in configuration devices or other memory, and transmit this compressed bit stream to stratix ii fpgas. during configuration, the stratix ii fp ga decompresses the bit stream in real time and programs its sram cells. stratix ii fpgas support decompression in the fpp (when using a max ii device/microprocessor and flash memory), as and ps configuration schemes. decompression is not supported in the ppa configuration scheme nor in jtag-based configuration. remote system upgrades shortened design cycles, evolving standards, and system deployments in remote locations are difficult chal lenges faced by modern system designers. stratix ii devices can he lp effectively deal with these challenges with their inherent re-programmability and dedicated circuitry to perform remote system updates. remote system updates help deliver feature enhancements and bug fixes without costly recalls, reduce time to market, and extend product life. stratix ii fpgas feature dedicated remote system upgrade circuitry to facilitate remote system updates. soft logic (nios ? processor or user logic) implemented in the stratix ii device can download a new configuration image from a remote location, store it in configuration memory, and direct the dedicated remote system upgrade circuitry to initiate a reconfiguration cycle. the dedicated circuitry performs error detection during and after the configuration process, recovers from any error condition by reverting back to a safe configuration image, and provides
3?10 altera corporation stratix ii device handbook, volume 1 may 2007 configuration error status information. this dedicated remote system upgrade circuitry avoids system downtime and is the critical component for successful remote system upgrades. rsc is supported in the following stratix ii configuration schemes: fpp, as, ps, and ppa. rsc can also be implemented in conjunction with advanced stratix ii features such as real-time decompression of configuration data and design security using aes for secure and efficient field upgrades. f see the remote system upgrades with stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii device handbook or the stratix ii gx device handbook for more information about remote configuration in stratix ii devices. configuring stratix ii fpgas with jrunner jrunner is a software driver that configures altera fpgas, including stratix ii fpgas, through the byteblaster ii or byteblastermv cables in jtag mode. the programming input file supported is in raw binary file (.rbf) format. jrunner also requires a chain description file (.cdf) generated by the quartus ii software. jrunner is targeted for embedded jtag configuration. the source code is developed for the windows nt operating system (os), but can be customized to run on other platforms. f for more information on the jrunner software driver, see the jrunner software driver: an embedded soluti on to the jtag configuration white paper and the source files on the altera web site (www.altera.com) . programming serial configur ation devices with srunner a serial configuration device can be programmed in-system by an external microprocessor using srunner. srunner is a software driver developed for embedded serial configuration device programming that can be easily customized to fit in di fferent embedded systems. srunner is able to read a .rpd file (raw programming data) and write to the serial configuration devices. the serial configuration device programming time using srunner is comparable to the programming time when using the quartus ii software. f for more information about srunner, see the srunner: an embedded solution for epcs programming white paper and the source code on the altera web site at www.altera.com . f for more information on programming serial configuration devices, see the serial configuration devices (e pcs1 & epcs4) data sheet in the configuration handbook.
altera corporation 3?11 may 2007 stratix ii device handbook, volume 1 configuration & testing configuring stratix ii fpgas with the microblaster driver the microblaster tm software driver supports an rbf programming input file and is ideal for embedded fpp or ps configuration. the source code is developed for the windows nt operating system, although it can be customized to run on other operating systems. for more information on the microblaster software driver, see the configuring the microblaster fast passive parallel software driver white paper or the configuring the microblaster passive serial so ftware driver white paper on the altera web site ( www.altera.com ). pll reconfiguration the phase-locked loops (plls) in the stratix ii device family support reconfiguration of their multiply, divide, vco-phase selection, and bandwidth selection settings without reconfiguring the entire device. you can use either serial data from th e logic array or regular i/o pins to program the pll?s counter settings in a serial chain. this option provides considerable flexibility for freque ncy synthesis, allowing real-time variation of the pll frequency and delay. the rest of the device is functional while re configuring the pll. f see the plls in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii device handbook or the stratix ii gx device handbook for more information on stratix ii plls. temperature sensing diode (tsd) stratix ii devices include a diode-co nnected transistor for use as a temperature sensor in power manageme nt. this diode is used with an external digital thermometer device. these devices steer bias current through the stratix ii diode, measur ing forward voltage and converting this reading to temperature in the form of an 8-bit signed number (7 bits plus sign). the external device's output represents the junction temperature of the stratix ii device an d can be used for intelligent power management. the diode requires two pins ( tempdiodep and tempdioden ) on the stratix ii device to connect to the external temperature-sensing device, as shown in figure 3?1 . the temperature sensing diode is a passive element and therefore can be used before the stratix ii device is powered.
3?12 altera corporation stratix ii device handbook, volume 1 may 2007 temperature sensing diode (tsd) figure 3?1. external temperature-sensing diode table 3?6 shows the specifications for bias voltage and current of the stratix ii temperature sensing diode. table 3?6. temperature-sensing di ode electrical characteristics parameter minimum typical maximum unit ibias high 80 100 120 a ibias low 8 10 12 a vbp - vbn 0.3 0.9 v vbn 0.7 v series resistance 3 stratix ii device temperature-sensing device tempdiodep tempdioden
altera corporation 3?13 may 2007 stratix ii device handbook, volume 1 configuration & testing the temperature-sensing diode works for the entire operating range, as shown in figure 3?2 . figure 3?2. temperature vs. temperature-sensing diode voltage the temperature sensing diode is a very sensitive circuit which can be influenced by noise coupled from other traces on the board, and possibly within the device package itself, depending on device usage. the interfacing device registers temperatur e based on milivolts of difference as seen at the tsd. switching i/o near the tsd pins can affect the temperature reading. altera recomme nds you take temperature readings during periods of no ac tivity in the device (for example, standby mode where no clocks are toggling in the de vice), such as when the nearby i/os are at a dc state, and disable clock networks in the device. automated single event upset (seu) detection stratix ii devices offer on-chip circuitr y for automated checking of single event upset (seu) detection. some appl ications that require the device to operate error free at high elevations or in close proximity to earth?s north or south pole require periodic checks to ensure continued data integrity. the error detection cyclic redundancy check (crc) feature controlled by 0.90 0.85 0.95 0.75 0.65 voltage (across diode) temperature (?c) 0.55 0.45 0.60 0.50 0.40 0.70 0.80 ?55 ?30 ?5 20 45 70 95 120 10 a bias current 100 a bias current
3?14 altera corporation stratix ii device handbook, volume 1 may 2007 document revision history the device & pin options dialog box in the quartus ii software uses a 32-bit crc circuit to ensure data reliab ility and is one of the best options for mitigating seu. you can implement the error detection crc feature with ex isting circuitry in stratix ii devices, eliminating the n eed for external lo gic. for stratix ii devices, crc is computed by the device during configuration and checked against an automatically computed crc during normal operation. the crc_error pin reports a soft error when configuration sram data is corrupted, triggering device reconfiguration. custom-built circuitry dedicated circuitry is built in the stratix ii devices to perform error detection automatically. this error dete ction circuitry in stratix ii devices constantly checks for errors in the configuration sram cells while the device is in user mode. you can monitor one external pin for the error and use it to trigger a re-configuration cy cle. you can select the desired time between checks by adjusting a built-in clock divider. software interface in the quartus ii software version 4.1 and later, you can turn on the automated error detection crc feature in the device & pin options dialog box. this dialog box allows you to enable the feature and set the internal frequency of the crc between 400 khz to 50 mhz. this controls the rate that the crc circuitry verifi es the internal configuration sram bits in the fpga device. for more information on crc, refer to an 357: error detection using crc in altera fpga devices . document revision history table 3?7 shows the revision history for this chapter. table 3?7. document revision history (part 1 of 2) date and document version changes made summary of changes may 2007, v4.2 moved document revision history section to the end of the chapter. ? updated the ?temperature sensing diode (tsd)? section. ?
altera corporation 3?15 may 2007 stratix ii device handbook, volume 1 configuration & testing april 2006, v4.1 updated ?device security using configuration bitstream encryption? section. ? december 2005, v4.0 updated ?software interface? section. ? may 2005, v3.0 updated ?ieee std. 1149.1 jtag boundary-scan support? section. updated ?operating modes? section. ? january 2005, v2.1 updated jtag chain device limits. ? january 2005, v2.0 updated table 3?3. ? july 2004, v1.1 added ?automated single event upset (seu) detection? section. updated ?device security using configuration bitstream encryption? section. updated figure 3?2. ? february 2004, v1.0 added document to the stratix ii device handbook. ? table 3?7. document revision history (part 2 of 2) date and document version changes made summary of changes
3?16 altera corporation stratix ii device handbook, volume 1 may 2007 document revision history
altera corporation 4?1 may 2007 4. hot socketing & power-on reset stratix ? ii devices offer hot socketing, wh ich is also known as hot plug-in or hot swap, and power sequencing support without the use of any external devices. you can insert or remove a stratix ii board in a system during system operation without ca using undesirable effects to the running system bus or the board th at was inserted into the system. the hot socketing feature also remove s some of the difficulty when you use stratix ii devices on printed circui t boards (pcbs) that also contain a mixture of 5.0-, 3.3-, 2.5-, 1.8-, 1.5- an d 1.2-v devices. with the stratix ii hot socketing feature, you no longer need to ensure a proper power-up sequence for each device on the board. the stratix ii hot socketing feature provides: board or device insertion and removal without external components or board manipulation support for any power-up sequence non-intrusive i/o buffers to system buses during hot insertion this chapter also discusses the power- on reset (por) circuitry in stratix ii devices. the por circuitry keeps the devices in the reset state until the v cc is within operating range. stratix ii hot-socketing specifications stratix ii devices offer hot socketing capability with al l three features listed above without any external components or special design requirements. the hot socketing feature in stratix ii devices allows: the device can be driven before power-up without any damage to the device itself. i/o pins remain tri-stated during power-up. the device does not drive out before or during power-up, thereby affecting other buses in operation. signal pins do not drive the v ccio , v ccpd , or v ccint power supplies. external input signals to i/o pins of the device do not internally power the v ccio or v ccint power supplies of the device via internal paths within the device. sii51004-3.2
4?2 altera corporation stratix ii device handbook, volume 1 may 2007 stratix ii hot-socketing specifications devices can be driven before power-up you can drive signals into the i/o pins, dedicated input pins and dedicated clock pins of stratix ii de vices before or during power-up or power-down without damaging the devi ce. stratix ii devices support any power-up or power- down sequence (v ccio , v ccint , and v ccpd ) in order to simplify system level design. i/o pins remain tri-stated during power-up a device that does not support hot-socketing may interrupt system operation or cause contention by driv ing out before or during power-up. in a hot socketing situation, stratix ii device's output buffers are turned off during system power-up or power- down. stratix ii device also does not drive out until the device is co nfigured and has attained proper operating conditions. signal pins do not drive the v ccio , v ccint or v ccpd power supplies devices that do not support hot-socketing can short power supplies together when powered-up through the device signal pins. this irregular power-up can damage both the driving and driven devices and can disrupt card power-up. stratix ii devices do not have a current path from i/o pins, dedicated input pins, or dedicated clock pins to the v ccio , v ccint , or v ccpd pins before or during power-up. a stratix ii device may be inserted into (or removed from) a powered-up system board without damaging or interfering with system-board operatio n. when hot-socketing, stratix ii devices may have a minimal effect on the signal integrity of the backplane. 1 you can power up or power down the v ccio , v ccint , and v ccpd pins in any sequence. the powe r supply ramp rates can range from 100 s to 100 ms. all v cc supplies must power down within 100 ms of each other to prevent i/o pins from driving out. during hot socketing, the i /o pin capacitance is less than 15 pf and the clock pin capacitance is less than 20 pf. stratix ii devices meet the following hot socketing specification. the hot socketing dc specification is: | i iopin | < 300 a. the hot socketing ac specification is: | i iopin | < 8 ma for 10 ns or less.
altera corporation 4?3 may 2007 stratix ii device handbook, volume 1 hot socketing & power-on reset i iopin is the current at any user i/o pi n on the device. this specification takes into account the pin capacitance, but not board trace and external loading capacitance. additional capacitance for trace, connector, and loading needs must be considered se parately. for the ac specification, the peak current duration is 10 ns or less because of power-up transients. for more information, refer to the hot-socketing & power-sequencing feature & testing for altera devices white paper. a possible concern regarding hot-socketing is the potential for latch-up. latch-up can occur when electrical su bsystems are hot-socketed into an active system. during hot-socketing, the signal pins may be connected and driven by the active system before the power supply can provide current to the device's v cc and ground planes. this condition can lead to latch-up and cause a low-impedance path from v cc to ground within the device. as a result, the device extends a large amount of current, possibly causing electrical damage. nevertheless, stratix ii devices are immune to latch-up when hot-socketing. hot socketing feature implementation in stratix ii devices the hot socketing feature turns off the output buffer during the power-up event (either v ccint , v ccio , or v ccpd supplies) or power down. the hot- socket circuit will generate an internal hotsckt signal when either v ccint , v ccio , or v ccpd is below threshold voltage. the hotsckt signal will cut off the output buffer to make sure that no dc current (except for weak pull up leaking) leaks through the pin. when v cc ramps up very slowly, v cc is still relatively low even after the por signal is released and the configuration is finished. the conf_done , nceo , and nstatus pins fail to respond, as the output buffer can not flip from the state set by the hot socketing circuit at this low v cc voltage. therefore, the hot socketing circuit has been removed on these co nfiguration pins to make sure that they are able to operate during configur ation. it is expected behavior for these pins to drive out during po wer-up and power-down sequences. each i/o pin has the foll owing circuitry shown in figure 4?1 .
4?4 altera corporation stratix ii device handbook, volume 1 may 2007 hot socketing feature implementation in stratix ii devices figure 4?1. hot socketing circuit block diagram for stratix ii devices the por circuit monitors v ccint voltage level and keeps i/o pins tri- stated until the device is in user mode. the weak pull-up resistor (r) from the i/o pin to v ccio is present to keep the i /o pins from floating. the 3.3-v tolerance control circuit permits the i/o pins to be driven by 3.3 v before v ccio and/or v ccint and/or v ccpd are powered, and it prevents the i/o pins from driving out when th e device is not in user mode. the hot socket circuit prevents i/o pi ns from internally powering v ccio , v ccint , and v ccpd when driven by external signals before the device is powered. figure 4?2 shows a transistor level cross section of the stratix ii device i/o buffers. this design ensures th at the output buffers do not drive when v ccio is powered before v ccint or if the i/o pad voltage is higher than v ccio . this also applies for sudden voltage spikes during hot insertion. there is no current path from signal i/o pins to v ccint or v ccio or v ccpd during hot insertion. the v pa d leakage current charges the 3.3-v tolerant circuit capacitance. output enable output hot socket output pre-driver voltage tolerance control power on reset monitor weak pull-up resistor pad input buffer to logic array r
altera corporation 4?5 may 2007 stratix ii device handbook, volume 1 hot socketing & power-on reset figure 4?2. transistor level diagram of fpga device i/o buffers notes to figure 4?2 : (1) this is the logic array signal or the larger of either the v ccio or v pa d signal. (2) this is the larger of either the v ccio or v pad signal. power-on reset circuitry stratix ii devices have a por circuit to keep the whole device system in reset state until the power supply voltage levels have stabilized during power-up. the por circuit monitors the v ccint , v ccio , and v ccpd voltage levels and tri-states all the user i/o pins while v cc is ramping up until normal user levels are reached. the por circuitry also ensures that all eight i/o bank v ccio voltages, v ccpd voltage, as well as the logic array v ccint voltage, reach an acceptable level before configuration is triggered. after the stratix ii device enters user mode, the por circuit continues to monitor the v ccint voltage level so that a brown-out condition during user mode can be detected. if there is a v ccint voltage sag below the stratix ii operational level during user mode, the por circuit resets the device. when power is applied to a stratix ii device, a power-on-reset event occurs if v cc reaches the recommended operating range within a certain period of time (specified as a maximum v cc rise time). the maximum v cc rise time for stratix ii device is 100 ms. stratix ii devices provide a dedicated input pin ( porsel ) to select por delay times of 12 or 100 ms during power-up. when the porsel pin is connected to ground, the por time is 100 ms. when the porsel pin is connected to v cc , the por time is 12 ms. logic array signal (1) (2) v ccio v pad n+ n+ n-well n+ p+ p+ p-well p-substrate
4?6 altera corporation stratix ii device handbook, volume 1 may 2007 document revision history document revision history table 4?1 shows the revision history for this chapter. table 4?1. document revision history date and document version changes made summary of changes may 2007, v3.2 moved the document revision history section to the end of the chapter. ? april 2006, v3.1 updated ?signal pins do not drive the vccio, vccint or vccpd power supplies? section. updated hot socketing ac specification. may 2005, v3.0 updated ?signal pins do not drive the vccio, vccint or vccpd power supplies? section. removed information on esd protection. ? january 2005, v2.1 updated input rise and fall time. ? january 2005, v2.0 updated the ?hot socketing feature implementation in stratix ii devices?, ?esd protection?, and ?power-on reset circuitry? sections. ? july 2004, v1.1 updated all tables. added tables. ? february 2004, v1.0 added document to the stratix ii device handbook. ?
altera corporation 5?1 april 2011 5. dc & switching characteristics operating conditions stratix ? ii devices are offered in both co mmercial and industrial grades. industrial devices are offered in -4 speed grades and commercial devices are offered in -3 (fastest), -4, -5 speed grades. tables 5?1 through 5?32 provide information about absolute maximum ratings, recommended operating conditions, dc electrical characteristics, and other specifications for stratix ii devices. absolute maximum ratings table 5?1 contains the absolute maximum ratings for the stratix ii device family. table 5?1. stratix ii device absolute maximum ratings notes (1) , (2) , (3) symbol parameter conditions minimum maximum unit v ccint supply voltage with respect to ground ?0.5 1.8 v v ccio supply voltage with respect to ground ?0.5 4.6 v v ccpd supply voltage with respect to ground ?0.5 4.6 v v cca analog power supply for plls with respect to ground ?0.5 1.8 v v ccd digital power supply for plls wi th respect to ground ?0.5 1.8 v v i dc input voltage (4) ?0.5 4.6 v i out dc output current, per pin ?25 40 ma t stg storage temperature no bias ?65 150 c t j junction temperature bga packages under bias ?55 125 c notes to ta b l e s 5 ? 1 (1) see the operating requirements for altera devices data sheet . (2) conditions beyond those listed in table 5?1 may cause permanent damage to a device. additionally, device operation at the absolute maximum ratings for extended pe riods of time may have adve rse affects on the device. (3) supply voltage specifications apply to voltage readin gs taken at the device pins, not at the power supply. (4) during transitions, the inputs may overshoot to the voltage shown in table 5?2 based upon the input duty cycle. the dc case is equivalent to 100% dut y cycle. during transitions, the inputs may undershoot to ?2.0 v for input currents less than 100 ma and periods shorter than 20 ns. sii51005-4.5
5?2 altera corporation stratix ii device handbook, volume 1 april 2011 operating conditions recommended oper ating conditions table 5?3 contains the stratix ii device family recommended operating conditions. table 5?2. maximum duty cy cles in voltage transitions symbol parameter condition maximum duty cycles unit v i maximum duty cycles in voltage transitions v i = 4.0 v 100 % v i = 4.1 v 90 % v i = 4.2 v 50 % v i = 4.3 v 30 % v i = 4.4 v 17 % v i = 4.5 v 10 % table 5?3. stratix ii device recomm ended operating conditions (part 1 of 2) note (1) symbol parameter conditions minimum maximum unit v ccint supply voltage for internal logic 100 s risetime 100 ms (3) 1.15 1.25 v v ccio supply voltage for input and output buffers, 3.3-v operation 100 s risetime 100 ms (3) , (6) 3.135 (3.00) 3.465 (3.60) v supply voltage for input and output buffers, 2.5-v operation 100 s risetime 100 ms (3) 2.375 2.625 v supply voltage for input and output buffers, 1.8-v operation 100 s risetime 100 ms (3) 1.71 1.89 v supply voltage for output buffers, 1.5-v operation 100 s risetime 100 ms (3) 1.425 1.575 v supply voltage for input and output buffers, 1.2-v operation 100 s risetime 100 ms (3) 1.14 1.26 v v ccpd supply voltage for pre-drivers as well as configuration and jtag i/o buffers. 100 s risetime 100 ms (4) 3.135 3.465 v v cca analog power supply for plls 100 s risetime 100 ms (3) 1.15 1.25 v v ccd digital power supply for plls 100 s risetime 100 ms (3) 1.15 1.25 v v i input voltage (see ta b l e 5 ? 2 ) (2) , (5) ?0.5 4.0 v v o output voltage 0 v ccio v
altera corporation 5?3 april 2011 stratix ii device handbook, volume 1 dc & switching characteristics dc electrical characteristics table 5?4 shows the stratix ii device family dc electrical characteristics. t j operating junction temperature for commercial use 0 85 c for industrial use ?40 100 c for military use (7) ?55 125 c notes to ta b l e 5 ? 3 : (1) supply voltage specifications apply to voltage readin gs taken at the device pins, not at the power supply. (2) during transitions, the inputs may overshoot to the voltage shown in table 5?2 based upon the input duty cycle. the dc case is equivalent to 100% dut y cycle. during transitions, the inputs may undershoot to ?2.0 v for input currents less than 100 ma and periods shorter than 20 ns. (3) maximum v cc rise time is 100 ms, and v cc must rise monotonically from ground to v cc . (4) v ccpd must ramp-up from 0 v to 3.3 v within 100 s to 100 ms. if v ccpd is not ramped up within this specified time, your stratix ii device does not configure succ essfully. if your system does not allow for a v ccpd ramp-up time of 100 ms or less, you must hold nconfig low until all power supplies are reliable. (5) all pins, including dedicated inputs, clock, i/o, and jtag pins, may be driven before v ccint , v ccpd , and v ccio are powered. (6) v ccio maximum and minimum conditions for pc i and pci-x are shown in parentheses. (7) for more information, refer to the stratix ii military temperature range support technical brief. table 5?3. stratix ii device recomm ended operating conditions (part 2 of 2) note (1) symbol parameter conditions minimum maximum unit table 5?4. stratix ii device dc operating conditions (part 1 of 2) note (1) symbol parameter conditions minimum typical maximum unit i i input pin leakage current v i = v cciomax to 0 v (2) ?10 10 a i oz tri-stated i/o pin leakage current v o = v cciomax to 0 v (2) ?10 10 a i ccint0 v ccint supply current (standby) v i = ground, no load, no toggling inputs t j = 25 c ep2s15 0.25 (3) a ep2s30 0.30 (3) a ep2s60 0.50 (3) a ep2s90 0.62 (3) a ep2s130 0.82 (3) a ep2s180 1.12 (3) a i ccpd0 v ccpd supply current (standby) v i = ground, no load, no toggling inputs t j = 25 c, v ccpd = 3.3v ep2s15 2.2 (3) ma ep2s30 2.7 (3) ma ep2s60 3.6 (3) ma ep2s90 4.3 (3) ma ep2s130 5.4 (3) ma ep2s180 6.8 (3) ma
5?4 altera corporation stratix ii device handbook, volume 1 april 2011 operating conditions i/o standard specifications tables 5?5 through 5?32 show the stratix ii device family i/o standard specifications. i cci00 v ccio supply current (standby) v i = ground, no load, no toggling inputs t j = 25 c ep2s15 4.0 (3) ma ep2s30 4.0 (3) ma ep2s60 4.0 (3) ma ep2s90 4.0 (3) ma ep2s130 4.0 (3) ma ep2s180 4.0 (3) ma r conf (4) value of i/o pin pull-up resistor before and during configuration vi = 0; v ccio = 3.3 v 10 25 50 k vi = 0; v ccio = 2.5 v 15 35 70 k vi = 0; v ccio = 1.8 v 30 50 100 k vi = 0; v ccio = 1.5 v 40 75 150 k vi = 0; v ccio = 1.2 v 50 90 170 k recommended value of i/o pin external pull-down resistor before and during configuration 12k notes to ta b l e 5 ? 4 : (1) typical values are for t a = 25c, v ccint = 1.2 v, and v ccio = 1.5 v, 1.8 v, 2.5 v, and 3.3 v. (2) this value is specified for normal device operation. the value may vary during power-up. this applies for all v ccio settings (3.3, 2.5, 1.8, and 1.5 v). (3) maximum values depend on the actual t j and design utilization. see the excel-based powerplay early power estimator (available at www.altera.com ) or the quartus ii powerplay power analyzer feature for maximum values. see the section ?power consumption? on page 5?20 for more information. (4) pin pull-up resistance values are lower if an external source drives the pin higher than v ccio . table 5?4. stratix ii device dc operating conditions (part 2 of 2) note (1) symbol parameter conditions minimum typical maximum unit table 5?5. lvttl specifications (part 1 of 2) symbol parameter conditions minimum maximum unit v ccio (1) output supply voltage 3.135 3.465 v v ih high-level input voltage 1.7 4.0 v v il low-level input voltage ?0.3 0.8 v v oh high-level output voltage i oh = ?4 ma (2) 2.4 v
altera corporation 5?5 april 2011 stratix ii device handbook, volume 1 dc & switching characteristics v ol low-level output voltage i ol = 4 ma (2) 0.45 v notes to ta b l e s 5 ? 5 : (1) stratix ii devices comply to the narrow range for the supply voltage as specified in the eia/jedec standard, jesd8-b. (2) this specification is supported across all the programmabl e drive strength settings available for this i/o standard as shown in the stratix ii architecture chapter in volume 1 of the stratix ii device handbook . table 5?6. lvcmos specifications symbol parameter conditions minimum maximum unit v ccio (1) output supply voltage 3.135 3.465 v v ih high-level input voltage 1.7 4.0 v v il low-level input voltage ?0.3 0.8 v v oh high-level output voltage v ccio = 3.0, i oh = ?0.1 ma (2) v ccio ? 0.2 v v ol low-level output voltage v ccio = 3.0, i ol = 0.1 ma (2) 0.2 v notes to ta b l e 5 ? 6 : (1) stratix ii devices comply to the narrow range for the supply voltage as specified in the eia/jedec standard, jesd8-b. (2) this specification is supported acro ss all the programmable drive strength available for this i/o standard as shown in the stratix ii architecture chapter in volume 1 of the stratix ii device handbook . table 5?7. 2.5-v i/o specifications symbol parameter conditions minimum maximum unit v ccio (1) output supply voltage 2.375 2.625 v v ih high-level input voltage 1.7 4.0 v v il low-level input voltage ?0.3 0.7 v v oh high-level output voltage i oh = ?1ma (2) 2.0 v v ol low-level output voltage i ol = 1 ma (2) 0.4 v notes to ta b l e 5 ? 7 : (1) stratix ii devices v ccio voltage level support of 2.5 -5% is narrow er than defined in the normal range of the eia/jedec standard. (2) this specification is supported across all the programmab le drive settings available fo r this i/o standard as shown in the stratix ii architecture chapter in volume 1 of the stratix ii device handbook . table 5?5. lvttl specifications (part 2 of 2) symbol parameter conditions minimum maximum unit
5?6 altera corporation stratix ii device handbook, volume 1 april 2011 operating conditions figures 5?1 and 5?2 show receiver input and transmitter output waveforms, respectively, for all differential i/o standards (lvds, lvpecl, and hypertransport technology). table 5?8. 1.8-v i/o specifications symbol parameter conditions minimum maximum unit v ccio (1) output supply voltage 1.71 1.89 v v ih high-level input voltage 0.65 v ccio 2.25 v v il low-level input voltage ?0.30 0.35 v ccio v v oh high-level output voltage i oh = ?2 ma (2) v ccio ? 0.45 v v ol low-level output voltage i ol = 2 ma (2) 0.45 v notes to ta b l e 5 ? 8 : (1) the stratix ii device family?s v ccio voltage level support of 1.8 -5% is narrower than defined in the normal range of the eia/jedec standard. (2) this specification is supported across all the programmab le drive settings available fo r this i/o standard as shown in the stratix ii architecture chapter in volume 1 of the stratix ii device handbook . table 5?9. 1.5-v i/o specifications symbol parameter conditions minimum maximum unit v ccio (1) output supply voltage 1.425 1.575 v v ih high-level input voltage 0.65 v ccio v ccio + 0.30 v v il low-level input voltage ?0.30 0.35 v ccio v v oh high-level output voltage i oh = ?2 ma (2) 0.75 v ccio v v ol low-level output voltage i ol = 2 ma (2) 0.25 v ccio v notes to ta b l e 5 ? 9 : (1) the stratix ii device family?s v ccio voltage level support of 1.5 -5% is narrower than defined in the normal range of the eia/jedec standard. (2) this specification is supported across all the programmab le drive settings available fo r this i/o standard as shown in the stratix ii architecture chapter in volume 1 of the stratix ii device handbook .
altera corporation 5?7 april 2011 stratix ii device handbook, volume 1 dc & switching characteristics figure 5?1. receiver input waveform s for differential i/o standards figure 5?2. transmitter output wavefo rms for differential i/o standards single-ended waveform differential waveform positive channel (p) = v ih negative channel (n) = v il ground v id v id v id p ? n = 0 v v cm single-ended waveform differential waveform positive channel (p) = v oh negative channel (n) = v ol ground v od v od v od p ? n = 0 v v cm
5?8 altera corporation stratix ii device handbook, volume 1 april 2011 operating conditions table 5?10. 2.5-v lvds i/o specifications symbol parameter conditions minimum typical maximum unit v ccio i/o supply voltage for left and right i/o banks (1, 2, 5, and 6) 2.375 2.500 2.625 v v id input differential voltage swing (single-ended) 100 350 900 mv v icm input common mode voltage 200 1,250 1,800 mv v od output differential voltage (single-ended) r l = 100 250 450 mv v ocm output common mode voltage r l = 100 1.125 1.375 v r l receiver differential input discrete resistor (external to stratix ii devices) 90 100 110 table 5?11. 3.3-v lvds i/o specifications symbol parameter conditions minimum typical maximum unit v ccio (1) i/o supply voltage for top and bottom pll banks (9, 10, 11, and 12) 3.135 3.300 3.465 v v id input differential voltage swing (single-ended) 100 350 900 mv v icm input common mode voltage 200 1,250 1,800 mv v od output differential voltage (single-ended) r l = 100 250 710 mv v ocm output common mode voltage r l = 100 840 1,570 mv r l receiver differential input discrete resistor (external to stratix ii devices) 90 100 110 note to ta b l e 5 ? 11 : (1) the top and bottom clock input differential buffer s in i/o banks 3, 4, 7, and 8 are powered by v ccint , not v ccio . the pll clock output/feedback differential buffers are powered by vcc_pll_out . for differential clock output/feedback operation, vcc_pll_out should be connected to 3.3 v.
altera corporation 5?9 april 2011 stratix ii device handbook, volume 1 dc & switching characteristics table 5?12. lvpecl specifications symbol parameter conditions minimum typical maximum unit v ccio (1) i/o supply voltage 3.135 3.300 3.465 v v id input differential voltage swing (single-ended) 300 600 1,000 mv v icm input common mode voltage 1.0 2.5 v v od output differential voltage (single-ended) r l = 100 525 970 mv v ocm output common mode voltage r l = 100 1,650 2,250 mv r l receiver differential input resistor 90 100 110 note to table 5?12 : (1) the top and bottom clock input differential buffer s in i/o banks 3, 4, 7, and 8 are powered by v ccint , not v ccio . the pll clock output/feedback differential buffers are powered by vcc_pll_out . for differential clock output/feedback operation, vcc_pll_out should be connected to 3.3 v. table 5?13. hypertransport te chnology spec ifications symbol parameter conditions mi nimum typical maximum unit v ccio i/o supply voltage for left and right i/o banks (1, 2, 5, and 6) 2.375 2.500 2.625 v v id input differential voltage swing (single-ended) r l = 100 300 600 900 mv v icm input common mode voltage r l = 100 385 600 845 mv v od output differential voltage (single-ended) r l = 100 400 600 820 mv v od change in v od between high and low r l = 100 75 mv v ocm output common mode voltage r l = 100 440 600 780 mv v ocm change in v ocm between high and low r l = 100 50 mv r l receiver differential input resistor 90 100 110 table 5?14. 3.3-v pci specifications (part 1 of 2) symbol parameter conditions mi nimum typical maximum unit v ccio output supply voltage 3.0 3.3 3.6 v v ih high-level input voltage 0.5 v ccio v ccio + 0.5 v
5?10 altera corporation stratix ii device handbook, volume 1 april 2011 operating conditions v il low-level input voltage ?0.3 0.3 v ccio v v oh high-level output voltage i out = ?500 a0.9 v ccio v v ol low-level output voltage i out = 1,500 a0.1 v ccio v table 5?15. pci-x mode 1 specifications symbol parameter conditions mi nimum typical maximum unit v ccio output supply voltage 3.0 3.6 v v ih high-level input voltage 0.5 v ccio v ccio + 0.5 v v il low-level input voltage ?0.30 0.35 v ccio v v ipu input pull-up voltage 0.7 v ccio v v oh high-level output voltage i out = ?500 a0.9 v ccio v v ol low-level output voltage i out = 1,500 a0.1 v ccio v table 5?16. sstl-18 clas s i specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 1.71 1.80 1.89 v v ref reference voltage 0.855 0.900 0.945 v v tt termination voltage v ref ? 0.04 v ref v ref + 0.04 v v ih (dc) high-level dc input voltage v ref + 0.125 v v il (dc) low-level dc input voltage v ref ? 0.125 v v ih (ac) high-level ac input voltage v ref + 0.25 v v il (ac) low-level ac input voltage v ref ? 0.25 v v oh high-level output voltage i oh = ?6.7 ma (1) v tt + 0.475 v v ol low-level output voltage i ol = 6.7 ma (1) v tt ? 0.475 v note to table 5?16 : (1) this specification is supported across all the programmable drive settings available for this i/o standard as shown in the stratix ii architecture chapter in volume 1 of the stratix ii device handbook . table 5?14. 3.3-v pci specifications (part 2 of 2) symbol parameter conditions mi nimum typical maximum unit
altera corporation 5?11 april 2011 stratix ii device handbook, volume 1 dc & switching characteristics table 5?17. sstl-18 clas s ii specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 1.71 1.80 1.89 v v ref reference voltage 0.855 0.900 0.945 v v tt termination voltage v ref ? 0.04 v ref v ref + 0.04 v v ih (dc) high-level dc input voltage v ref + 0.125 v v il (dc) low-level dc input voltage v ref ? 0.125 v v ih (ac) high-level ac input voltage v ref + 0.25 v v il (ac) low-level ac input voltage v ref ? 0.25 v v oh high-level output voltage i oh = ?13.4 ma (1) v ccio ? 0.28 v v ol low-level output voltage i ol = 13.4 ma (1) 0.28 v note to table 5?17 : (1) this specification is supported across all the programmable drive settings available for this i/o standard as shown in the stratix ii architecture chapter in volume 1 of the stratix ii device handbook . table 5?18. sstl-18 class i & ii differential specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 1.71 1.80 1.89 v v swing (dc) dc differential input voltage 0.25 v v x (ac) ac differential input cross point voltage (v ccio /2) ? 0.175 (v ccio /2) + 0.175 v v swing (ac) ac differential input voltage 0.5 v v iso input clock signal offset voltage 0.5 v ccio v v iso input clock signal offset voltage variation 200 mv v ox (ac) ac differential cross point voltage (v ccio /2) ? 0.125 (v ccio /2) + 0.125 v
5?12 altera corporation stratix ii device handbook, volume 1 april 2011 operating conditions table 5?19. sstl-2 class i specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 2.375 2.500 2.625 v v tt termination voltage v ref ? 0.04 v ref v ref + 0.04 v v ref reference voltage 1.188 1.250 1.313 v v ih (dc) high-level dc input voltage v ref + 0.18 3.00 v v il (dc) low-level dc input voltage ?0.30 v ref ? 0.18 v v ih (ac) high-level ac input voltage v ref + 0.35 v v il (ac) low-level ac input voltage v ref - 0.35 v v oh high-level output voltage i oh = ?8.1 ma (1) v tt + 0.57 v v ol low-level output voltage i ol = 8.1 ma (1) v tt ? 0.57 v note to table 5?19 : (1) this specification is supported across all the programmable drive settings available for this i/o standard as shown in the stratix ii architecture chapter in volume 1 of the stratix ii device handbook . table 5?20. sstl-2 class ii specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 2.375 2.500 2.625 v v tt termination voltage v ref ? 0.04 v ref v ref + 0.04 v v ref reference voltage 1.188 1.250 1.313 v v ih (dc) high-level dc input voltage v ref + 0.18 v ccio + 0.30 v v il (dc) low-level dc input voltage ?0.30 v ref ? 0.18 v v ih (ac) high-level ac input voltage v ref + 0.35 v v il (ac) low-level ac input voltage v ref - 0.35 v v oh high-level output voltage i oh = ?16.4 ma (1) v tt + 0.76 v v ol low-level output voltage i ol = 16.4 ma (1) v tt ? 0.76 v note to table 5?20 : (1) this specification is supported across all the programmable drive settings available for this i/o standard as shown in the stratix ii architecture chapter in volume 1 of the stratix ii device handbook .
altera corporation 5?13 april 2011 stratix ii device handbook, volume 1 dc & switching characteristics table 5?21. sstl-2 class i & ii differential specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 2.375 2.500 2.625 v v swing (dc) dc differential input voltage 0.36 v v x (ac) ac differential input cross point voltage (v ccio /2) ? 0.2 (v ccio /2) + 0.2 v v swing (ac) ac differential input voltage 0.7 v v iso input clock signal offset voltage 0.5 v ccio v v iso input clock signal offset voltage variation 200 mv v ox (ac) ac differential output cross point voltage (v ccio /2) ? 0.2 (v ccio /2) + 0.2 v table 5?22. 1.2-v hstl specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 1.14 1.20 1.26 v v ref reference voltage 0.48 v ccio 0.50 v ccio 0.52 v ccio v v ih (dc) high-level dc input voltage v ref + 0.08 v ccio + 0.15 v v il (dc) low-level dc input voltage ?0.15 v ref ? 0.08 v v ih (ac) high-level ac input voltage v ref + 0.15 v ccio + 0.24 v v il (ac) low-level ac input voltage ?0.24 v ref ? 0.15 v v oh high-level output voltage i oh = 8 ma v ref + 0.15 v ccio + 0.15 v v ol low-level output voltage i oh = ?8 ma ?0.15 v ref ? 0.15 v
5?14 altera corporation stratix ii device handbook, volume 1 april 2011 operating conditions table 5?23. 1.5-v hstl class i specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 1.425 1.500 1.575 v v ref input reference voltage 0.713 0.750 0.788 v v tt termination voltage 0.713 0.750 0.788 v v ih (dc) dc high-level input voltage v ref + 0.1 v v il (dc) dc low-level input voltage ?0.3 v ref ? 0.1 v v ih (ac) ac high-level input voltage v ref + 0.2 v v il (ac) ac low-level input voltage v ref ? 0.2 v v oh high-level output voltage i oh = 8 ma (1) v ccio ? 0.4 v v ol low-level output voltage i oh = ?8 ma (1) 0.4 v note to table 5?23 : (1) this specification is supported across all the programmable drive settings available for this i/o standard as shown in the stratix ii architecture chapter in volume 1 of the stratix ii device handbook . table 5?24. 1.5-v hstl class ii specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 1.425 1.500 1.575 v v ref input reference voltage 0.713 0.750 0.788 v v tt termination voltage 0.713 0.750 0.788 v v ih (dc) dc high-level input voltage v ref + 0.1 v v il (dc) dc low-level input voltage ?0.3 v ref ? 0.1 v v ih (ac) ac high-level input voltage v ref + 0.2 v v il (ac) ac low-level input voltage v ref ? 0.2 v v oh high-level output voltage i oh = 16 ma (1) v ccio ? 0.4 v v ol low-level output voltage i oh = ?16 ma (1) 0.4 v note to table 5?24 : (1) this specification is supported across all the programmable drive settings available for this i/o standard as shown in the stratix ii architecture chapter in volume 1 of the stratix ii device handbook .
altera corporation 5?15 april 2011 stratix ii device handbook, volume 1 dc & switching characteristics table 5?25. 1.5-v hstl class i & ii differential specifications symbol parameter conditions minimum typical maximum unit v ccio i/o supply voltage 1.425 1.500 1.575 v v dif (dc) dc input differential voltage 0.2 v v cm (dc) dc common mode input voltage 0.68 0.90 v v dif (ac) ac differential input voltage 0.4 v v ox (ac) ac differential cross point voltage 0.68 0.90 v table 5?26. 1.8-v hstl class i specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 1.71 1.80 1.89 v v ref input reference voltage 0.85 0.90 0.95 v v tt termination voltage 0.85 0.90 0.95 v v ih (dc) dc high-level input voltage v ref + 0.1 v v il (dc) dc low-level input voltage ?0.3 v ref ? 0.1 v v ih (ac) ac high-level input voltage v ref + 0.2 v v il (ac) ac low-level input voltage v ref ? 0.2 v v oh high-level output voltage i oh = 8 ma (1) v ccio ? 0.4 v v ol low-level output voltage i oh = ?8 ma (1) 0.4 v note to table 5?26 : (1) this specification is supported across all the programmable drive settings available for this i/o standard as shown in the stratix ii architecture chapter in volume 1 of the stratix ii device handbook .
5?16 altera corporation stratix ii device handbook, volume 1 april 2011 operating conditions table 5?27. 1.8-v hstl class ii specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 1.71 1.80 1.89 v v ref input reference voltage 0.85 0.90 0.95 v v tt termination voltage 0.85 0.90 0.95 v v ih (dc) dc high-level input voltage v ref + 0.1 v v il (dc) dc low-level input voltage ?0.3 v ref ? 0.1 v v ih (ac) ac high-level input voltage v ref + 0.2 v v il (ac) ac low-level input voltage v ref ? 0.2 v v oh high-level output voltage i oh = 16 ma (1) v ccio ? 0.4 v v ol low-level output voltage i oh = ?16 ma (1) 0.4 v note to table 5?27 : (1) this specification is supported across all the programmable drive settings available for this i/o standard as shown in the stratix ii architecture chapter in volume 1 of the stratix ii device handbook . table 5?28. 1.8-v hstl class i & ii differential specifications symbol parameter conditions minimum typical maximum unit v ccio i/o supply voltage 1.71 1.80 1.89 v v dif (dc) dc input differential voltage 0.2 v ccio + 0.6 v v v cm (dc) dc common mode input voltage 0.78 1.12 v v dif (ac) ac differential input voltage 0.4 v ccio + 0.6 v v v ox (ac) ac differential cross point voltage 0.68 0.90 v
altera corporation 5?17 april 2011 stratix ii device handbook, volume 1 dc & switching characteristics bus hold specifications table 5?29 shows the stratix ii device family bus hold specifications. on-chip termination specifications tables 5?30 and 5?31 define the specification for internal termination resistance tolerance when using series or differential on-chip termination. table 5?29. bus hold parameters parameter conditions v ccio level unit 1.2 v 1.5 v 1.8 v 2.5 v 3.3 v min max min max min max min max min max low sustaining current v in > v il (maximum) 22.5 25.0 30.0 50.0 70.0 a high sustaining current v in < v ih (minimum) ?22.5 ?25.0 ?30.0 ?50.0 ?70.0 a low overdrive current 0 v < v in < v ccio 120 160 200 300 500 a high overdrive current 0 v < v in < v ccio ?120 ?160 ?200 ?300 ?500 a bus-hold trip point 0.45 0.95 0.50 1.00 0.68 1.07 0.70 1.70 0.80 2.00 v table 5?30. series on-chip termi nation specification for top & bottom i/o banks (part 1 of 2) notes (1) , 2 symbol description conditions resistance tolerance commercial max industrial max unit 25- r s 3.3/2.5 internal series termination with calibration (25- setting) v ccio = 3.3/2.5 v 5 10 % internal series termination without calibration (25- setting) v ccio = 3.3/2.5 v 30 30 %
5?18 altera corporation stratix ii device handbook, volume 1 april 2011 operating conditions 50- r s 3.3/2.5 internal series termination with calibration (50- setting) v ccio = 3.3/2.5 v 5 10 % internal series termination without calibration (50- setting) v ccio = 3.3/2.5 v 30 30 % 50- r t 2.5 internal parallel termination with calibration (50- setting) v ccio = 1.8 v 30 30 % 25- r s 1.8 internal series termination with calibration (25- setting) v ccio = 1.8 v 5 10 % internal series termination without calibration (25- setting) v ccio = 1.8 v 30 30 % 50- r s 1.8 internal series termination with calibration (50- setting) v ccio = 1.8 v 5 10 % internal series termination without calibration (50- setting) v ccio = 1.8 v 30 30 % 50- r t 1.8 internal parallel termination with calibration (50- setting) v ccio = 1.8 v 10 15 % 50 ? r s 1.5 internal series termination with calibration (50- setting) v ccio = 1.5 v 8 10 % internal series termination without calibration (50- setting) v ccio = 1.5 v 36 36 % 50- r t 1.5 internal parallel termination with calibration (50- setting) v ccio = 1.5 v 10 15 % 50 ? r s 1.2 internal series termination with calibration (50- setting) v ccio = 1.2 v 8 10 % internal series termination without calibration (50- setting) v ccio = 1.2 v 50 50 % 50- r t 1.2 internal parallel termination with calibration (50- setting) v ccio = 1.2 v 10 15 % notes for ta b l e 5 ? 3 0 : (1) the resistance tolerances for calibrated soct and poct are for the moment of calibrat ion. if the temperature or voltage changes over time, the tolerance may also change. (2) on-chip parallel termination with calibr ation is only supported for input pins. table 5?30. series on-chip termi nation specification for top & bottom i/o banks (part 2 of 2) notes (1) , 2 symbol description conditions resistance tolerance commercial max industrial max unit
altera corporation 5?19 april 2011 stratix ii device handbook, volume 1 dc & switching characteristics pin capacitance table 5?32 shows the stratix ii device family pin capacitance. table 5?31. series & differential on-chip terminat ion specification for left & right i/o banks symbol description conditions resistance tolerance commercial max industrial max unit 25- r s 3.3/2.5 internal series termination without calibration (25- setting ) v ccio = 3.3/2.5 v 30 30 % 50- r s 3.3/2.5/1.8 internal series termination without calibration (50- setting ) v ccio = 3.3/2.5/1.8 v 30 30 % 50- r s 1.5 internal series termination without calibration (50- setting ) v ccio = 1.5 v 36 36 % r d internal differential termination for lvds or hypertransport technology (100- setting ) v ccio = 2.5 v 20 25 % table 5?32. stratix ii device capacitance note (1) symbol parameter typical unit c iotb input capacitance on i/o pins in i/o banks 3, 4, 7, and 8. 5.0 pf c iolr input capacitance on i/o pins in i/o banks 1, 2, 5, and 6, including high- speed differential receiv er and transmitter pins. 6.1 pf c clktb input capacitance on top/bottom clock input pins: clk[4..7] and clk[12..15] . 6.0 pf c clklr input capacitance on left/right clock inputs: clk0 , clk2 , clk8 , clk10 . 6.1 pf c clklr+ input capacitance on left/right clock inputs: clk1 , clk3 , clk9 , and clk11 . 3.3 pf c outfb input capacitance on dual-purpose clock output/feedback pins in pll banks 9, 10, 11, and 12. 6.7 pf note to table 5?32 : (1) capacitance is sample-tested only. capacitance is me asured using time-domain reflections (tdr). measurement accuracy is within 0.5pf
5?20 altera corporation stratix ii device handbook, volume 1 april 2011 power consumption power consumption altera ? offers two ways to calculate power for a design: the excel-based powerplay early power estimator po wer calculator and the quartus ? ii powerplay power analyzer feature. the interactive excel-based powerplay early power estimator is typically used prior to designing the fpga in order to get an estimate of device power. the quartus ii powerplay power analyzer provides better quality estimates based on the specif ics of the design after place-and- route is complete. the power analyzer can apply a combination of user- entered, simulation-derived and es timated signal ac tivities which, combined with detailed circuit mode ls, can yield very accurate power estimates. in both cases, these calculations should only be used as an estimation of power, not as a specification. f for more information about powerplay tools, refer to the powerplay early power estimator user guide and the powerplay early power estimator and powerplay power analyzer chapters in volume 3 of the quartus ii handbook . the powerplay early power estimator is available on the altera web site at www.altera.com . see table 5?4 on page 5?3 for typical i cc standby specifications. timing model the directdrive tm technology and multitrack tm interconnect ensure predictable performance, accurate simulation, and ac curate timing analysis across al l stratix ii device densities and speed grades. this section describes and specifies the performance, internal timing, external timing, and pll, high-speed i/o, ex ternal memory interface, and jtag timing specifications. all specifications are representative of worst-case supply voltage and junction temperature conditions. 1 the timing numbers listed in th e tables of this section are extracted from the quartus ii software version 5.0 sp1. preliminary & final timing timing models can have either preliminary or final status. the quartus ii software issues an informational me ssage during the design compilation if the timing models are preliminary. table 5?33 shows the status of the stratix ii device timing models.
altera corporation 5?21 april 2011 stratix ii device handbook, volume 1 dc & switching characteristics preliminary status means the timing model is subject to change. initially, timing numbers are created using simulation results, process data, and other known parameters. these tests are used to make the preliminary numbers as close to the actual timing parameters as possible. final timing numbers are based on ac tual device operation and testing. these numbers reflect the actual performance of the device under worst-case voltage and juncti on temperature conditions. i/o timing measurement methodology altera characterizes timing delays at the worst-case process, minimum voltage, and maximum temperature for input register setup time (t su ) and hold time (t h ). the quartus ii software uses the following equations to calculate t su and t h timing for stratix ii devices input signals. t su = + data delay from input pin to input register + micro setup time of the input register ? clock delay from input pin to input register t h = ? data delay from input pin to input register + micro hold time of the input register + clock delay from input pin to input register figure 5?3 shows the setup and hold timing diagram for input registers. table 5?33. stratix ii device timing model status device preliminary final ep2s15 v ep2s30 v ep2s60 v ep2s90 v ep2s130 v ep2s180 v
5?22 altera corporation stratix ii device handbook, volume 1 april 2011 timing model figure 5?3. input register setup & hold timing diagram for output timing, different i/o standards require different baseline loading techniques for reporting ti ming delays. altera characterizes timing delays with the required termination for each i/o standard and with 0 pf (except for pci and pci- x which use 10 pf) loading and the timing is specified up to the output pin of the fpga device. the quartus ii software calculates the i/o timing for each i /o standard with a default baseline loading as specified by the i/o standards. the following measurements are made during device characterization. altera measures clock-to-output delays (t co ) at worst-case process, minimum voltage, and maximum temperature (pvt) for default loading conditions shown in table 5?34 . use the following equations to calculate clock pin to output pin timing for stratix ii devices. t co from clock pin to i/o pin = dela y from clock pad to i/o output register + ioe output register clock-to-output delay + delay from output register to output pin + i/o output delay t xz /t zx from clock pin to i/o pin = delay from clock pad to i/o output register + ioe output regi ster clock-to-output delay + delay from output register to output pin + i/o output delay + output enable pin delay simulation using ibis models is required to determine the delays on the pcb traces in addition to the output pin delay timing reported by the quartus ii software and the timing model in the device handbook. 1. simulate the output driver of choi ce into the generalized test setup, using values from table 5?34 . 2. record the time to v meas . 3. simulate the output driver of ch oice into the actual pcb trace and load, using the appropriate ibis model or capacitance value to represent the load. input data delay input clock delay micro t su micro t h
altera corporation 5?23 april 2011 stratix ii device handbook, volume 1 dc & switching characteristics 4. record the time to v meas . 5. compare the results of steps 2 and 4. the increase or decrease in delay should be added to or subt racted from the i/o standard output adder delays to yield the actual worst-case propagation delay (clock-to-output) of the pcb trace. the quartus ii software reports the ti ming with the conditions shown in table 5?34 using the above equation. figure 5?4 shows the model of the circuit that is represented by the outp ut timing of the quartus ii software. figure 5?4. output delay timing reporting setup modeled by quartus ii notes to figure 5?4 : (1) output pin timing is reported at the ou tput pin of the fpga device. additional delays for loading and board trace delay need to be accounted for with ibis model simulations. (2) v ccpd is 3.085 v unless otherwise specified. (3) v ccint is 1.12 v unless otherwise specified. figures 5?5 and 5?6 show the measurement setup for output disable and output enable timing. output buffer v tt v ccio r d output n output p r t c l r s v meas output gnd gnd
5?24 altera corporation stratix ii device handbook, volume 1 april 2011 timing model table 5?34. output timing measurem ent methodology for output pins notes (1) , (2) , (3) i/o standard loading and termination measurement point r s ( )r d ( )r t ( )v ccio (v) v tt (v) c l (pf) v meas (v) lv t t l (4) 3.135 0 1.5675 lv c m o s (4) 3.135 0 1.5675 2.5 v (4) 2.375 0 1.1875 1.8 v (4) 1.710 0 0.855 1.5 v (4) 1.425 0 0.7125 pci (5) 2.970 10 1.485 pci-x (5) 2.970 10 1.485 sstl-2 class i 25 50 2.325 1.123 0 1.1625 sstl-2 class ii 25 25 2.325 1.123 0 1.1625 sstl-18 class i 25 50 1.660 0.790 0 0.83 sstl-18 class ii 25 25 1.660 0.790 0 0.83 1.8-v hstl class i 50 50 1.660 0.790 0 0.83 1.8-v hstl class ii 25 25 1.660 0.790 0 0.83 1.5-v hstl class i 50 50 1.375 0.648 0 0.6875 1.5-v hstl class ii 25 1.375 0.648 0 0.6875 1.2-v hstl with oct 50 1.140 0 0.570 differential sstl-2 class i 50 50 2.325 1.123 0 1.1625 differential sstl-2 class ii 25 25 2.325 1.123 0 1.1625 differential sstl-18 class i 50 50 1.660 0.790 0 0.83 differential sstl-18 class ii 25 25 1.660 0.790 0 0.83 1.5-v differential hstl class i 50 50 1.375 0.648 0 0.6875 1.5-v differential hstl class ii 25 1.375 0.648 0 0.6875 1.8-v differential hstl class i 50 50 1.660 0.790 0 0.83 1.8-v differential hstl class ii 25 25 1.660 0.790 0 0.83 lvds 100 2.325 0 1.1625 hypertransport 100 2.325 0 1.1625 lvpecl 100 3.135 0 1.5675 notes to table 5?34 : (1) input measurement point at internal node is 0.5 v ccint . (2) output measuring point for v meas at buffer output is 0.5 v ccio . (3) input stimulus edge rate is 0 to v cc in 0.2 ns (internal signal) from the driver preceding the i/o buffer. (4) less than 50-mv ripple on v ccio and v ccpd , v ccint = 1.15 v with less than 30-mv ripple (5) v ccpd = 2.97 v, less than 50-mv ripple on v ccio and v ccpd , v ccint = 1.15 v
altera corporation 5?25 april 2011 stratix ii device handbook, volume 1 dc & switching characteristics figure 5?5. measurement setup for t xz note (1) note to figure 5?5 : (1) v ccint is 1.12 v for this measurement. t xz , driving high to tristate t xz , driving low to tristate 100 din oe dout v ccio oe enable disable dout din t lz 100 mv ? v ccint ?0? 100 din oe dout oe enable disable dout din t hz 100 mv ? v ccint ?1? gnd
5?26 altera corporation stratix ii device handbook, volume 1 april 2011 timing model figure 5?6. measurement setup for t zx table 5?35 specifies the input ti ming measurement setup. t zx , tristate to driving high t zx , tristate to driving low 1 m din oe dout 1 m din oe dout oe disable enable dout din t zh ? v ccint ?1? ? v cci o oe disable enable dout din ? v ccint ?0? t zl ? v cci o table 5?35. timing measurement metho dology for input pins (part 1 of 2) notes (1) ? (4) i/o standard measurement conditions measurement point v ccio (v) v ref (v) edge rate (ns) v meas (v) lv t t l (5) 3.135 3.135 1.5675 lv c m o s (5) 3.135 3.135 1.5675 2.5 v (5) 2.375 2.375 1.1875 1.8 v (5) 1.710 1.710 0.855 1.5 v (5) 1.425 1.425 0.7125 pci (6) 2.970 2.970 1.485 pci-x (6) 2.970 2.970 1.485 sstl-2 class i 2.325 1.163 2.325 1.1625 sstl-2 class ii 2.325 1.163 2.325 1.1625 sstl-18 class i 1.660 0.830 1.660 0.83 sstl-18 class ii 1.660 0.830 1.660 0.83 1.8-v hstl class i 1.660 0.830 1.660 0.83
altera corporation 5?27 april 2011 stratix ii device handbook, volume 1 dc & switching characteristics performance table 5?36 shows stratix ii performance for some common designs. all performance values were obtained with the quartus ii software compilation of library of paramete rized modules (lpm), or megacore ? functions for the finite impulse respon se (fir) and fast fourier transform (fft) designs. 1.8-v hstl class ii 1.660 0.830 1.660 0.83 1.5-v hstl class i 1.375 0.688 1.375 0.6875 1.5-v hstl class ii 1.375 0.688 1.375 0.6875 1.2-v hstl with oct 1.140 0.570 1.140 0.570 differential sstl-2 class i 2.325 1.163 2.325 1.1625 differential sstl-2 class ii 2.325 1.163 2.325 1.1625 differential sstl-18 class i 1.660 0.830 1.660 0.83 differential sstl-18 class ii 1.660 0.830 1.660 0.83 1.5-v differential hstl class i 1.375 0.688 1.375 0.6875 1.5-v differential hstl class ii 1.375 0.688 1.375 0.6875 1.8-v differential hstl class i 1.660 0.830 1.660 0.83 1.8-v differential hstl class ii 1.660 0.830 1.660 0.83 lvds 2.325 0.100 1.1625 hypertransport 2.325 0.400 1.1625 lvpecl 3.135 0.100 1.5675 notes to table 5?35 : (1) input buffer sees no load at buffer input. (2) input measuring point at buffer input is 0.5 v ccio . (3) output measuring point is 0.5 v cc at internal node. (4) input edge rate is 1 v/ns. (5) less than 50-mv ripple on v ccio and v ccpd , v ccint = 1.15 v with less than 30-mv ripple (6) v ccpd = 2.97 v, less than 50-mv ripple on v ccio and v ccpd , v ccint = 1.15 v table 5?35. timing measurement metho dology for input pins (part 2 of 2) notes (1) ? (4) i/o standard measurement conditions measurement point v ccio (v) v ref (v) edge rate (ns) v meas (v)
5?28 altera corporation stratix ii device handbook, volume 1 april 2011 timing model 1 the performance numbers in table 5?36 are extracted from the quartus ii software version 5.1 sp1. table 5?36. stratix ii performance notes (part 1 of 6) note (1) applications resources used performance aluts trimatrix memory blocks dsp blocks -3 speed grade (2) -3 speed grade (3) -4 speed grade -5 speed grade unit le 16-to-1 multiplexer (4) 21 0 0 654.87 625.0 523.83 460.4 mhz 32-to-1 multiplexer (4) 38 0 0 519.21 473.26 464.25 384.17 mhz 16-bit counter 16 0 0 566.57 538.79 489.23 421.05 mhz 64-bit counter 64 0 0 244.31 232.07 209.11 181.38 mhz tr i m a t r i x memory m512 block simple dual-port ram 32 18 bit 0 1 0 500.00 476.19 434.02 373.13 mhz fifo 32 x 18 bit 22 1 0 500.00 476.19 434.78 373.13 mhz tr i m a t r i x memory m4k block simple dual-port ram 128 x 36 bit ( 8 ) 0 1 0 540.54 515.46 469.48 401.60 mhz true dual-port ram 128 18 bit ( 8 ) 0 1 0 540.54 515.46 469.48 401.60 mhz fifo 128 36 bit 22 1 0 530.22 499.00 469.48 401.60 mhz simple dual-port ram 128 36 bit (9) 0 1 0 475.28 453.30 413.22 354.10 mhz true dual-port ram 128 18 bit (9) 0 1 0 475.28 453.30 413.22 354.10 mhz
altera corporation 5?29 april 2011 stratix ii device handbook, volume 1 dc & switching characteristics tr i m a t r i x memory m-ram block single port ram 4k 144 bit 0 1 0 349.65 333.33 303.95 261.09 mhz simple dual-port ram 4k 144 bit 0 1 0 420.16 400.00 364.96 313.47 mhz true dual-port ram 4k 144 bit 0 1 0 349.65 333.33 303.95 261.09 mhz single port ram 8k 72 bit 0 1 0 354.60 337.83 307.69 263.85 mhz simple dual-port ram 8k 72 bit 0 1 0 420.16 400.00 364.96 313.47 mhz true dual-port ram 8k 72 bit 0 1 0 349.65 333.33 303.95 261.09 mhz single port ram 16k 36 bit 0 1 0 364.96 347.22 317.46 271.73 mhz simple dual-port ram 16k 36 bit 0 1 0 420.16 400.00 364.96 313.47 mhz true dual-port ram 16k 36 bit 0 1 0 359.71 342.46 313.47 268.09 mhz single port ram 32k 18 bit 0 1 0 364.96 347.22 317.46 271.73 mhz simple dual-port ram 32k 18 bit 0 1 0 420.16 400.0 364.96 313.47 mhz true dual-port ram 32k 18 bit 0 1 0 359.71 342.46 313.47 268.09 mhz single port ram 64k 9 bit 0 1 0 364.96 347.22 317.46 271.73 mhz simple dual-port ram 64k 9 bit 0 1 0 420.16 400.0 364.96 313.47 mhz true dual-port ram 64k 9 bit 0 1 0 359.71 342.46 313.47 268.09 mhz table 5?36. stratix ii performance notes (part 2 of 6) note (1) applications resources used performance aluts trimatrix memory blocks dsp blocks -3 speed grade (2) -3 speed grade (3) -4 speed grade -5 speed grade unit
5?30 altera corporation stratix ii device handbook, volume 1 april 2011 timing model dsp block 9 9-bit multiplier (5) 0 0 1 430.29 409.16 373.13 320.10 mhz 18 18-bit multiplier (5) 0 0 1 410.17 390.01 356.12 305.06 mhz 18 18-bit multiplier (7) 0 0 1 450.04 428.08 391.23 335.12 mhz 36 36-bit multiplier (5) 0 0 1 250.00 238.15 217.48 186.60 mhz 36 36-bit multiplier (6) 0 0 1 410.17 390.01 356.12 305.06 mhz 18-bit, four-tap fir filter 0 0 1 410.17 390.01 356.12 305.06 mhz larger designs 8-bit,16-tap parallel fir filter 58 0 4 259.06 240.61 217.15 185.01 mhz 8-bit, 1024-point, streaming, three multipliers and five adders fft function 2976 22 9 398.72 364.03 355.23 306.37 mhz 8-bit, 1024-point, streaming, four multipliers and two adders fft function 2781 22 12 398.56 409.16 347.22 311.13 mhz 8-bit, 1024-point, single output, one parallel fft engine, burst, three multipliers and five adders fft function 984 5 3 425.17 365.76 346.98 292.39 mhz 8-bit, 1024-point, single output, one parallel fft engine, burst, four multipliers and two adders fft function 919 5 4 427.53 378.78 357.14 307.59 mhz table 5?36. stratix ii performance notes (part 3 of 6) note (1) applications resources used performance aluts trimatrix memory blocks dsp blocks -3 speed grade (2) -3 speed grade (3) -4 speed grade -5 speed grade unit
altera corporation 5?31 april 2011 stratix ii device handbook, volume 1 dc & switching characteristics larger designs 8-bit, 1024-point, single output, two parallel fft engines, burst, three multiplier and five adders fft function 1725 10 6 430.29 401.92 373.13 319.08 mhz 8-bit, 1024-point, single output, two parallel fft engines, burst, four multipliers and two adders fft function 1594 10 8 422.65 407.33 373.13 329.10 mhz 8-bit, 1024-point, quadrant output, one parallel fft engine, burst, three multipliers and five adders fft function 2361 10 9 315.45 342.81 325.73 284.25 mhz 8-bit, 1024-point, quadrant output, one parallel fft engine, burst, four multipliers and two adders fft function 2165 10 12 373.13 369.54 317.96 256.14 mhz 8-bit, 1024-point, quadrant output, two parallel fft engines, burst, three multipliers and five adders fft function 3996 14 18 378.50 367.10 332.33 288.68 mhz 8-bit, 1024-point, quadrant output, two parallel fft engines, burst, four multipliers and two adders fft function 3604 14 24 391.38 361.14 340.25 280.89 mhz table 5?36. stratix ii performance notes (part 4 of 6) note (1) applications resources used performance aluts trimatrix memory blocks dsp blocks -3 speed grade (2) -3 speed grade (3) -4 speed grade -5 speed grade unit
5?32 altera corporation stratix ii device handbook, volume 1 april 2011 timing model larger designs 8-bit, 1024-point, quadrant output, four parallel fft engines, burst, three multipliers and five adders fft function 6850 28 36 334.11 345.66 308.54 276.31 mhz 8-bit, 1024-point, quadrant output, four parallel fft engines, burst, four multipliers two adders fft function 6067 28 48 367.91 349.04 327.33 268.24 mhz 8-bit, 1024-point, quadrant output, one parallel fft engine, buffered burst, three multipliers and adders fft function 2730 18 9 387.44 388.34 364.56 306.84 mhz 8-bit, 1024-point, quadrant output, one parallel fft engine, buffered burst, four multipliers and two adders fft function 2534 18 12 419.28 369.66 364.96 307.88 mhz 8-bit, 1024-point, quadrant output, two parallel fft engines, buffered burst, three multipliers five adders fft function 4358 30 18 396.51 378.07 340.13 291.29 mhz 8-bit, 1024-point, quadrant output, two parallel fft engines, buffered burst four multipliers and two adders fft function 3966 30 24 389.71 398.08 356.53 280.74 mhz table 5?36. stratix ii performance notes (part 5 of 6) note (1) applications resources used performance aluts trimatrix memory blocks dsp blocks -3 speed grade (2) -3 speed grade (3) -4 speed grade -5 speed grade unit
altera corporation 5?33 april 2011 stratix ii device handbook, volume 1 dc & switching characteristics larger designs 8-bit, 1024-point, quadrant output, four parallel fft engines, buffered burst, three multipliers five adders fft function 7385 60 36 359.58 352.98 312.01 278.00 mhz 8-bit, 1024-point, quadrant output, four parallel fft engines, buffered burst, four multipliers and two adders fft function 6601 60 48 371.88 355.74 327.86 277.62 mhz notes for ta b l e 5 ? 3 6 : (1) these design performance numbers were obtain ed using the quartus ii software version 5.0 sp1. (2) these numbers apply to -3 speed grade ep2s15, ep2s30, ep2s60, and ep2s90 devices. (3) these numbers apply to -3 speed grade ep2s130 and ep2s180 devices. (4) this application uses regi stered inputs and outputs. (5) this application uses registered multiplier input and output stages within the dsp block. (6) this application uses registered multiplier input, pipeline, and output stages within the dsp block. (7) this application uses registered multi plier input with output of the multip lier stage feeding the accumulator or subtractor within the dsp block. (8) this application uses the same clock source that is globally routed and connected to ports a and b. (9) this application uses locally routed clocks or differently sourced clocks for ports a and b. table 5?36. stratix ii performance notes (part 6 of 6) note (1) applications resources used performance aluts trimatrix memory blocks dsp blocks -3 speed grade (2) -3 speed grade (3) -4 speed grade -5 speed grade unit
5?34 altera corporation stratix ii device handbook, volume 1 april 2011 timing model internal timing parameters see tables 5?37 through 5?42 for internal timing parameters. table 5?37. le_ff internal timing microparameters symbol parameter -3 speed grade (1) -3 speed grade (2) -4 speed grade -5 speed grade unit min (3) max min (3) max min (4) max min (3) max t su le register setup time before clock 90 95 104 104 121 ps t h le register hold time after clock 149 157 172 172 200 ps t co le register clock-to-output delay 62 94 62 99 59 62 109 62 127 ps t clr minimum clear pulse width 204 214 234 234 273 ps t pre minimum preset pulse width 204 214 234 234 273 ps t clkl minimum clock low time 612 642 703 703 820 ps t clkh minimum clock high time 612 642 703 703 820 ps t lut 162 378 162 397 162 170 435 162 507 ps t adder 354 619 354 650 354 372 712 354 829 ps notes to table 5?37 : (1) these numbers apply to -3 speed grade ep2s15, ep2s30, ep2s60, and ep2s90 devices. (2) these numbers apply to -3 speed grade ep2s130 and ep2s180 devices. (3) for the -3 and -5 speed grades, the minimum timing is fo r the commercial temperature grade. only -4 speed grade devices offer the industrial temperature grade. (4) for the -4 speed grade, the first number is the mi nimum timing parameter for indu strial devices. the second number is the minimum timing pa rameter for commercial devices.
altera corporation 5?35 april 2011 stratix ii device handbook, volume 1 dc & switching characteristics table 5?38. ioe internal timing microparameters symbol parameter -3 speed grade (1) -3 speed grade (2) -4 speed grade -5 speed grade unit min (3) max min (3) max min (4) max min (3) max t su ioe input and output register setup time before clock 122 128 140 140 163 ps t h ioe input and output register hold time after clock 72 75 82 82 96 ps t co ioe input and output register clock-to- output delay 101 169 101 177 97 101 194 101 226 ps t pin2combout_r row input pin to ioe combinational output 410 760 410 798 391 410 873 410 1,018 ps t pin2combout_c column input pin to ioe combinational output 428 787 428 825 408 428 904 428 1,054 ps t combin2pin_r row ioe data input to combinational output pin 1,101 2,026 1,101 2,127 1,049 1,101 2,329 1,101 2,439 ps t combin2pin_c column ioe data input to combinational output pin 991 1,854 991 1,946 944 991 2,131 991 2,246 ps t clr minimum clear pulse width 200 210 229 229 268 ps t pre minimum preset pulse width 200 210 229 229 268 ps t clkl minimum clock low time 600 630 690 690 804 ps t clkh minimum clock high time 600 630 690 690 804 ps notes to table 5?38 : (1) these numbers apply to -3 speed grade ep2s15, ep2s30, ep2s60, and ep2s90 devices. (2) these numbers apply to -3 speed grade ep2s130 and ep2s180 devices. (3) for the -3 and -5 speed grades, the minimum timing is fo r the commercial temperature grade. only -4 speed grade devices offer the industrial temperature grade. (4) for the -4 speed grade, the first number is the mi nimum timing parameter for indu strial devices. the second number is the minimum timing pa rameter for commercial devices.
5?36 altera corporation stratix ii device handbook, volume 1 april 2011 timing model table 5?39. dsp block internal timing microparameters (part 1 of 2) symbol parameter -3 speed grade (1) -3 speed grade (2) -4 speed grade -5 speed grade unit min (3) max min (3) max min (4) max min (3) max t su input, pipeline, and output register setup time before clock 50 52 57 57 67 ps t h input, pipeline, and output register hold time after clock 180 189 206 206 241 ps t co input, pipeline, and output register clock- to-output delay 00 00 0 0 0 0 0 ps t inreg2pipe9 input register to dsp block pipeline register in 9 9-bit mode 1,312 2,030 1,312 2,030 1,250 1,312 2,334 1,312 2,720 ps t inreg2pipe18 input register to dsp block pipeline register in 18 18-bit mode 1,302 2,010 1,302 2,110 1,240 1,302 2,311 1,302 2,693 ps t inreg2pipe36 input register to dsp block pipeline register in 36 36-bit mode 1,302 2,010 1,302 2,110 1,240 1,302 2,311 1,302 2,693 ps t pipe2outreg2add dsp block pipeline register to output register delay in two- multipliers adder mode 924 1,450 924 1,522 880 924 1,667 924 1,943 ps t pipe2outreg4add dsp block pipeline register to output register delay in four- multipliers adder mode 1,134 1,850 1,134 1,942 1,080 1,134 2,127 1,134 2,479 ps t pd9 combinational input to output delay for 99 2,100 2,880 2,100 3,024 2,000 2,100 3,312 2,100 3,859 ps t pd18 combinational input to output delay for 18 18 2,110 2,990 2,110 3,139 2,010 2,110 3,438 2,110 4,006 ps t pd36 combinational input to output delay for 36 36 2,939 4,450 2,939 4,672 2,800 2,939 5,117 2,939 5,962 ps t clr minimum clear pulse width 2,212 2,322 2,543 2,543 2,964 ps
altera corporation 5?37 april 2011 stratix ii device handbook, volume 1 dc & switching characteristics t clkl minimum clock low time 1,190 1,249 1,368 1,368 1,594 ps t clkh minimum clock high time 1,190 1,249 1,368 1,368 1,594 ps notes to table 5?39 : (1) these numbers apply to -3 speed grade ep2s15, ep2s30, ep2s60, and ep2s90 devices. (2) these numbers apply to -3 speed grade ep2s130 and ep2s180 devices. (3) for the -3 and -5 speed grades, the minimum timing is fo r the commercial temperature grade. only -4 speed grade devices offer the industrial temperature grade. (4) for the -4 speed grade, the first number is the mi nimum timing parameter for indu strial devices. the second number is the minimum timing pa rameter for commercial devices. table 5?40. m512 block internal timing microparameters (part 1 of 2) note (1) symbol parameter -3 speed grade (2) -3 speed grade (3) -4 speed grade -5 speed grade unit min (4) max min (4) max min (5) max min (4) max t m512rc synchronous read cycle time 2,089 2,318 2,089 2.433 1,989 2,089 2,664 2,089 3,104 ps t m512weresu write or read enable setup time before clock 22 23 25 25 29 ps t m512wereh write or read enable hold time after clock 203 213 233 233 272 ps t m512datasu data setup time before clock 22 23 25 25 29 ps t m512datah data hold time after clock 203 213 233 233 272 ps t m512waddrsu write address setup time before clock 22 23 25 25 29 ps t m512waddrh write address hold time after clock 203 213 233 233 272 ps t m512raddrsu read address setup time before clock 22 23 25 25 29 ps t m512raddrh read address hold time after clock 203 213 233 233 272 ps table 5?39. dsp block internal timing microparameters (part 2 of 2) symbol parameter -3 speed grade (1) -3 speed grade (2) -4 speed grade -5 speed grade unit min (3) max min (3) max min (4) max min (3) max
5?38 altera corporation stratix ii device handbook, volume 1 april 2011 timing model t m512dataco1 clock-to-output delay when using output registers 298 478 298 501 284 298 548 298 640 ps t m512dataco2 clock-to-output delay without output registers 2,102 2,345 2,102 2,461 2,003 2,102 2,695 2,102 3,141 ps t m512clkl minimum clock low time 1,315 1,380 1,512 1,512 1,762 ps t m512clkh minimum clock high time 1,315 1,380 1,512 1,512 1,762 ps t m512clr minimum clear pulse width 144 151 165 165 192 ps notes to table 5?40 : (1) f max of m512 block obtained using the quartus ii soft ware does not necessarily equal to 1/tm512rc. (2) these numbers apply to -3 speed grade ep2s15, ep2s30, ep2s60, and ep2s90 devices. (3) these numbers apply to -3 speed grade ep2s130 and ep2s180 devices. (4) for the -3 and -5 speed grades, the minimum timing is fo r the commercial temperature grade. only -4 speed grade devices offer the industrial temperature grade. (5) for the -4 speed grade, the first number is the mi nimum timing parameter for indu strial devices. the second number is the minimum timing pa rameter for commercial devices. table 5?41. m4k block internal timing microparameters (part 1 of 2) note (1) symbol parameter -3 speed grade (2) -3 speed grade (3) -4 speed grade -5 speed grade unit min (4) max min (4) max min (5) max min (4) max t m4krc synchronous read cycle time 1,462 2,240 1,462 2,351 1,393 1,462 2,575 1,462 3,000 ps t m4kweresu write or read enable setup time before clock 22 23 25 25 29 ps t m4kwereh write or read enable hold time after clock 203 213 233 233 272 ps t m4kbesu byte enable setup time before clock 22 23 25 25 29 ps t m4kbeh byte enable hold time after clock 203 213 233 233 272 ps table 5?40. m512 block internal timing microparameters (part 2 of 2) note (1) symbol parameter -3 speed grade (2) -3 speed grade (3) -4 speed grade -5 speed grade unit min (4) max min (4) max min (5) max min (4) max
altera corporation 5?39 april 2011 stratix ii device handbook, volume 1 dc & switching characteristics t m4kdataasu a port data setup time before clock 22 23 25 25 29 ps t m4kdataah a port data hold time after clock 203 213 233 233 272 ps t m4kaddrasu a port address setup time before clock 22 23 25 25 29 ps t m4kaddrah a port address hold time after clock 203 213 233 233 272 ps t m4kdatabsu b port data setup time before clock 22 23 25 25 29 ps t m4kdatabh b port data hold time after clock 203 213 233 233 272 ps t m4kraddrbsu b port address setup time before clock 22 23 25 25 29 ps t m4kraddrbh b port address hold time after clock 203 213 233 233 272 ps t m4kdataco1 clock-to-output delay when using output registers 334 524 334 549 319 334 601 334 701 ps t m4kdataco2 (6) clock-to-output delay without output registers 1,616 2,453 1,616 2,574 1,540 1,616 2,820 1,616 3,286 ps t m4kclkh minimum clock high time 1,250 1,312 1,437 1,437 1,675 ps t m4kclkl minimum clock low time 1,250 1,312 1,437 1,437 1,675 ps t m4kclr minimum clear pulse width 144 151 165 165 192 ps notes to table 5?41 : (1) f max of m4k block obtained using the quartus ii so ftware does not necessarily equal to 1/tm4krc. (2) these numbers apply to -3 speed grade ep2s15, ep2s30, ep2s60, and ep2s90 devices. (3) these numbers apply to -3 speed grade ep2s130 and ep2s180 devices. (4) for the -3 and -5 speed grades, the minimum timing is fo r the commercial temperature grade. only -4 speed grade devices offer the industrial temperature grade. (5) for the -4 speed grade, the first number is the mi nimum timing parameter for indu strial devices. the second number is the minimum timing pa rameter for commercial devices. (6) numbers apply to unpacked memory modes, true dual-p ort memory modes, and simple dual-port memory modes that use locally routed or non-identical sources for the a and b port registers. table 5?41. m4k block internal timing microparameters (part 2 of 2) note (1) symbol parameter -3 speed grade (2) -3 speed grade (3) -4 speed grade -5 speed grade unit min (4) max min (4) max min (5) max min (4) max
5?40 altera corporation stratix ii device handbook, volume 1 april 2011 timing model table 5?42. m-ram block internal ti ming microparameters (part 1 of 2) note (1) symbol parameter -3 speed grade (2) -3 speed grade (3) -4 speed grade -5 speed grade unit min (4) max min (4) max min (5) max min (4) max t megarc synchronous read cycle time 1,866 2,774 1,866 2,911 1,777 1,866 3,189 1,777 1,866 3,716 ps t megaweresu write or read enable setup time before clock 144 151 165 165 192 ps t megawereh write or read enable hold time after clock 39 40 44 44 52 ps t megabesu byte enable setup time before clock 50 52 57 57 67 ps t megabeh byte enable hold time after clock 39 40 44 44 52 ps t megadataasu a port data setup time before clock 50 52 57 57 67 ps t megadataah a port data hold time after clock 243 255 279 279 325 ps t megaaddrasu a port address setup time before clock 589 618 677 677 789 ps t megaaddrah a port address hold time after clock 241 253 277 277 322 ps t megadatabsu b port setup time before clock 50 52 57 57 67 ps t megadatabh b port hold time after clock 243 255 279 279 325 ps t megaaddrbsu b port address setup time before clock 589 618 677 677 789 ps t megaaddrbh b port address hold time after clock 241 253 277 277 322 ps t megadataco1 clock-to-output delay when using output registers 480 715 480 749 457 480 821 480 957 ps t megadataco2 clock-to-output delay without output registers 1,950 2,899 1,950 3,042 1,857 1,950 3,332 1,950 3,884 ps t megaclkl minimum clock low time 1,250 1,312 1,437 1,437 1,675 ps
altera corporation 5?41 april 2011 stratix ii device handbook, volume 1 dc & switching characteristics stratix ii clock timing parameters see tables 5?43 through 5?67 for stratix ii clock timing parameters. t megaclkh minimum clock high time 1,250 1,312 1,437 1,437 1,675 ps t megaclr minimum clear pulse width 144 151 165 165 192 ps notes to table 5?42 : (1) f max of m-ram block obtained using the quartus ii so ftware does not necessarily equal to 1/tmegarc. (2) these numbers apply to -3 speed grade ep2s15, ep2s30, ep2s60, and ep2s90 devices. (3) these numbers apply to -3 speed grade ep2s130 and ep2s180 devices. (4) for the -3 and -5 speed grades, the minimum timing is fo r the commercial temperature grade. only -4 speed grade devices offer the industrial temperature grade. (5) for the -4 speed grade, the first number is the mi nimum timing parameter for indu strial devices. the second number is the minimum timing pa rameter for commercial devices. table 5?42. m-ram block internal ti ming microparameters (part 2 of 2) note (1) symbol parameter -3 speed grade (2) -3 speed grade (3) -4 speed grade -5 speed grade unit min (4) max min (4) max min (5) max min (4) max table 5?43. stratix ii clock timing parameters symbol parameter t cin delay from clock pad to i/o input register t cout delay from clock pad to i/o output register t pllcin delay from pll inclk pad to i/o input register t pllcout delay from pll inclk pad to i/o output register
5?42 altera corporation stratix ii device handbook, volume 1 april 2011 timing model ep2s15 clock timing parameters tables 5?44 though 5?47 show the maximum clock timing parameters for ep2s15 devices. table 5?44. ep2s15 column pins regional clock timing parameters parameter minimum timing -3 speed grade -4 speed grade -5 speed grade unit industrial commercial t cin 1.445 1.512 2.487 2.848 3.309 ns t cout 1.288 1.347 2.245 2.570 2.985 ns t pllcin 0.104 0.102 0.336 0.373 0.424 ns t pllcout -0.053 -0.063 0.094 0.095 0.1 ns table 5?45. ep2s15 column pins global clock timing parameters parameter minimum timing -3 speed grade -4 speed grade -5 speed grade unit industrial commercial t cin 1.419 1.487 2.456 2.813 3.273 ns t cout 1.262 1.322 2.214 2.535 2.949 ns t pllcin 0.094 0.092 0.326 0.363 0.414 ns t pllcout -0.063 -0.073 0.084 0.085 0.09 ns table 5?46. ep2s15 row pins regional clock timing parameters parameter minimum timing -3 speed grade -4 speed grade -5 speed grade unit industrial commercial t cin 1.232 1.288 2.144 2.454 2.848 ns t cout 1.237 1.293 2.140 2.450 2.843 ns t pllcin -0.109 -0.122 -0.007 -0.021 -0.037 ns t pllcout -0.104 -0.117 -0.011 -0.025 -0.042 ns
altera corporation 5?43 april 2011 stratix ii device handbook, volume 1 dc & switching characteristics ep2s30 clock timing parameters tables 5?48 through 5?51 show the maximum clock timing parameters for ep2s30 devices. table 5?47. ep2s15 row pins global clock timing parameters parameter minimum timing -3 speed grade -4 speed grade -5 speed grade unit industrial commercial t cin 1.206 1.262 2.113 2.422 2.815 ns t cout 1.211 1.267 2.109 2.418 2.810 ns t pllcin -0.125 -0.138 -0.023 -0.038 -0.056 ns t pllcout -0.12 -0.133 -0.027 -0.042 -0.061 ns table 5?48. ep2s30 column pins regional clock timing parameters parameter minimum timing -3 speed grade -4 speed grade -5 speed grade unit industrial commercial t cin 1.553 1.627 2.639 3.025 3.509 ns t cout 1.396 1.462 2.397 2.747 3.185 ns t pllcin 0.114 0.113 0.225 0.248 0.28 ns t pllcout -0.043 -0.052 -0.017 -0.03 -0.044 ns table 5?49. ep2s30 column pins global clock timing parameters parameter minimum timing -3 speed grade -4 speed grade -5 speed grade unit industrial commercial t cin 1.539 1.613 2.622 3.008 3.501 ns t cout 1.382 1.448 2.380 2.730 3.177 ns t pllcin 0.101 0.098 0.209 0.229 0.267 ns t pllcout -0.056 -0.067 -0.033 -0.049 -0.057 ns
5?44 altera corporation stratix ii device handbook, volume 1 april 2011 timing model ep2s60 clock timing parameters tables 5?52 through 5?55 show the maximum clock timing parameters for ep2s60 devices. table 5?50. ep2s30 row pins regional clock timing parameters parameter minimum timing -3 speed grade -4 speed grade -5 speed grade unit industrial commercial t cin 1.304 1.184 1.966 2.251 2.616 ns t cout 1.309 1.189 1.962 2.247 2.611 ns t pllcin -0.135 ?0.158 ?0.208 ?0.254 ?0.302 ns t pllcout -0.13 ?0.153 ?0.212 ?0.258 ?0.307 ns table 5?51. ep2s30 row pins global clock timing parameters parameter minimum timing -3 speed grade -4 speed grade -5 speed grade unit industrial commercial t cin 1.289 1.352 2.238 2.567 2.990 ns t cout 1.294 1.357 2.234 2.563 2.985 ns t pllcin -0.14 -0.154 -0.169 -0.205 -0.254 ns t pllcout -0.135 -0.149 -0.173 -0.209 -0.259 ns table 5?52. ep2s60 column pins regional clock timing parameters parameter minimum timing -3 speed grade -4 speed grade -5 speed grade unit industrial commercial t cin 1.681 1.762 2.945 3.381 3.931 ns t cout 1.524 1.597 2.703 3.103 3.607 ns t pllcin 0.066 0.064 0.279 0.311 0.348 ns t pllcout -0.091 -0.101 0.037 0.033 0.024 ns
altera corporation 5?45 april 2011 stratix ii device handbook, volume 1 dc & switching characteristics table 5?53. ep2s60 column pins global clock timing parameters parameter minimum timing -3 speed grade -4 speed grade -5 speed grade unit industrial commercial t cin 1.658 1.739 2.920 3.350 3.899 ns t cout 1.501 1.574 2.678 3.072 3.575 ns t pllcin 0.06 0.057 0.278 0.304 0.355 ns t pllcout -0.097 -0.108 0.036 0.026 0.031 ns table 5?54. ep2s60 row pins regional clock timing parameters parameter minimum timing -3 speed grade -4 speed grade -5 speed grade unit industrial commercial t cin 1.463 1.532 2.591 2.972 3.453 ns t cout 1.468 1.537 2.587 2.968 3.448 ns t pllcin -0.153 -0.167 -0.079 -0.099 -0.128 ns t pllcout -0.148 -0.162 -0.083 -0.103 -0.133 ns table 5?55. ep2s60 row pins global clock timing parameters parameter minimum timing -3 speed grade -4 speed grade -5 speed grade unit industrial commercial t cin 1.439 1.508 2.562 2.940 3.421 ns t cout 1.444 1.513 2.558 2.936 3.416 ns t pllcin -0.161 -0.174 -0.083 -0.107 -0.126 ns t pllcout -0.156 -0.169 -0.087 -0.111 -0.131 ns
5?46 altera corporation stratix ii device handbook, volume 1 april 2011 timing model ep2s90 clock timing parameters tables 5?56 through 5?59 show the maximum clock timing parameters for ep2s90 devices. table 5?56. ep2s90 column pins regional clock timing parameters parameter minimum timing -3 speed grade -4 speed grade -5 speed grade unit industrial commercial t cin 1.768 1.850 3.033 3.473 4.040 ns t cout 1.611 1.685 2.791 3.195 3.716 ns t pllcin -0.127 -0.117 0.125 0.129 0.144 ns t pllcout -0.284 -0.282 -0.117 -0.149 -0.18 ns table 5?57. ep2s90 column pins global clock timing parameters parameter minimum timing -3 speed grade -4 speed grade -5 speed grade unit industrial commercial t cin 1.783 1.868 3.058 3.502 4.070 ns t cout 1.626 1.703 2.816 3.224 3.746 ns t pllcin -0.137 -0.127 0.115 0.119 0.134 ns t pllcout -0.294 -0.292 -0.127 -0.159 -0.19 ns table 5?58. ep2s90 row pins regional clock timing parameters parameter minimum timing -3 speed grade -4 speed grade -5 speed grade unit industrial commercial t cin 1.566 1.638 2.731 3.124 3.632 ns t cout 1.571 1.643 2.727 3.120 3.627 ns t pllcin -0.326 -0.326 -0.178 -0.218 -0.264 ns t pllcout -0.321 -0.321 -0.182 -0.222 -0.269 ns
altera corporation 5?47 april 2011 stratix ii device handbook, volume 1 dc & switching characteristics ep2s130 clock timing parameters tables 5?60 through 5?63 show the maximum clock timing parameters for ep2s130 devices. table 5?59. ep2s90 row pins global clock timing parameters parameter minimum timing -3 speed grade -4 speed grade -5 speed grade unit industrial commercial t cin 1.585 1.658 2.757 3.154 3.665 ns t cout 1.590 1.663 2.753 3.150 3.660 ns t pllcin -0.341 -0.341 -0.193 -0.235 -0.278 ns t pllcout -0.336 -0.336 -0.197 -0.239 -0.283 ns table 5?60. ep2s130 column pins regional clock timing parameters parameter minimum timing -3 speed grade -4 speed grade -5 speed grade unit industrial commercial t cin 1.889 1.981 3.405 3.722 4.326 ns t cout 1.732 1.816 3.151 3.444 4.002 ns t pllcin 0.105 0.106 0.226 0.242 0.277 ns t pllcout -0.052 -0.059 -0.028 -0.036 -0.047 ns table 5?61. ep2s130 column pins global clock timing parameters parameter minimum timing -3 speed grade -4 speed grade -5 speed grade unit industrial commercial t cin 1.907 1.998 3.420 3.740 4.348 ns t cout 1.750 1.833 3.166 3.462 4.024 ns t pllcin 0.134 0.136 0.276 0.296 0.338 ns t pllcout -0.023 -0.029 0.022 0.018 0.014 ns
5?48 altera corporation stratix ii device handbook, volume 1 april 2011 timing model ep2s1 8 0 clock timing parameters tables 5?64 through 5?67 show the maximum clock timing parameters for ep2s180 devices. table 5?62. ep2s130 row pins regional clock timing parameters parameter minimum timing -3 speed grade -4 speed grade -5 speed grade unit industrial commercial t cin 1.680 1.760 3.070 3.351 3.892 ns t cout 1.685 1.765 3.066 3.347 3.887 ns t pllcin -0.113 -0.124 -0.12 -0.138 -0.168 ns t pllcout -0.108 -0.119 -0.124 -0.142 -0.173 ns table 5?63. ep2s130 row pins global clock timing parameters parameter minimum timing -3 speed grade -4 speed grade -5 speed grade unit industrial commercial t cin 1.690 1.770 3.075 3.362 3.905 ns t cout 1.695 1.775 3.071 3.358 3.900 ns t pllcin -0.087 -0.097 -0.075 -0.089 -0.11 ns t pllcout -0.082 -0.092 -0.079 -0.093 -0.115 ns table 5?64. ep2s180 column pins regional clock timing parameters parameter minimum timing -3 speed grade -4 speed grade -5 speed grade unit industrial commercial t cin 2.001 2.095 3.643 3.984 4.634 ns t cout 1.844 1.930 3.389 3.706 4.310 ns t pllcin -0.307 -0.297 0.053 0.046 0.048 ns t pllcout -0.464 -0.462 -0.201 -0.232 -0.276 ns
altera corporation 5?49 april 2011 stratix ii device handbook, volume 1 dc & switching characteristics table 5?65. ep2s180 column pins global clock timing parameters parameter minimum timing -3 speed grade -4 speed grade -5 speed grade unit industrial commercial t cin 2.003 2.100 3.652 3.993 4.648 ns t cout 1.846 1.935 3.398 3.715 4.324 ns t pllcin -0.3 -0.29 0.053 0.054 0.058 ns t pllcout -0.457 -0.455 -0.201 -0.224 -0.266 ns table 5?66. ep2s180 row pins regional clock timing parameters parameter minimum timing -3 speed grade -4 speed grade -5 speed grade unit industrial commercial t cin 1.759 1.844 3.273 3.577 4.162 ns t cout 1.764 1.849 3.269 3.573 4.157 ns t pllcin -0.542 -0.541 -0.317 -0.353 -0.414 ns t pllcout -0.537 -0.536 -0.321 -0.357 -0.419 ns table 5?67. ep2s180 row pins global clock timing parameters parameter minimum timing -3 speed grade -4 speed grade -5 speed grade unit industrial commercial t cin 1.763 1.850 3.285 3.588 4.176 ns t cout 1.768 1.855 3.281 3.584 4.171 ns t pllcin -0.542 -0.542 -0.319 -0.355 -0.42 ns t pllcout -0.537 -0.537 -0.323 -0.359 -0.425 ns
5?50 altera corporation stratix ii device handbook, volume 1 april 2011 timing model clock network skew adders the quartus ii software models skew within dedicated clock networks such as global and regi onal clocks. therefore, intra-clock network skew adder is not specified. table 5?68 specifies the clock skew between any two clock networks driving registers in the ioe. table 5?68. clock network specifications name description min typ max unit clock skew adder ep2s15, ep2s30, ep2s60 (1) inter-clock network, same side 50 ps inter-clock network, entire chip 100 ps clock skew adder ep2s90 (1) inter-clock network, same side 55 ps inter-clock network, entire chip 110 ps clock skew adder ep2s130 (1) inter-clock network, same side 63 ps inter-clock network, entire chip 125 ps clock skew adder ep2s180 (1) inter-clock network, same side 75 ps inter-clock network, entire chip 150 ps note to table 5?68 : (1) this is in addition to intra-clock network sk ew, which is modeled in the quartus ii software.
altera corporation 5?51 april 2011 stratix ii device handbook, volume 1 dc & switching characteristics ioe programmable delay see tables 5?69 and 5?70 for ioe programmable delay. table 5?69. stratix ii ioe progra mmable delay on column pins note (1) parameter paths affected available settings minimum timing (2) -3 speed grade (3) -4 speed grade -5 speed grade min offset (ps) max offset (ps) min offset (ps) max offset (ps) min offset (ps) max offset (ps) min offset (ps) max offset (ps) input delay from pin to internal cells pad to i/o dataout to logic array 80 0 1,696 1,781 0 0 2,881 3,025 0 3,313 0 3,860 input delay from pin to input register pad to i/o input register 64 0 0 1,955 2,053 0 0 3,275 3,439 0 3,766 0 4,388 delay from output register to output pin i/o output register to pad 20 0 316 332 0 0 500 525 0 575 0 670 output enable pin delay t xz , t zx 20 0 305 320 0 0 483 507 0 556 0 647 notes to table 5?69 : (1) the incremental values for the settings are generally linea r. for the exact delay associated with each setting, use the latest version of the quartus ii software. (2) the first number is the minimum timing parameter for industrial devices. the second number is the minimum timing parameter for commercial devices. (3) the first number applies to -3 speed grade ep2s15, ep2s30, ep2s60, and ep2s90 devices. the second number applies to -3 speed grade ep2s130 and ep2s180 devices.
5?52 altera corporation stratix ii device handbook, volume 1 april 2011 timing model default capacitive loading of different i/o standards see table 5?71 for default capacitive loading of different i/o standards. table 5?70. stratix ii ioe prog rammable delay on row pins note (1) parameter paths affected available settings minimum timing (2) -3 speed grade (3) -4 speed grade -5 speed grade min offset (ps) max offset (ps) min offset (ps) max offset (ps) min offset (ps) max offset (ps) min offset (ps) max offset (ps) input delay from pin to internal cells pad to i/o dataout to logic array 80 0 1,697 1,782 0 0 2,876 3,020 0 3,308 0 3,853 input delay from pin to input register pad to i/o input register 64 0 0 1,956 2,054 0 0 3,270 3,434 0 3,761 0 4,381 delay from output register to output pin i/o output register to pad 20 0 316 332 0 0 525 525 0 575 0 670 output enable pin delay t xz , t zx 20 0 305 320 0 0 507 507 0 556 0 647 notes to table 5?70 : (1) the incremental values for the settings are generally linear. for the exact delay associated with each setting, use the latest version of the quartus ii software. (2) the first number is the minimum timing parameter for industrial devices. the second number is the minimum timing parameter for commercial devices. (3) the first number applies to -3 speed grade ep2s15, ep2s30, ep2s60, and ep2s90 devices. the second number applies to -3 speed grade ep2s130 and ep2s180 devices. table 5?71. default loading of different i/ o standards for stratix ii (part 1 of 2) i/o standard capacitive load unit lvttl 0 pf lv c m o s 0 p f 2.5 v 0 pf 1.8 v 0 pf 1.5 v 0 pf pci 10 pf pci-x 10 pf sstl-2 class i 0 pf
altera corporation 5?53 april 2011 stratix ii device handbook, volume 1 dc & switching characteristics sstl-2 class ii 0 pf sstl-18 class i 0 pf sstl-18 class ii 0 pf 1.5-v hstl class i 0 pf 1.5-v hstl class ii 0 pf 1.8-v hstl class i 0 pf 1.8-v hstl class ii 0 pf 1.2-v hstl with oct 0 pf differential sstl-2 class i 0 pf differential sstl-2 class ii 0 pf differential sstl-18 class i 0 pf differential sstl-18 class ii 0 pf 1.5-v differential hstl class i 0 pf 1.5-v differential hstl class ii 0 pf 1.8-v differential hstl class i 0 pf 1.8-v differential hstl class ii 0 pf lv d s 0 p f hypertransport 0 pf lvpecl 0 pf table 5?71. default loading of different i/ o standards for stratix ii (part 2 of 2) i/o standard capacitive load unit
5?54 altera corporation stratix ii device handbook, volume 1 april 2011 timing model i/o delays see tables 5?72 through 5?76 for i/o delays. table 5?72. i/o delay parameters symbol parameter t dip delay from i/o datain to output pad t op delay from i/o output register to output pad t pcout delay from input pad to i/o dataout to core t pi delay from input pad to i/o input register table 5?73. stratix ii i/o input delay for column pins (part 1 of 3) i/o standard parameter minimum timing -3 speed grade (2) -3 speed grade (3) -4 speed grade -5 speed grade unit industrial commercial lv t t l t pi 674 707 1223 1282 1405 1637 ps t pcout 408 428 787 825 904 1054 ps 2.5 v t pi 684 717 1210 1269 1390 1619 ps t pcout 418 438 774 812 889 1036 ps 1.8 v t pi 747 783 1366 1433 1570 1829 ps t pcout 481 504 930 976 1069 1246 ps 1.5 v t pi 749 786 1436 1506 1650 1922 ps t pcout 483 507 1000 1049 1149 1339 ps lv c m o s t pi 674 707 1223 1282 1405 1637 ps t pcout 408 428 787 825 904 1054 ps sstl-2 class i t pi 507 530 818 857 939 1094 ps t pcout 241 251 382 400 438 511 ps sstl-2 class ii t pi 507 530 818 857 939 1094 ps t pcout 241 251 382 400 438 511 ps sstl-18 class i t pi 543 569 898 941 1031 1201 ps t pcout 277 290 462 484 530 618 ps sstl-18 class ii t pi 543 569 898 941 1031 1201 ps t pcout 277 290 462 484 530 618 ps 1.5-v hstl class i t pi 560 587 993 1041 1141 1329 ps t pcout 294 308 557 584 640 746 ps
altera corporation 5?55 april 2011 stratix ii device handbook, volume 1 dc & switching characteristics 1.5-v hstl class ii t pi 560 587 993 1041 1141 1329 ps t pcout 294 308 557 584 640 746 ps 1.8-v hstl class i t pi 543 569 898 941 1031 1201 ps t pcout 277 290 462 484 530 618 ps 1.8-v hstl class ii t pi 543 569 898 941 1031 1201 ps t pcout 277 290 462 484 530 618 ps pci t pi 679 712 1214 1273 1395 1625 ps t pcout 413 433 778 816 894 1042 ps pci-x t pi 679 712 1214 1273 1395 1625 ps t pcout 413 433 778 816 894 1042 ps differential sstl-2 class i (1) t pi 507 530 818 857 939 1094 ps t pcout 241 251 382 400 438 511 ps differential sstl-2 class ii (1) t pi 507 530 818 857 939 1094 ps t pcout 241 251 382 400 438 511 ps differential sstl-18 class i (1) t pi 543 569 898 941 1031 1201 ps t pcout 277 290 462 484 530 618 ps differential sstl-18 class ii (1) t pi 543 569 898 941 1031 1201 ps t pcout 277 290 462 484 530 618 ps 1.8-v differential hstl class i (1) t pi 543 569 898 941 1031 1201 ps t pcout 277 290 462 484 530 618 ps 1.8-v differential hstl class ii (1) t pi 543 569 898 941 1031 1201 ps t pcout 277 290 462 484 530 618 ps 1.5-v differential hstl class i (1) t pi 560 587 993 1041 1141 1329 ps t pcout 294 308 557 584 640 746 ps 1.5-v differential hstl class ii (1) t pi 560 587 993 1041 1141 1329 ps t pcout 294 308 557 584 640 746 ps table 5?73. stratix ii i/o input delay for column pins (part 2 of 3) i/o standard parameter minimum timing -3 speed grade (2) -3 speed grade (3) -4 speed grade -5 speed grade unit industrial commercial
5?56 altera corporation stratix ii device handbook, volume 1 april 2011 timing model 1.2-v hstl t pi 645 677 1194 1252 - - ps t pcout 379 398 758 795 - - ps notes for ta b l e 5 ? 7 3 : (1) these i/o standards are only supported on dqs pins. (2) these numbers apply to -3 speed grade ep2s15, ep2s30, ep2s60, and ep2s90 devices. (3) these numbers apply to -3 speed grade ep2s130 and ep2s180 devices. table 5?74. stratix ii i/o input de lay for row pins (part 1 of 2) i/o standard parameter minimum timing -3 speed grade (1) -3 speed grade (2) -4 speed grade -5 speed grade unit industrial commercial lv t t l t pi 715 749 1287 1350 1477 1723 ps t pcout 391 410 760 798 873 1018 ps 2.5 v t pi 726 761 1273 1335 1461 1704 ps t pcout 402 422 746 783 857 999 ps 1.8 v t pi 788 827 1427 1497 1639 1911 ps t pcout 464 488 900 945 1035 1206 ps 1.5 v t pi 792 830 1498 1571 1720 2006 ps t pcout 468 491 971 1019 1116 1301 ps lv c m o s t pi 715 749 1287 1350 1477 1723 ps t pcout 391 410 760 798 873 1018 ps sstl-2 class i t pi 547 573 879 921 1008 1176 ps t pcout 223 234 352 369 404 471 ps sstl-2 class ii t pi 547 573 879 921 1008 1176 ps t pcout 223 234 352 369 404 471 ps sstl-18 class i t pi 577 605 960 1006 1101 1285 ps t pcout 253 266 433 454 497 580 ps sstl-18 class ii t pi 577 605 960 1006 1101 1285 ps t pcout 253 266 433 454 497 580 ps 1.5-v hstl class i t pi 602 631 1056 1107 1212 1413 ps t pcout 278 292 529 555 608 708 ps table 5?73. stratix ii i/o input delay for column pins (part 3 of 3) i/o standard parameter minimum timing -3 speed grade (2) -3 speed grade (3) -4 speed grade -5 speed grade unit industrial commercial
altera corporation 5?57 april 2011 stratix ii device handbook, volume 1 dc & switching characteristics 1.5-v hstl class ii t pi 602 631 1056 1107 1212 1413 ps t pcout 278 292 529 555 608 708 ps 1.8-v hstl class i t pi 577 605 960 1006 1101 1285 ps t pcout 253 266 433 454 497 580 ps 1.8-v hstl class ii t pi 577 605 960 1006 1101 1285 ps t pcout 253 266 433 454 497 580 ps lv d s t pi 515 540 948 994 1088 1269 ps t pcout 191 201 421 442 484 564 ps hypertransport t pi 515 540 948 994 1088 1269 ps t pcout 191 201 421 442 484 564 ps notes for ta b l e 5 ? 7 4 : (1) these numbers apply to -3 speed grade ep2s15, ep2s30, ep2s60, and ep2s90 devices. (2) these numbers apply to -3 speed grade ep2s130 and ep2s180 devices. table 5?75. stratix ii i/o output de lay for column pins (part 1 of 8) i/o standard drive strength parameter minimum timing -3 speed grade (3) -3 speed grade (4) -4 speed grade -5 speed grade unit industrial commercial lvttl 4 ma t op 1178 1236 2351 2467 2702 2820 ps t dip 1198 1258 2417 2537 2778 2910 ps 8 ma t op 1041 1091 2036 2136 2340 2448 ps t dip 1061 1113 2102 2206 2416 2538 ps 12 ma t op 976 1024 2036 2136 2340 2448 ps t dip 996 1046 2102 2206 2416 2538 ps 16 ma t op 951 998 1893 1986 2176 2279 ps t dip 971 1020 1959 2056 2252 2369 ps 20 ma t op 931 976 1787 1875 2054 2154 ps t dip 951 998 1853 1945 2130 2244 ps 24 ma (1) t op 924 969 1788 1876 2055 2156 ps t dip 944 991 1854 1946 2131 2246 ps table 5?74. stratix ii i/o input de lay for row pins (part 2 of 2) i/o standard parameter minimum timing -3 speed grade (1) -3 speed grade (2) -4 speed grade -5 speed grade unit industrial commercial
5?58 altera corporation stratix ii device handbook, volume 1 april 2011 timing model lv c m o s 4 m a t op 1041 1091 2036 2136 2340 2448 ps t dip 1061 1113 2102 2206 2416 2538 ps 8 ma t op 952 999 1786 1874 2053 2153 ps t dip 972 1021 1852 1944 2129 2243 ps 12 ma t op 926 971 1720 1805 1977 2075 ps t dip 946 993 1786 1875 2053 2165 ps 16 ma t op 933 978 1693 1776 1946 2043 ps t dip 953 1000 1759 1846 2022 2133 ps 20 ma t op 921 965 1677 1759 1927 2025 ps t dip 941 987 1743 1829 2003 2115 ps 24 ma (1) t op 909 954 1659 1741 1906 2003 ps t dip 929 976 1725 1811 1982 2093 ps 2.5 v 4 ma t op 1004 1053 2063 2165 2371 2480 ps t dip 1024 1075 2129 2235 2447 2570 ps 8 ma t op 955 1001 1841 1932 2116 2218 ps t dip 975 1023 1907 2002 2192 2308 ps 12 ma t op 934 980 1742 1828 2002 2101 ps t dip 954 1002 1808 1898 2078 2191 ps 16 ma (1) t op 918 962 1679 1762 1929 2027 ps t dip 938 984 1745 1832 2005 2117 ps table 5?75. stratix ii i/o output de lay for column pins (part 2 of 8) i/o standard drive strength parameter minimum timing -3 speed grade (3) -3 speed grade (4) -4 speed grade -5 speed grade unit industrial commercial
altera corporation 5?59 april 2011 stratix ii device handbook, volume 1 dc & switching characteristics 1.8 v 2 ma t op 1042 1093 2904 3048 3338 3472 ps t dip 1062 1115 2970 3118 3414 3562 ps 4 ma t op 1047 1098 2248 2359 2584 2698 ps t dip 1067 1120 2314 2429 2660 2788 ps 6 ma t op 974 1022 2024 2124 2326 2434 ps t dip 994 1044 2090 2194 2402 2524 ps 8 ma t op 976 1024 1947 2043 2238 2343 ps t dip 996 1046 2013 2113 2314 2433 ps 10 ma t op 933 978 1882 1975 2163 2266 ps t dip 953 1000 1948 2045 2239 2356 ps 12 ma (1) t op 934 979 1833 1923 2107 2209 ps t dip 954 1001 1899 1993 2183 2299 ps 1.5 v 2 ma t op 1023 1073 2505 2629 2879 3002 ps t dip 1043 1095 2571 2699 2955 3092 ps 4 ma t op 963 1009 2023 2123 2325 2433 ps t dip 983 1031 2089 2193 2401 2523 ps 6 ma t op 966 1012 1923 2018 2210 2315 ps t dip 986 1034 1989 2088 2286 2405 ps 8 ma (1) t op 926 971 1878 1970 2158 2262 ps t dip 946 993 1944 2040 2234 2352 ps sstl-2 class i 8 ma t op 913 957 1715 1799 1971 2041 ps t dip 933 979 1781 1869 2047 2131 ps 12 ma (1) t op 896 940 1672 1754 1921 1991 ps t dip 916 962 1738 1824 1997 2081 ps sstl-2 class ii 16 ma t op 876 918 1609 1688 1849 1918 ps t dip 896 940 1675 1758 1925 2008 ps 20 ma t op 877 919 1598 1676 1836 1905 ps t dip 897 941 1664 1746 1912 1995 ps 24 ma (1) t op 872 915 1596 1674 1834 1903 ps t dip 892 937 1662 1744 1910 1993 ps table 5?75. stratix ii i/o output de lay for column pins (part 3 of 8) i/o standard drive strength parameter minimum timing -3 speed grade (3) -3 speed grade (4) -4 speed grade -5 speed grade unit industrial commercial
5?60 altera corporation stratix ii device handbook, volume 1 april 2011 timing model sstl-18 class i 4 ma t op 909 953 1690 1773 1942 2012 ps t dip 929 975 1756 1843 2018 2102 ps 6 ma t op 914 958 1656 1737 1903 1973 ps t dip 934 980 1722 1807 1979 2063 ps 8 ma t op 894 937 1640 1721 1885 1954 ps t dip 914 959 1706 1791 1961 2044 ps 10 ma t op 898 942 1638 1718 1882 1952 ps t dip 918 964 1704 1788 1958 2042 ps 12 ma (1) t op 891 936 1626 1706 1869 1938 ps t dip 911 958 1692 1776 1945 2028 ps sstl-18 class ii 8 ma t op 883 925 1597 1675 1835 1904 ps t dip 903 947 1663 1745 1911 1994 ps 16 ma t op 894 937 1578 1655 1813 1882 ps t dip 914 959 1644 1725 1889 1972 ps 18 ma t op 890 933 1585 1663 1821 1890 ps t dip 910 955 1651 1733 1897 1980 ps 20 ma (1) t op 890 933 1583 1661 1819 1888 ps t dip 910 955 1649 1731 1895 1978 ps 1.8-v hstl class i 4 ma t op 912 956 1608 1687 1848 1943 ps t dip 932 978 1674 1757 1924 2033 ps 6 ma t op 917 962 1595 1673 1833 1928 ps t dip 937 984 1661 1743 1909 2018 ps 8 ma t op 896 940 1586 1664 1823 1917 ps t dip 916 962 1652 1734 1899 2007 ps 10 ma t op 900 944 1591 1669 1828 1923 ps t dip 920 966 1657 1739 1904 2013 ps 12 ma (1) t op 892 936 1585 1663 1821 1916 ps t dip 912 958 1651 1733 1897 2006 ps table 5?75. stratix ii i/o output de lay for column pins (part 4 of 8) i/o standard drive strength parameter minimum timing -3 speed grade (3) -3 speed grade (4) -4 speed grade -5 speed grade unit industrial commercial
altera corporation 5?61 april 2011 stratix ii device handbook, volume 1 dc & switching characteristics 1.8-v hstl class ii 16 ma t op 877 919 1385 1453 1591 1680 ps t dip 897 941 1451 1523 1667 1770 ps 18 ma t op 879 921 1394 1462 1602 1691 ps t dip 899 943 1460 1532 1678 1781 ps 20 ma (1) t op 879 921 1402 1471 1611 1700 ps t dip 899 943 1468 1541 1687 1790 ps 1.5-v hstl class i 4 ma t op 912 956 1607 1686 1847 1942 ps t dip 932 978 1673 1756 1923 2032 ps 6 ma t op 917 961 1588 1666 1825 1920 ps t dip 937 983 1654 1736 1901 2010 ps 8 ma t op 899 943 1590 1668 1827 1922 ps t dip 919 965 1656 1738 1903 2012 ps 10 ma t op 900 943 1592 1670 1829 1924 ps t dip 920 965 1658 1740 1905 2014 ps 12 ma (1) t op 893 937 1590 1668 1827 1922 ps t dip 913 959 1656 1738 1903 2012 ps 1.5-v hstl class ii 16 ma t op 881 924 1431 1501 1644 1734 ps t dip 901 946 1497 1571 1720 1824 ps 18 ma t op 884 927 1439 1510 1654 1744 ps t dip 904 949 1505 1580 1730 1834 ps 20 ma (1) t op 886 929 1450 1521 1666 1757 ps t dip 906 951 1516 1591 1742 1847 ps 1.2-v hstl t op 958 1004 1602 1681 - - ps t dip 978 1026 1668 1751 - - ps pci t op 1028 1082 1956 2051 2244 2070 ps t dip 1048 1104 2022 2121 2320 2160 ps pci-x t op 1028 1082 1956 2051 2244 2070 ps t dip 1048 1104 2022 2121 2320 2160 ps table 5?75. stratix ii i/o output de lay for column pins (part 5 of 8) i/o standard drive strength parameter minimum timing -3 speed grade (3) -3 speed grade (4) -4 speed grade -5 speed grade unit industrial commercial
5?62 altera corporation stratix ii device handbook, volume 1 april 2011 timing model differential sstl-2 class i 8 ma t op 913 957 1715 1799 1971 2041 ps t dip 933 979 1781 1869 2047 2131 ps 12 ma t op 896 940 1672 1754 1921 1991 ps t dip 916 962 1738 1824 1997 2081 ps differential sstl-2 class ii 16 ma t op 876 918 1609 1688 1849 1918 ps t dip 896 940 1675 1758 1925 2008 ps 20 ma t op 877 919 1598 1676 1836 1905 ps t dip 897 941 1664 1746 1912 1995 ps 24 ma t op 872 915 1596 1674 1834 1903 ps t dip 892 937 1662 1744 1910 1993 ps differential sstl-18 class i 4 ma t op 909 953 1690 1773 1942 2012 ps t dip 929 975 1756 1843 2018 2102 ps 6 ma t op 914 958 1656 1737 1903 1973 ps t dip 934 980 1722 1807 1979 2063 ps 8 ma t op 894 937 1640 1721 1885 1954 ps t dip 914 959 1706 1791 1961 2044 ps 10 ma t op 898 942 1638 1718 1882 1952 ps t dip 918 964 1704 1788 1958 2042 ps 12 ma t op 891 936 1626 1706 1869 1938 ps t dip 911 958 1692 1776 1945 2028 ps differential sstl-18 class ii 8 ma t op 883 925 1597 1675 1835 1904 ps t dip 903 947 1663 1745 1911 1994 ps 16 ma t op 894 937 1578 1655 1813 1882 ps t dip 914 959 1644 1725 1889 1972 ps 18 ma t op 890 933 1585 1663 1821 1890 ps t dip 910 955 1651 1733 1897 1980 ps 20 ma t op 890 933 1583 1661 1819 1888 ps t dip 910 955 1649 1731 1895 1978 ps table 5?75. stratix ii i/o output de lay for column pins (part 6 of 8) i/o standard drive strength parameter minimum timing -3 speed grade (3) -3 speed grade (4) -4 speed grade -5 speed grade unit industrial commercial
altera corporation 5?63 april 2011 stratix ii device handbook, volume 1 dc & switching characteristics 1.8-v differential hstl class i 4 ma t op 912 956 1608 1687 1848 1943 ps t dip 932 978 1674 1757 1924 2033 ps 6 ma t op 917 962 1595 1673 1833 1928 ps t dip 937 984 1661 1743 1909 2018 ps 8 ma t op 896 940 1586 1664 1823 1917 ps t dip 916 962 1652 1734 1899 2007 ps 10 ma t op 900 944 1591 1669 1828 1923 ps t dip 920 966 1657 1739 1904 2013 ps 12 ma t op 892 936 1585 1663 1821 1916 ps t dip 912 958 1651 1733 1897 2006 ps 1.8-v differential hstl class ii 16 ma t op 877 919 1385 1453 1591 1680 ps t dip 897 941 1451 1523 1667 1770 ps 18 ma t op 879 921 1394 1462 1602 1691 ps t dip 899 943 1460 1532 1678 1781 ps 20 ma t op 879 921 1402 1471 1611 1700 ps t dip 899 943 1468 1541 1687 1790 ps 1.5-v differential hstl class i 4 ma t op 912 956 1607 1686 1847 1942 ps t dip 932 978 1673 1756 1923 2032 ps 6 ma t op 917 961 1588 1666 1825 1920 ps t dip 937 983 1654 1736 1901 2010 ps 8 ma t op 899 943 1590 1668 1827 1922 ps t dip 919 965 1656 1738 1903 2012 ps 10 ma t op 900 943 1592 1670 1829 1924 ps t dip 920 965 1658 1740 1905 2014 ps 12 ma t op 893 937 1590 1668 1827 1922 t dip 913 959 1656 1738 1903 2012 table 5?75. stratix ii i/o output de lay for column pins (part 7 of 8) i/o standard drive strength parameter minimum timing -3 speed grade (3) -3 speed grade (4) -4 speed grade -5 speed grade unit industrial commercial
5?64 altera corporation stratix ii device handbook, volume 1 april 2011 timing model 1.5-v differential hstl class ii 16 ma t op 881 924 1431 1501 1644 1734 ps t dip 901 946 1497 1571 1720 1824 ps 18 ma t op 884 927 1439 1510 1654 1744 t dip 904 949 1505 1580 1730 1834 20 ma t op 886 929 1450 1521 1666 1757 t dip 906 951 1516 1591 1742 1847 notes to table 5?75 : (1) this is the default setting in the quartus ii software. (2) these i/o standards are only supported on dqs pins. (3) these numbers apply to -3 speed grade ep2s15, ep2s30, ep2s60, and ep2s90 devices. (4) these numbers apply to -3 speed grade ep2s130 and ep2s180 devices. table 5?76. stratix ii i/o output delay for row pins (part 1 of 3) i/o standard drive strength parameter minimum timing -3 speed grade (2) -3 speed grade (3) -4 speed grade -5 speed grade unit industrial commercial lv t t l 4 m a t op 1267 1328 2655 2786 3052 3189 ps t dip 1225 1285 2600 2729 2989 3116 ps 8 ma t op 1144 1200 2113 2217 2429 2549 ps t dip 1102 1157 2058 2160 2366 2476 ps 12 ma (1) t op 1091 1144 2081 2184 2392 2512 ps t dip 1049 1101 2026 2127 2329 2439 ps lv c m o s 4 m a t op 1144 1200 2113 2217 2429 2549 ps t dip 1102 1157 2058 2160 2366 2476 ps 8 ma (1) t op 1044 1094 1853 1944 2130 2243 ps t dip 1002 1051 1798 1887 2067 2170 ps table 5?75. stratix ii i/o output de lay for column pins (part 8 of 8) i/o standard drive strength parameter minimum timing -3 speed grade (3) -3 speed grade (4) -4 speed grade -5 speed grade unit industrial commercial
altera corporation 5?65 april 2011 stratix ii device handbook, volume 1 dc & switching characteristics 2.5 v 4 ma t op 1128 1183 2091 2194 2403 2523 ps t dip 1086 1140 2036 2137 2340 2450 ps 8 ma t op 1030 1080 1872 1964 2152 2265 ps t dip 988 1037 1817 1907 2089 2192 ps 12 ma (1) t op 1012 1061 1775 1862 2040 2151 ps t dip 970 1018 1720 1805 1977 2078 ps 1.8 v 2 ma t op 1196 1253 2954 3100 3396 3542 ps t dip 1154 1210 2899 3043 3333 3469 ps 4 ma t op 1184 1242 2294 2407 2637 2763 ps t dip 1142 1199 2239 2350 2574 2690 ps 6 ma t op 1079 1131 2039 2140 2344 2462 ps t dip 1037 1088 1984 2083 2281 2389 ps 8 ma (1) t op 1049 1100 1942 2038 2232 2348 ps t dip 1007 1057 1887 1981 2169 2275 ps 1.5 v 2 ma t op 1158 1213 2530 2655 2908 3041 ps t dip 1116 1170 2475 2598 2845 2968 ps 4 ma t op 1055 1106 2020 2120 2322 2440 ps t dip 1013 1063 1965 2063 2259 2367 ps sstl-2 class i 8 ma t op 1002 1050 1759 1846 2022 2104 ps t dip 960 1007 1704 1789 1959 2031 ps sstl-2 class ii 16 ma (1) t op 947 992 1581 1659 1817 1897 ps t dip 905 949 1526 1602 1754 1824 ps sstl-18 class i 4 ma t op 990 1038 1709 1793 1964 2046 ps t dip 948 995 1654 1736 1901 1973 ps 6 ma t op 994 1042 1648 1729 1894 1975 ps t dip 952 999 1593 1672 1831 1902 ps 8 ma t op 970 1018 1633 1713 1877 1958 ps t dip 928 975 1578 1656 1814 1885 ps 10 ma (1) t op 974 1021 1615 1694 1856 1937 ps t dip 932 978 1560 1637 1793 1864 ps table 5?76. stratix ii i/o output delay for row pins (part 2 of 3) i/o standard drive strength parameter minimum timing -3 speed grade (2) -3 speed grade (3) -4 speed grade -5 speed grade unit industrial commercial
5?66 altera corporation stratix ii device handbook, volume 1 april 2011 timing model maximum input & output clock toggle rate maximum clock toggle rate is de fined as the maximum frequency achievable for a clock type signal at an i/o pin. the i/o pin can be a regular i/o pin or a de dicated clock i/o pin. 1.8-v hstl class i 4 ma t op 972 1019 1610 1689 1850 1956 ps t dip 930 976 1555 1632 1787 1883 ps 6 ma t op 975 1022 1580 1658 1816 1920 ps t dip 933 979 1525 1601 1753 1847 ps 8 ma t op 958 1004 1576 1653 1811 1916 ps t dip 916 961 1521 1596 1748 1843 ps 10 ma t op 962 1008 1567 1644 1801 1905 ps t dip 920 965 1512 1587 1738 1832 ps 12 ma (1) t op 953 999 1566 1643 1800 1904 ps t dip 911 956 1511 1586 1737 1831 ps 1.5-v hstl class i 4 ma t op 970 1018 1591 1669 1828 1933 ps t dip 928 975 1536 1612 1765 1860 ps 6 ma t op 974 1021 1579 1657 1815 1919 ps t dip 932 978 1524 1600 1752 1846 ps 8 ma (1) t op 960 1006 1572 1649 1807 1911 ps t dip 918 963 1517 1592 1744 1838 ps lv d s t op 1018 1067 1723 1808 1980 2089 ps t dip 976 1024 1668 1751 1917 2016 ps hypertransport t op 1005 1053 1723 1808 1980 2089 ps t dip 963 1010 1668 1751 1917 2016 ps notes to table 5?76 : (1) this is the default setting in the quartus ii software. (2) these numbers apply to -3 speed grade ep2s15, ep2s30, ep2s60, and ep2s90 devices. (3) these numbers apply to -3 speed grade ep2s130 and ep2s180 devices. table 5?76. stratix ii i/o output delay for row pins (part 3 of 3) i/o standard drive strength parameter minimum timing -3 speed grade (2) -3 speed grade (3) -4 speed grade -5 speed grade unit industrial commercial
altera corporation 5?67 april 2011 stratix ii device handbook, volume 1 dc & switching characteristics the maximum clock toggle rate is different from the maximum data bit rate. if the maximum clock toggle rate on a regular i/o pin is 300 mhz, the maximum data bit rate for dual data rate (ddr) could be potentially as high as 600 mbps on the same i/o pin. table 5?77 specifies the maximum in put clock toggle rates. table 5?78 specifies the maximum output clock toggle rates at 0pf load. table 5?79 specifies the derating factors for the output clock toggle rate for a non 0pf load. to calculate the output toggle rate for a non 0pf load, use this formula: the toggle rate for a non 0pf load = 1000 / (1000/ toggle rate at 0pf load + derating factor * load value in pf /1000) for example, the output toggle rate at 0pf load for sstl-18 class ii 20ma i/o standard is 550 mhz on a -3 devi ce clock output pin. the derating factor is 94ps/pf. for a 10pf load the toggle rate is calculated as: 1000 / (1000/550 + 94 10 /1000) = 363 (mhz) tables 5?77 through 5?79 show the i/o toggle rates for stratix ii devices. table 5?77. maximum input toggle rate on stratix ii devices (part 1 of 2) input i/o standard column i/o pins (mhz ) row i/o pins (mhz) dedicated clock inputs (mhz) -3 -4 -5 -3 -4 -5 -3 -4 -5 lvttl 500 500 450 500 500 450 500 500 400 2.5-v lvttl/cmos 500 500 450 500 500 450 500 500 400 1.8-v lvttl/cmos 500 500 450 500 500 450 500 500 400 1.5-v lvttl/cmos 500 500 450 500 500 450 500 500 400 lvcmos 500 500 450 500 500 450 500 500 400 sstl-2 class i 500 500 500 500 500 500 500 500 500 sstl-2 class ii 500 500 500 500 500 500 500 500 500 sstl-18 class i 500 500 500 500 500 500 500 500 500 sstl-18 class ii 500 500 500 500 500 500 500 500 500 1.5-v hstl class i 500 500 500 500 500 500 500 500 500 1.5-v hstl class ii 500 500 500 500 500 500 500 500 500 1.8-v hstl class i 500 500 500 500 500 500 500 500 500
5?68 altera corporation stratix ii device handbook, volume 1 april 2011 timing model 1.8-v hstl class ii 500 500 500 500 500 500 500 500 500 pci (1) 500 500 450 - - - 500 500 400 pci-x (1) 500 500 450 - - - 500 500 400 1.2-v hstl (2) 280 - - - - - 280 - - differential sstl-2 class i (1) , (3) 500 500 500 - - - 500 500 500 differential sstl-2 class ii (1) , (3) 500 500 500 - - - 500 500 500 differential sstl-18 class i (1) , (3) 500 500 500 - - - 500 500 500 differential sstl-18 class ii (1) , (3) 500 500 500 - - - 500 500 500 1.8-v differential hstl class i (1) , (3) 500 500 500 - - - 500 500 500 1.8-v differential hstl class ii (1) , (3) 500 500 500 - - - 500 500 500 1.5-v differential hstl class i (1) , (3) 500 500 500 - - - 500 500 500 1.5-v differential hstl class ii (1) , (3) 500 500 500 - - - 500 500 500 hypertransport technology (4) - - - 520 520 420 717 717 640 lvpecl (1) - - - - - - 450 450 400 lvds (5) - - - 520 520 420 717 717 640 lvds (6) - - - - - - 450 450 400 notes to table 5?77 : (1) row clock inputs don?t support pci, pci-x, lv pecl, and differential hstl and sstl standards. (2) 1.2-v hstl is only su pported on column i/o pins. (3) differential hstl and sstl standards are on ly supported on column clock and dqs inputs. (4) hypertransport technology is only supported on row i/o and row dedicated clock input pins. (5) these numbers apply to i/o pins and dedicate d clock pins in the left and right i/o banks. (6) these numbers apply to dedicated cloc k pins in the top and bottom i/o banks. table 5?77. maximum input toggle rate on stratix ii devices (part 2 of 2) input i/o standard column i/o pins (mhz ) row i/o pins (mhz) dedicated clock inputs (mhz) -3 -4 -5 -3 -4 -5 -3 -4 -5
altera corporation 5?69 april 2011 stratix ii device handbook, volume 1 dc & switching characteristics table 5?78. maximum output toggle rate on stratix ii devices (part 1 of 5) note (1) i/o standard drive strength column i/o pins (mhz) row i/o pins (mhz) clock outputs (mhz) -3 -4 -5 -3 -4 -5 -3 -4 -5 3.3-v lvttl 4 ma 270 225 210 270 225 210 270 225 210 8 ma 435 355 325 435 355 325 435 355 325 12 ma 580 475 420 580 475 420 580 475 420 16 ma 720 594 520 - - - 720 594 520 20 ma 875 700 610 - - - 875 700 610 24 ma 1,030 794 670 - - - 1,030 794 670 3.3-v lvcmos 4 ma 290 250 230 290 250 230 290 250 230 8 ma 565 480 440 565 480 440 565 480 440 12 ma 790 710 670 - - - 790 710 670 16 ma 1,020 925 875 - - - 1,020 925 875 20 ma 1,066 985 935 - - - 1,066 985 935 24 ma 1,100 1,040 1,000 - - - 1,100 1,040 1,000 2.5-v lvttl/lvcmos 4 ma 230 194 180 230 194 180 230 194 180 8 ma 430 380 380 430 380 380 430 380 380 12 ma 630 575 550 630 575 550 630 575 550 16 ma 930 845 820 - - - 930 845 820 1.8-v lvttl/lvcmos 2 ma 120 109 104 120 109 104 120 109 104 4 ma 285 250 230 285 250 230 285 250 230 6 ma 450 390 360 450 390 360 450 390 360 8 ma 660 570 520 660 570 520 660 570 520 10 ma 905 805 755 - - - 905 805 755 12 ma 1,131 1,040 990 - - - 1,131 1,040 990 1.5-v lvttl/lvcmos 2 ma 244 200 180 244 200 180 244 200 180 4 ma 470 370 325 470 370 325 470 370 325 6 ma 550 430 375 - - - 550 430 375 8 ma 625 495 420 - - - 625 495 420 sstl-2 class i 8 ma 400 300 300 - - - 400 300 300 12 ma 400 400 350 400 350 350 400 400 350 sstl-2 class ii 16 ma 350 350 300 350 350 300 350 350 300 20 ma 400 350 350 - - - 400 350 350 24 ma 400 400 350 - - - 400 400 350
5?70 altera corporation stratix ii device handbook, volume 1 april 2011 timing model sstl-18 class i 4 ma 200 150 150 200 150 150 200 150 150 6 ma 350 250 200 350 250 200 350 250 200 8 ma 450 300 300 450 300 300 450 300 300 10 ma 500 400 400 500 400 400 500 400 400 12 ma 700 550 400 - - - 650 550 400 sstl-18 class ii 8 ma 200 200 150 - - - 200 200 150 16 ma 400 350 350 - - - 400 350 350 18 ma 450 400 400 - - - 450 400 400 20 ma 550 500 450 - - - 550 500 450 1.8-v hstl class i 4 ma 300 300 300 300 300 300 300 300 300 6 ma 500 450 450 500 450 450 500 450 450 8 ma 650 600 600 650 600 600 650 600 600 10 ma 700 650 600 700 650 600 700 650 600 12 ma 700 700 650 700 700 650 700 700 650 1.8-v hstl class ii 16 ma 500 500 450 - - - 500 500 450 18 ma 550 500 500 - - - 550 500 500 20 ma 650 550 550 - - - 550 550 550 1.5-v hstl class i 4 ma 350 300 300 350 300 300 350 300 300 6 ma 500 500 450 500 500 450 500 500 450 8 ma 700 650 600 700 650 600 700 650 600 10 ma 700 700 650 - - - 700 700 650 12 ma 700 700 700 - - - 700 700 700 1.5-v hstl class ii 16 ma 600 600 550 - - - 600 600 550 18 ma 650 600 600 - - - 650 600 600 20 ma 700 650 600 - - - 700 650 600 differential sstl-2 class i (3) 8 ma 400 300 300 400 300 300 400 300 300 12 ma 400 400 350 400 400 350 400 400 350 differential sstl-2 class ii (3) 16 ma 350 350 300 350 350 300 350 350 300 20 ma 400 350 350 350 350 297 400 350 350 24 ma 400 400 350 - - - 400 400 350 table 5?78. maximum output toggle rate on stratix ii devices (part 2 of 5) note (1) i/o standard drive strength column i/o pins (mhz) row i/o pins (mhz) clock outputs (mhz) -3 -4 -5 -3 -4 -5 -3 -4 -5
altera corporation 5?71 april 2011 stratix ii device handbook, volume 1 dc & switching characteristics differential sstl-18 class i (3) 4 ma 200 150 150 200 150 150 200 150 150 6 ma 350 250 200 350 250 200 350 250 200 8 ma 450 300 300 450 300 300 450 300 300 10 ma 500 400 400 500 400 400 500 400 400 12 ma 700 550 400 350 350 297 650 550 400 differential sstl-18 class ii (3) 8 ma 200 200 150 - - - 200 200 150 16 ma 400 350 350 - - - 400 350 350 18 ma 450 400 400 - - - 450 400 400 20 ma 550 500 450 - - - 550 500 450 1.8-v differential hstl class i (3) 4 ma 300 300 300 - - - 300 300 300 6 ma 500 450 450 - - - 500 450 450 8 ma 650 600 600 - - - 650 600 600 10 ma 700 650 600 - - - 700 650 600 12 ma 700 700 650 - - - 700 700 650 1.8-v differential hstl class ii (3) 16 ma 500 500 450 - - - 500 500 450 18 ma 550 500 500 - - - 550 500 500 20 ma 650 550 550 - - - 550 550 550 1.5-v differential hstl class i (3) 4 ma 350 300 300 - - - 350 300 300 6 ma 500 500 450 - - - 500 500 450 8 ma 700 650 600 - - - 700 650 600 10 ma 700 700 650 - - - 700 700 650 12 ma 700 700 700 - - - 700 700 700 1.5-v differential hstl class ii (3) 16 ma 600 600 550 - - - 600 600 550 18 ma 650 600 600 - - - 650 600 600 20 ma 700 650 600 - - - 700 650 600 3.3-v pci 1,000 790 670 - - - 1,000 790 670 3.3-v pci-x 1,000 790 670 - - - 1,000 790 670 lvds (6) - - - 500 500 500 450 400 300 hypertransport technology (4) , (6) 500 500 500 - - - lvpecl (5) - - - - - - 450 400 300 3.3-v lvttl oct 50 400 400 350 400 400 350 400 400 350 2.5-v lvttl oct 50 350 350 300 350 350 300 350 350 300 table 5?78. maximum output toggle rate on stratix ii devices (part 3 of 5) note (1) i/o standard drive strength column i/o pins (mhz) row i/o pins (mhz) clock outputs (mhz) -3 -4 -5 -3 -4 -5 -3 -4 -5
5?72 altera corporation stratix ii device handbook, volume 1 april 2011 timing model 1.8-v lvttl oct 50 700 550 450 700 550 450 700 550 450 3.3-v lvcmos oct 50 350 350 300 350 350 300 350 350 300 1.5-v lvcmos oct 50 550 450 400 550 450 400 550 450 400 sstl-2 class i oct 50 600 500 500 600 500 500 600 500 500 sstl-2 class ii oct 25 600 550 500 600 550 500 600 550 500 sstl-18 class i oct 50 560 400 350 590 400 350 450 400 350 sstl-18 class ii oct 25 550 500 450 - - - 550 500 450 1.2-v hstl (2) oct 50 280 - - - - - 280 - - 1.5-v hstl class i oct 50 600 550 500 600 550 500 600 550 500 1.8-v hstl class i oct 50 650 600 600 650 600 600 650 600 600 1.8-v hstl class ii oct 25 500 500 450 - - - 500 500 450 differential sstl-2 class i oct 50 600 500 500 600 500 500 600 500 500 differential sstl-2 class ii oct 25 600 550 500 600 550 500 600 550 500 differential sstl-18 class i oct 50 560 400 350 590 400 350 560 400 350 differential sstl-18 class ii oct 25 550 500 450 - - - 550 500 450 1.8-v differential hstl class i oct 50 650 600 600 650 600 600 650 600 600 1.8-v differential hstl class ii oct 25 500 500 450 - - - 500 500 450 1.5-v differential hstl class i oct 50 600 550 500 600 550 500 600 550 500 table 5?78. maximum output toggle rate on stratix ii devices (part 4 of 5) note (1) i/o standard drive strength column i/o pins (mhz) row i/o pins (mhz) clock outputs (mhz) -3 -4 -5 -3 -4 -5 -3 -4 -5
altera corporation 5?73 april 2011 stratix ii device handbook, volume 1 dc & switching characteristics 1.2-v differential hstl oct 50 280 - - - - - 280 - - notes to table 5?78 : (1) the toggle rate applies to 0-pf output load for all i/ o standards except for lvds and hypertransport technology on row i/o pins. for lvds and hypertra nsport technology on row i/o pins, the toggle rates apply to load from 0 to 5pf. (2) 1.2-v hstl is only supported on co lumn i/o pins in i/o banks 4, 7, and 8. (3) differential hstl and sstl is only supported on column clock and dqs outputs. (4) hypertransport technology is only supported on row i/o and row dedicated clock input pins. (5) lvpecl is only supported on column clock pins. (6) refer to tables 5?81 through 5?91 if using serdes block. use the toggle rate values from the clock output column for pll output. table 5?79. maximum output clock toggle rate derating factors (part 1 of 5) i/o standard drive strength maximum output clock toggle rate derating factors (ps/pf) column i/o pins row i/o pi ns dedicated clock outputs -3 -4 -5 -3 -4 -5 -3 -4 -5 3.3-v lvttl 4 ma 478 510 510 478 510 510 466 510 510 8 ma 260 333 333 260 333 333 291 333 333 12 ma 213 247 247 213 247 247 211 247 247 16 ma 136 197 197 - - - 166 197 197 20 ma 138 187 187 - - - 154 187 187 24 ma 134 177 177 - - - 143 177 177 3.3-v lvcmos 4 ma 377 391 391 377 391 391 377 391 391 8 ma 206 212 212 206 212 212 178 212 212 12 ma 141 145 145 - - - 115 145 145 16 ma 108 111 111 - - - 86 111 111 20 ma 83 88 88 - - - 79 88 88 24 ma 65 72 72 - - - 74 72 72 2.5-v lvttl/lvcmos 4 ma 387 427 427 387 427 427 391 427 427 8 ma 163 224 224 163 224 224 170 224 224 12 ma 142 203 203 142 203 203 152 203 203 16 ma 120 182 182 - - - 134 182 182 table 5?78. maximum output toggle rate on stratix ii devices (part 5 of 5) note (1) i/o standard drive strength column i/o pins (mhz) row i/o pins (mhz) clock outputs (mhz) -3 -4 -5 -3 -4 -5 -3 -4 -5
5?74 altera corporation stratix ii device handbook, volume 1 april 2011 timing model 1.8-v lvttl/lvcmos 2 ma 951 1421 1421 951 1421 1421 904 1421 1421 4 ma 405 516 516 405 516 516 393 516 516 6 ma 261 325 325 261 325 325 253 325 325 8 ma 223 274 274 223 274 274 224 274 274 10 ma 194 236 236 - - - 199 236 236 12 ma 174 209 209 - - - 180 209 209 1.5-v lvttl/lvcmos 2 ma 652 963 963 652 963 963 618 963 963 4 ma 333 347 347 333 347 347 270 347 347 6 ma 182 247 247 - - - 198 247 247 8 ma 135 194 194 - - - 155 194 194 sstl-2 class i 8 ma 364 680 680 364 680 680 350 680 680 12 ma 163 207 207 163 207 207 188 207 207 sstl-2 class ii 16 ma 118 147 147 118 147 147 94 147 147 20 ma 99 122 122 - - - 87 122 122 24 ma 91 116 116 - - - 85 116 116 sstl-18 class i 4 ma 458 570 570 458 570 570 505 570 570 6 ma 305 380 380 305 380 380 336 380 380 8 ma 225 282 282 225 282 282 248 282 282 10 ma 167 220 220 167 220 220 190 220 220 12 ma 129 175 175 - - - 148 175 175 sstl-18 class ii 8 ma 173 206 206 - - - 155 206 206 16 ma 150 160 160 - - - 140 160 160 18 ma 120 130 130 - - - 110 130 130 20 ma 109 127 127 - - - 94 127 127 sstl-2 class i 8 ma 364 680 680 364 680 680 350 680 680 12 ma 163 207 207 163 207 207 188 207 207 sstl-2 class ii 16 ma 118 147 147 118 147 147 94 147 147 20 ma 99 122 122 - - - 87 122 122 24 ma 91 116 116 - - - 85 116 116 table 5?79. maximum output clock toggle rate derating factors (part 2 of 5) i/o standard drive strength maximum output clock toggle rate derating factors (ps/pf) column i/o pins row i/o pi ns dedicated clock outputs -3 -4 -5 -3 -4 -5 -3 -4 -5
altera corporation 5?75 april 2011 stratix ii device handbook, volume 1 dc & switching characteristics sstl-18 class i 4 ma 458 570 570 458 570 570 505 570 570 6 ma 305 380 380 305 380 380 336 380 380 8 ma 225 282 282 225 282 282 248 282 282 10 ma 167 220 220 167 220 220 190 220 220 12 ma 129 175 175 - - - 148 175 175 sstl-18 class ii 8 ma 173 206 206 - - - 155 206 206 16 ma 150 160 160 - - - 140 160 160 18 ma 120 130 130 - - - 110 130 130 20 ma 109 127 127 - - - 94 127 127 1.8-v hstl class i 4 ma 245 282 282 245 282 282 229 282 282 6 ma 164 188 188 164 188 188 153 188 188 8 ma 123 140 140 123 140 140 114 140 140 10 ma 110 124 124 110 124 124 108 124 124 12 ma 97 110 110 97 110 110 104 110 110 1.8-v hstl class ii 16 ma 101 104 104 - - - 99 104 104 18 ma 98 102 102 - - - 93 102 102 20 ma 93 99 99 - - - 88 99 99 1.5-v hstl class i 4 ma 168 196 196 168 196 196 188 196 196 6 ma 112 131 131 112 131 131 125 131 131 8 ma 84 99 99 84 99 99 95 99 99 10 ma 87 98 98 - - - 90 98 98 12 ma 86 98 98 - - - 87 98 98 1.5-v hstl class ii 16 ma 95 101 101 - - - 96 101 101 18 ma 95 100 100 - - - 101 100 100 20 ma 94 101 101 - - - 104 101 101 differential sstl-2 class ii (3) 8 ma 364 680 680 - - - 350 680 680 12 ma 163 207 207 - - - 188 207 207 16 ma 118 147 147 - - - 94 147 147 20 ma 99 122 122 - - - 87 122 122 24 ma 91 116 116 - - - 85 116 116 table 5?79. maximum output clock toggle rate derating factors (part 3 of 5) i/o standard drive strength maximum output clock toggle rate derating factors (ps/pf) column i/o pins row i/o pi ns dedicated clock outputs -3 -4 -5 -3 -4 -5 -3 -4 -5
5?76 altera corporation stratix ii device handbook, volume 1 april 2011 timing model differential sstl-18 class i (3) 4 ma 458 570 570 - - - 505 570 570 6 ma 305 380 380 - - - 336 380 380 8 ma 225 282 282 - - - 248 282 282 10 ma 167 220 220 - - - 190 220 220 12 ma 129 175 175 - - - 148 175 175 differential sstl-18 class ii (3) 8 ma 173 206 206 - - - 155 206 206 16 ma 150 160 160 - - - 140 160 160 18 ma 120 130 130 - - - 110 130 130 20 ma 109 127 127 - - - 94 127 127 1.8-v differential hstl class i (3) 4 ma 245 282 282 - - - 229 282 282 6 ma 164 188 188 - - - 153 188 188 8 ma 123 140 140 - - - 114 140 140 10 ma 110 124 124 - - - 108 124 124 12 ma 97 110 110 - - - 104 110 110 1.8-v differential hstl class ii (3) 16 ma 101 104 104 - - - 99 104 104 18 ma 98 102 102 - - - 93 102 102 20 ma 93 99 99 - - - 88 99 99 1.5-v differential hstl class i (3) 4 ma 168 196 196 - - - 188 196 196 6 ma 112 131 131 - - - 125 131 131 8 ma 84 99 99 - - - 95 99 99 10 ma 87 98 98 - - - 90 98 98 12 ma 86 98 98 - - - 87 98 98 1.5-v differential hstl class ii (3) 16 ma 95 101 101 - - - 96 101 101 18 ma 95 100 100 - - - 101 100 100 20 ma 94 101 101 - - - 104 101 101 3.3-v pci 134 177 177 - - - 143 177 177 3.3-v pci-x 134 177 177 - - - 143 177 177 lvds - - - 155 (1) 155 (1) 155 (1) 134 134 134 hypertransport technology - - - 155 (1) 155 (1) 155 (1) -- - lvpecl (4) - - - - - - 134 134 134 table 5?79. maximum output clock toggle rate derating factors (part 4 of 5) i/o standard drive strength maximum output clock toggle rate derating factors (ps/pf) column i/o pins row i/o pi ns dedicated clock outputs -3 -4 -5 -3 -4 -5 -3 -4 -5
altera corporation 5?77 april 2011 stratix ii device handbook, volume 1 dc & switching characteristics duty cycle distortion duty cycle distortion (dcd) describe s how much the falling edge of a clock is off from its idea l position. the ideal position is when both the clock high time (clkh) and the clock low time (clkl) equal half of the clock period (t), as shown in figure 5?7 . dcd is the deviation of the non-ideal falling edge from the ideal falling edge, such as d1 for the falling edge a and d2 for the falling edge b ( figure 5?7 ). the maximum dcd for a clock is the larger value of d1 and d2. 3.3-v lvttl oct 50 133 152 152 133 152 152 147 152 152 2.5-v lvttl oct 50 207 274 274 207 274 274 235 274 274 1.8-v lvttl oct 50 151 165 165 151 165 165 153 165 165 3.3-v lvcmos oct 50 300 316 316 300 316 316 263 316 316 1.5-v lvcmos oct 50 157 171 171 157 171 171 174 171 171 sstl-2 class i oct 50 121 134 134 121 134 134 77 134 134 sstl-2 class ii oct 25 56 101 101 56 101 101 58 101 101 sstl-18 class i oct 50 100 123 123 100 123 123 106 123 123 sstl-18 class ii oct 25 61 110 110 - - - 59 110 110 1.2-v hstl (2) oct 50 95 - - - - - - - 95 notes to table 5?79 : (1) for lvds and hypertransport technology output on row i/o pins, the toggle rate derating factors apply to loads larger than 5 pf. in the derating calculation, subtract 5 pf from the intended load value in pf for the correct result. for a load less than or equal to 5 pf, refer to table 5?78 for output toggle rates. (2) 1.2-v hstl is only supported on co lumn i/o pins in i/o banks 4,7, and 8. (3) differential hstl and sstl is only supported on column clock and dqs outputs. (4) lvpecl is only supported on column clock outputs. table 5?79. maximum output clock toggle rate derating factors (part 5 of 5) i/o standard drive strength maximum output clock toggle rate derating factors (ps/pf) column i/o pins row i/o pi ns dedicated clock outputs -3 -4 -5 -3 -4 -5 -3 -4 -5
5?78 altera corporation stratix ii device handbook, volume 1 april 2011 duty cycle distortion figure 5?7. duty cycle distortion dcd expressed in absolution deriva tion, for example, d1 or d2 in figure 5?7 , is clock-period independent. dcd can also be expressed as a percentage, and the percentage number is clock-period dependent. dcd as a percentage is defined as (t/2 ? d1) / t (the low percentage boundary) (t/2 + d2) / t (the high percentage boundary) dcd measurement techniques dcd is measured at an fpga output pin driven by registers inside the corresponding i/o element (ioe) block. when the ou tput is a single data rate signal (non-ddio), on ly one edge of the regist er input clock (positive or negative) triggers output transitions ( figure 5?8 ). therefore, any dcd present on the input clock signal or caused by the clock input buffer or different input i/o standard does no t transfer to the output signal. figure 5?8. dcd measurement technique for non-ddio (single-da ta rate) outputs clkh = t/2 clkl = t/2 d1 d2 falling edge a ideal falling edge clock period (t) falling edge b dq inst prn clrn inst1 dff input vcc clk not output output ioe
altera corporation 5?79 april 2011 stratix ii device handbook, volume 1 dc & switching characteristics however, when the output is a doub le data rate input/output (ddio) signal, both edges of the input clock signal (posit ive and negative) trigger output transitions ( figure 5?9 ). therefore, any dist ortion on the input clock and the input clock buff er affect the output dcd. figure 5?9. dcd measurement technique fo r ddio (double-data rate) outputs when an fpga pll generates the inte rnal clock, the pll output clocks the ioe block. as the pll only monitors the positive edge of the reference clock input and internally re-creates the output cloc k signal, any dcd present on the reference clock is filt ered out. therefore, the dcd for a ddio output with pll in the clock path is better than the dcd for a ddio output without pll in the clock path. tables 5?80 through 5?87 give the maximum dcd in absolution derivation for different i/o standards on stratix ii devices. examples are also provided that show how to calculate dcd as a percentage. dq inst2 prn clrn inst8 dff input vcc clk not output output ioe dq inst3 prn clrn dff v cc gnd table 5?80. maximum dcd for non-ddio output on row i/o pins (part 1 of 2) note (1) row i/o output standard maximum dcd for non-ddio output -3 devices -4 & -5 devices unit 3.3-v lvtttl 245 275 ps 3.3-v lvcmos 125 155 ps 2.5 v 105 135 ps
5?80 altera corporation stratix ii device handbook, volume 1 april 2011 duty cycle distortion here is an example for calculatin g the dcd as a percentage for a non-ddio output on a row i/o on a -3 device: if the non-ddio output i/o standard is sstl-2 class ii, the maximum dcd is 95 ps (see table 5?80 ). if the clock frequency is 267 mhz, the clock period t is: t = 1/ f = 1 / 267 mhz = 3.745 ns = 3745 ps to calculate the dcd as a percentage: (t/2 ? dcd) / t = (3745ps/2 ? 95ps) / 3745ps = 47.5% (for low boundary) (t/2 + dcd) / t = (3745ps/2 + 95ps) / 3745ps = 52.5% (for high boundary) 1.8 v 180 180 ps 1.5-v lvcmos 165 195 ps sstl-2 class i 115 145 ps sstl-2 class ii 95 125 ps sstl-18 class i 55 85 ps 1.8-v hstl class i 80 100 ps 1.5-v hstl class i 85 115 ps lvds/ hypertransport technology 55 80 ps note to table 5?80 : (1) the dcd specification is based on a no logic array noise condition. table 5?80. maximum dcd for non-ddio output on row i/o pins (part 2 of 2) note (1) row i/o output standard maximum dcd for non-ddio output -3 devices -4 & -5 devices unit
altera corporation 5?81 april 2011 stratix ii device handbook, volume 1 dc & switching characteristics therefore, the dcd percentage for the 267 mhz sstl-2 class ii non-ddio row output clock on a ?3 device ranges from 47.5% to 52.5%. table 5?81. maximum dcd for non- ddio output on column i/o pins note (1) column i/o output standard i/o standard maximum dcd for non-ddio output unit -3 devices -4 & -5 devices 3.3-v lvttl 190 220 ps 3.3-v lvcmos 140 175 ps 2.5 v 125 155 ps 1.8 v 80 110 ps 1.5-v lvcmos 185 215 ps sstl-2 class i 105 135 ps sstl-2 class ii 100 130 ps sstl-18 class i 90 115 ps sstl-18 class ii 70 100 ps 1.8-v hstl class i 80 110 ps 1.8-v hstl class ii 80 110 ps 1.5-v hstl class i 85 115 ps 1.5-v hstl class ii 50 80 ps 1.2-v hstl (2) 170 - ps lvpecl 55 80 ps notes to ta b l e 5 ? 8 1 : (1) the dcd specification is based on a no logic array noise condition. (2) 1.2-v hstl is only supported in -3 devices.
5?82 altera corporation stratix ii device handbook, volume 1 april 2011 duty cycle distortion here is an example for calculating the dcd in percentage for a ddio output on a row i/o on a -3 device: if the input i/o standard is sstl-2 and the ddio output i/o standard is sstl-2 class ii, the maximum dcd is 60 ps (see table 5?82 ). if the clock frequency is 267 mhz, the clock period t is: t = 1/ f = 1 / 267 mhz = 3.745 ns = 3745 ps calculate the dcd as a percentage: (t/2 ? dcd) / t = (3745ps/2 ? 60ps) / 3745ps = 48.4% (for low boundary) (t/2 + dcd) / t = (3745 ps/2 + 60 ps) / 3745ps = 51.6% (for high boundary) table 5?82. maximum dcd for ddio output on row i/ o pins without pll in the clock path for -3 devices notes (1) , (2) row ddio output i/o standard maximum dcd based on i/o standard of input feeding the ddio clock port (no pll in clock path) unit ttl/cmos sstl-2 sstl/hstl lvds/ hypertransport technology 3.3 & 2.5 v 1.8 & 1.5 v 2.5 v 1.8 & 1.5 v 3.3 v 3.3-v lvttl 260 380 145 145 110 ps 3.3-v lvcmos 210 330 100 100 65 ps 2.5 v 195 315 85 85 75 ps 1.8 v 150 265 85 85 120 ps 1.5-v lvcmos 255 370 140 140 105 ps sstl-2 class i 175 295 65 65 70 ps sstl-2 class ii 170 290 60 60 75 ps sstl-18 class i 155 275 55 50 90 ps 1.8-v hstl class i 150 270 60 60 95 ps 1.5-v hstl class i 150 270 55 55 90 ps lvds/ hypertransport technology 180 180 180 180 180 ps notes to table 5?82 : (1) the information in table 5?82 assumes the input clock has zero dcd. (2) the dcd specification is based on a no logic array noise condition.
altera corporation 5?83 april 2011 stratix ii device handbook, volume 1 dc & switching characteristics therefore, the dcd percentage for the 267 mhz sstl-2 class ii ddio row output clock on a ?3 devi ce ranges from 48.4% to 51.6%. table 5?83. maximum dcd for ddio output on row i/o pi ns without pll in the clock path for -4 & -5 devices notes (1) , (2) row ddio output i/o standard maximum dcd based on i/o standard of input feeding th e ddio clock port (no pll in the clock path) unit ttl/cmos sstl-2 sstl/hstl lvds/ hypertransport technology 3.3/2.5 v 1.8/1.5 v 2.5 v 1.8/1.5 v 3.3 v 3.3-v lvttl 440 495 170 160 105 ps 3.3-v lvcmos 390 450 120 110 75 ps 2.5 v 375 430 105 95 90 ps 1.8 v 325 385 90 100 135 ps 1.5-v lvcmos 430 490 160 155 100 ps sstl-2 class i 355 410 85 75 85 ps sstl-2 class ii 350 405 80 70 90 ps sstl-18 class i 335 390 65 65 105 ps 1.8-v hstl class i 330 385 60 70 110 ps 1.5-v hstl class i 330 390 60 70 105 ps lvds/ hypertransport technology 180 180 180 180 180 ps notes to table 5?83 : (1) table 5?83 assumes the input clock has zero dcd. (2) the dcd specification is based on a no logic array noise condition. table 5?84. maximum dcd for ddio output on column i/o pins without pll in the clock path for -3 devices (part 1 of 2) notes (1) , (2) ddio column output i/o standard maximum dcd based on i/o standard of input feeding the ddio clock port (no pll in the clock path) unit ttl/cmos sstl-2 sstl/hstl 1.2-v hstl 3.3/2.5 v 1.8/1.5 v 2.5 v 1.8/1.5 v 1.2 v 3.3-v lvttl 260 380 145 145 145 ps 3.3-v lvcmos 210 330 100 100 100 ps 2.5 v 195 315 85 85 85 ps
5?84 altera corporation stratix ii device handbook, volume 1 april 2011 duty cycle distortion 1.8 v 150 265 85 85 85 ps 1.5-v lvcmos 255 370 140 140 140 ps sstl-2 class i 175 295 65 65 65 ps sstl-2 class ii 170 290 60 60 60 ps sstl-18 class i 155 275 55 50 50 ps sstl-18 class ii 140 260 70 70 70 ps 1.8-v hstl class i 150 270 60 60 60 ps 1.8-v hstl class ii 150 270 60 60 60 ps 1.5-v hstl class i 150 270 55 55 55 ps 1.5-v hstl class ii 125 240 85 85 85 ps 1.2-v hstl 240 360 155 155 155 ps lvpecl 180 180 180 180 180 ps notes to table 5?84 : (1) table 5?84 assumes the input clock has zero dcd. (2) the dcd specification is based on a no logic array noise condition. table 5?85. maximum dcd for ddio output on column i/o pins without pll in the clock path for -4 & -5 devices (part 1 of 2) notes (1) , (2) ddio column output i/o standard maximum dcd based on i/o standar d of input feeding the ddio clock port (no pll in the clock path) unit ttl/cmos sstl-2 sstl/hstl 3.3/2.5 v 1.8/1.5 v 2.5 v 1.8/1.5 v 3.3-v lvttl 440 495 170 160 ps 3.3-v lvcmos 390 450 120 110 ps 2.5 v 375 430 105 95 ps 1.8 v 325 385 90 100 ps 1.5-v lvcmos 430 490 160 155 ps sstl-2 class i 355 410 85 75 ps sstl-2 class ii 350 405 80 70 ps table 5?84. maximum dcd for ddio output on column i/o pins without pll in the clock path for -3 devices (part 2 of 2) notes (1) , (2) ddio column output i/o standard maximum dcd based on i/o standard of input feeding the ddio clock port (no pll in the clock path) unit ttl/cmos sstl-2 sstl/hstl 1.2-v hstl 3.3/2.5 v 1.8/1.5 v 2.5 v 1.8/1.5 v 1.2 v
altera corporation 5?85 april 2011 stratix ii device handbook, volume 1 dc & switching characteristics sstl-18 class i 335 390 65 65 ps sstl-18 class ii 320 375 70 80 ps 1.8-v hstl class i 330 385 60 70 ps 1.8-v hstl class ii 330 385 60 70 ps 1.5-v hstl class i 330 390 60 70 ps 1.5-v hstl class ii 330 360 90 100 ps 1.2-v hstl 420 470 155 165 ps lvpecl 180 180 180 180 ps notes to table 5?85 : (1) table 5?85 assumes the input clock has zero dcd. (2) the dcd specification is based on a no logic array noise condition. table 5?85. maximum dcd for ddio output on column i/o pins without pll in the clock path for -4 & -5 devices (part 2 of 2) notes (1) , (2) ddio column output i/o standard maximum dcd based on i/o standar d of input feeding the ddio clock port (no pll in the clock path) unit ttl/cmos sstl-2 sstl/hstl 3.3/2.5 v 1.8/1.5 v 2.5 v 1.8/1.5 v table 5?86. maximum dcd for ddio output on row i/o pins with pll in the clock path (part 1 of 2) note (1) row ddio output i/o standard maximum dcd (pll output clock feeding ddio clock port) unit -3 device -4 & -5 device 3.3-v lvttl 110 105 ps 3.3-v lvcmos 65 75 ps 2.5v 75 90 ps 1.8v 85 100 ps 1.5-v lvcmos 105 100 ps sstl-2 class i 65 75 ps sstl-2 class ii 60 70 ps sstl-18 class i 50 65 ps 1.8-v hstl class i 50 70 ps 1.5-v hstl class i 55 70 ps
5?86 altera corporation stratix ii device handbook, volume 1 april 2011 duty cycle distortion lvds/ hypertransport technology 180 180 ps note to table 5?86 : (1) the dcd specification is based on a no logic array noise condition. table 5?87. maximum dcd for ddio output on column i/o with pll in the clock path note (1) column ddio output i/o standard maximum dcd (pll output clock feeding ddio clock port) unit -3 device -4 & -5 device 3.3-v lvttl 145 160 ps 3.3-v lvcmos 100 110 ps 2.5v 85 95 ps 1.8v 85 100 ps 1.5-v lvcmos 140 155 ps sstl-2 class i 65 75 ps sstl-2 class ii 60 70 ps sstl-18 class i 50 65 ps sstl-18 class ii 70 80 ps 1.8-v hstl class i 60 70 ps 1.8-v hstl class ii 60 70 ps 1.5-v hstl class i 55 70 ps 1.5-v hstl class ii 85 100 ps 1.2-v hstl 155 - ps lvpecl 180 180 ps notes to ta b l e 5 ? 8 7 : (1) the dcd specification is based on a no logic array noise condition. (2) 1.2-v hstl is only supported in -3 devices. table 5?86. maximum dcd for ddio output on row i/o pins with pll in the clock path (part 2 of 2) note (1) row ddio output i/o standard maximum dcd (pll output clock feeding ddio clock port) unit -3 device -4 & -5 device
altera corporation 5?87 april 2011 stratix ii device handbook, volume 1 dc & switching characteristics high-speed i/o specifications table 5?88 provides high-speed timing specifications definitions. table 5?89 shows the high-speed i/o timing specifications for -3 speed grade stratix ii devices. table 5?88. high-speed timing s pecifications & definitions high-speed timing spec ifications definitions t c high-speed receiver/transmitter input and output clock period. f hsclk high-speed receiver/transmitter input and output clock frequency. j deserialization factor (width of parallel data bus). w pll multiplication factor. t rise low-to-high transmission time. t fall high-to-low transmission time. timing unit interval (tui) the timing budget allowed for skew, propagation delays, and data sampling window. (tui = 1/(receiver input clock frequency multiplication factor) = t c / w ). f hsdr maximum/minimum lvds data transfer rate (f hsdr = 1/tui), non-dpa. f hsdrdpa maximum/minimum lvds data transfer rate (f hsdrdpa = 1/tui), dpa. channel-to-channel skew (tccs) the timing difference between the fastest and slowest output edges, including t co variation and clock skew. the clock is included in the tccs measurement. sampling window (sw) the period of time during which the data must be valid in order to capture it correctly. the setup and hold ti mes determine the ideal strobe position within the sampling window. input jitter peak-to-peak inpu t jitter on high-speed plls. output jitter peak-to-peak out put jitter on high-speed plls. t duty duty cycle on high-speed transmitter output clock. t lock lock time for high-speed transmitter and receiver plls. table 5?89. high-speed i/o s pecifications for -3 speed grade (part 1 of 2) notes (1) , (2) symbol conditions -3 speed grade unit min typ max f hsclk (clock frequency) f hsclk = f hsdr / w w = 2 to 32 (lvds, hypertransport technology) (3) 16 520 mhz w = 1 (serdes bypass, lvds only) 16 500 mhz w = 1 (serdes used, lvds only) 150 717 mhz
5?88 altera corporation stratix ii device handbook, volume 1 april 2011 high-speed i/o specifications f hsdr (data rate) j = 4 to 10 (lvds, hypertransport technology) 150 1,040 mbps j = 2 (lvds, hypertransport technology) (4) 760 mbps j = 1 (lvds only) (4) 500 mbps f hsdrdpa (dpa data rate) j = 4 to 10 (lvds, hypertransport technology) 150 1,040 mbps tccs all differential standards - 200 ps sw all differential standards 330 - ps output jitter 190 ps output t rise all differential i/o standards 160 ps output t fall all differential i/o standards 180 ps t duty 45 50 55 % dpa run length 6,400 ui dpa jitter tolerance data channel peak-to-peak jitter 0.44 ui dpa lock time standard training pattern transition density number of repetitions spi-4 0000000000 1111111111 10% 256 parallel rapid i/o 00001111 25% 256 10010000 50% 256 miscellaneous 10101010 100% 256 01010101 256 notes to table 5?89 : (1) when j = 4 to 10, the serdes block is used. (2) when j = 1 or 2, the serdes block is bypassed. (3) the input clock frequency and the w factor must sa tisfy the following fast pll vco specification: 150 input clock frequency w 1,040. (4) the minimum specification is dependen t on the clock source (fast pll, enhanced pll, clock pin, and so on) and the clock routing resource (global, regional, or local) utili zed. the i/o differential buff er and input register do not have a minimum toggle rate. table 5?89. high-speed i/o s pecifications for -3 speed grade (part 2 of 2) notes (1) , (2) symbol conditions -3 speed grade unit min typ max
altera corporation 5?89 april 2011 stratix ii device handbook, volume 1 dc & switching characteristics table 5?90 shows the high-speed i/o timing specifications for -4 speed grade stratix ii devices. table 5?90. high-speed i/o specifi cations for -4 speed grade notes (1) , (2) symbol conditions -4 speed grade unit min typ max f hsclk (clock frequency) f hsclk = f hsdr / w w = 2 to 32 (lvds, hypertransport technology) (3) 16 520 mhz w = 1 (serdes bypass, lvds only) 16 500 mhz w = 1 (serdes used, lvds only) 150 717 mhz f hsdr (data rate) j = 4 to 10 (lvds, hypertransport technology) 150 1,040 mbps j = 2 (lvds, hypertransport technology) (4) 760 mbps j = 1 (lvds only) (4) 500 mbps f hsdrdpa (dpa data rate) j = 4 to 10 (lvds, hypertransport technology) 150 1,040 mbps tccs all differential standards - 200 ps sw all differential standards 330 - ps output jitter 190 ps output t rise all differential i/o standards 160 ps output t fall all differential i/o standards 180 ps t duty 45 50 55 % dpa run length 6,400 ui dpa jitter tolerance data channel peak-to-peak jitter 0.44 ui dpa lock time standard training pattern transition density number of repetitions spi-4 0000000000 1111111111 10% 256 parallel rapid i/o 00001111 25% 256 10010000 50% 256 miscellaneous 10101010 100% 256 01010101 256 notes to table 5?90 : (1) when j = 4 to 10, the serdes block is used. (2) when j = 1 or 2, the serdes block is bypassed. (3) the input clock frequency and the w factor must sa tisfy the following fast pll vco specification: 150 input clock frequency w 1,040. (4) the minimum specification is dependen t on the clock source (fast pll, enhanced pll, clock pin, and so on) and the clock routing resource (global, regional, or local) utili zed. the i/o differential buff er and input register do not have a minimum toggle rate.
5?90 altera corporation stratix ii device handbook, volume 1 april 2011 high-speed i/o specifications table 5?91 shows the high-speed i/o timing specifications for -5 speed grade stratix ii devices. table 5?91. high-speed i/o specifi cations for -5 speed grade notes (1) , (2) symbol conditions -5 speed grade unit min typ max f hsclk (clock frequency) f hsclk = f hsdr / w w = 2 to 32 (lvds, hypertransport technology) (3) 16 420 mhz w = 1 (serdes bypass, lvds only) 16 500 mhz w = 1 (serdes used, lvds only) 150 640 mhz f hsdr (data rate) j = 4 to 10 (lvds, hypertransport technology) 150 840 mbps j = 2 (lvds, hypertransport technology) (4) 700 mbps j = 1 (lvds only) (4) 500 mbps f hsdrdpa (dpa data rate) j = 4 to 10 (lvds, hypertransport technology) 150 840 mbps tccs all differential i/o standards - 200 ps sw all differential i/o standards 440 - ps output jitter 190 ps output t rise all differential i/o standards 290 ps output t fall all differential i/o standards 290 ps t duty 45 50 55 % dpa run length 6,400 ui dpa jitter tolerance data channel peak-to-peak jitter 0.44 ui dpa lock time standard training pattern transition density number of repetitions spi-4 0000000000 1111111111 10% 256 parallel rapid i/o 00001111 25% 256 10010000 50% 256 miscellaneous 10101010 100% 256 01010101 256 notes to table 5?91 : (1) when j = 4 to 10, the serdes block is used. (2) when j = 1 or 2, the serdes block is bypassed. (3) the input clock frequency and the w factor must sa tisfy the following fast pll vco specification: 150 input clock frequency w 1,040. (4) the minimum specification is dependen t on the clock source (fast pll, enhanced pll, clock pin, and so on) and the clock routing resource (global, regional, or local) utili zed. the i/o differential buff er and input register do not have a minimum toggle rate.
altera corporation 5?91 april 2011 stratix ii device handbook, volume 1 dc & switching characteristics pll timing specifications tables 5?92 and 5?93 describe the stratix ii pll specifications when operating in both the commercial junc tion temperature range (0 to 85 c) and the industrial junction temperature range (?40 to 100 c). table 5?92. enhanced pll speci fications (part 1 of 2) name description min typ max unit f in input clock frequency 2 500 mhz f inpfd input frequency to the pfd 2 420 mhz f induty input clock duty cycle 40 60 % f einduty external feedback input clock duty cycle 40 60 % t injitter input or external feedback clock input jitter tolerance in terms of period jitter. bandwidth 0.85 mhz 0.5 ns (p-p) input or external feedback clock input jitter tolerance in terms of period jitter. bandwidth > 0.85 mhz 1.0 ns (p-p) t outjitter dedicated clock output period jitter 250 ps for 100 mhz outclk 25 mui for < 100 mhz outclk ps or mui (p-p) t fcomp external feedback compensation time 10 ns f out output frequency for internal global or regional clock 1.5 (2) 550.0 mhz t outduty duty cycle for external clock output (when set to 50%). 45 50 55 % f scanclk scanclk frequency 100 mhz t configpll time required to reconfigure scan chains for enhanced plls 174/f scanclk ns f out_ext pll external clock output frequency 1.5 (2) 550.0 (1) mhz
5?92 altera corporation stratix ii device handbook, volume 1 april 2011 pll timing specifications t lock time required for the pll to lock from the time it is enabled or the end of device configuration 0.03 1 ms t dlock time required for the pll to lock dynamically after automatic clock switchover between two identical clock frequencies 1ms f switchover frequency range where the clock switchover performs properly 4 500 mhz f clbw pll closed-loop bandwidth 0.13 1.20 16.90 mhz f vco pll vco operating range for ?3 and ?4 speed grade devices 300 1,040 mhz pll vco operating range for ?5 speed grade devices 300 840 mhz f ss spread-spectrum modulation frequency 30 150 khz % spread percent down spread for a given clock frequency 0.4 0.5 0.6 % t pll_pserr accuracy of pll phase shift 15 ps t areset minimum pulse width on areset signal. 10 ns t areset_reconfig minimum pulse width on the areset signal when using pll reconfiguration. reset the pll after scandone goes high. 500 ns notes to table 5?92 : (1) limited by i/o f max . see table 5?78 on page 5?69 for the maximum. cannot exceed f out specification. (2) if the counter cascading feature of the pll is ut ilized, there is no minimum output clock frequency. table 5?92. enhanced pll speci fications (part 2 of 2) name description min typ max unit
altera corporation 5?93 april 2011 stratix ii device handbook, volume 1 dc & switching characteristics table 5?93. fast pll specifications name description min typ max unit f in input clock frequency (for -3 and -4 speed grade devices) 16.08 717 mhz input clock frequency (for -5 speed grade devices) 16.08 640 mhz f inpfd input frequency to the pfd 16.08 500 mhz f induty input clock duty cycle 40 60 % t injitter input clock jitter tolerance in terms of period jitter. bandwidth 2mhz 0.5 ns (p-p) input clock jitter tolerance in terms of period jitter. bandwidth > 2mhz 1.0 ns (p-p) f vco upper vco frequency range for ?3 and ?4 speed grades 300 1,040 mhz upper vco frequency range for ?5 speed grades 300 840 mhz lower vco frequency range for ?3 and ?4 speed grades 150 520 mhz lower vco frequency range for ?5 speed grades 150 420 mhz f out pll output frequency to gclk or rclk 4.6875 550 mhz pll output frequency to lvds or dpa clock 150 1,040 mhz f out_io pll clock output frequency to regular i/o pin 4.6875 (1) mhz f scanclk scanclk frequency 100 mhz t configpll time required to rec onfigure scan chains for fast plls 75/f scanclk ns f clbw pll closed-loop bandwidth 1.16 5.00 28.00 mhz t lock time required for the pll to lock from the time it is enabled or the end of the device configuration 0.03 1.00 ms t pll_pserr accuracy of pll phase shift 15 ps t areset minimum pulse width on areset signal. 10 ns t areset_reconfig minimum pulse width on the areset signal when using pll reconfiguration. reset the pll after scandone goes high. 500 ns note to table 5?93 : (1) limited by i/o f max . see table 5?77 on page 5?67 for the maximum.
5?94 altera corporation stratix ii device handbook, volume 1 april 2011 external memory interface specifications external memory interface specifications tables 5?94 through 5?101 contain stratix ii device specifications for the dedicated circuitry used for interfac ing with external memory devices. table 5?95 lists the maximum delay in th e fast timing model for the stratix ii dqs delay buffer. multiply th e number of delay buffers that you are using in the dqs logic block to ge t the maximum delay achievable in your system. for example, if you im plement a 90 phase shift at 200 mhz, you use three delay buffers in mode 2. the maximum achievable delay from the dqs block is th en 3 .416 ps = 1.248 ns. table 5?94. dll frequency range specifications frequency mode frequency range resolution (degrees) 0 100 to 175 30 1 150 to 230 22.5 2 200 to 310 30 3 240 to 400 (?3 speed grade) 36 240 to 350 (?4 and ?5 speed grades) 36 table 5?95. dqs delay buffer maximum delay in fast timing model frequency mode maximum delay per delay buffer (fast timing model) unit 0 0.833 ns 1, 2, 3 0.416 ns table 5?96. dqs period jitter specifi cations for dll-delayed clock (tdqs_jitter) note (1) number of dqs delay buffer stages (2) commercial industrial unit 1 80 110 ps 2 110 130 ps 3 130 180 ps 4 160 210 ps notes to ta b l e 5 ? 9 6 : (1) peak-to-peak period jitter on the phase shifted dqs clock. (2) delay stages used for requested dqs ph ase shift are reported in your project?s compilation report in the quartus ii software.
altera corporation 5?95 april 2011 stratix ii device handbook, volume 1 dc & switching characteristics table 5?97. dqs phase jitter specifi cations for dll-delayed clock (tdqs phase_jitter) note (1) number of dqs delay buffer stages (2) dqs phase jitter unit 130ps 260ps 390ps 4 120 ps notes to ta b l e 5 ? 9 7 : (1) peak-to-peak phase jitter on the phase sh ifted dds clock (digital jitter is caused by dll tracking). (2) delay stages used for requested dqs ph ase shift are reported in your project?s compilation report in the quartus ii software. table 5?98. dqs phase-shift error specificat ions for dll-delay ed clock (tdqs_pserr) (1) number of dqs delay buffer stages (2) ?3 speed grade ?4 speed grade ?5 speed grade unit 1 253035ps 2 506070ps 3 75 90 105 ps 4 100 120 140 ps notes to table 5?98 : (1) this error specification is the absolute maximum and mi nimum error. for example, sk ew on three delay buffer stages in a c3 speed grade is 75 ps or 37.5 ps . (2) delay stages used for requested dqs phase shift are reported in your project?s compilation report in the quartus ii software. table 5?99. dqs bus clock skew adder specifications (tdqs_clock_skew_adder) mode dqs clock skew adder unit 4 dq per dqs 40 ps 9 dq per dqs 70 ps 18 dq per dqs 75 ps 36 dq per dqs 95 ps note to table 5?99 : (1) this skew specification is the absolute maximum and minimum skew. for example, skew on a 4 dq group is 40 ps or 20 ps.
5?96 altera corporation stratix ii device handbook, volume 1 april 2011 jtag timing specifications jtag timing specifications figure 5?10 shows the timing requirements for the jtag signals. figure 5?10. stratix ii jtag waveforms table 5?100. dqs phase offset delay per stage notes (1) , (2) , (3) speed grade min max unit -3 9 14 ps -4 9 14 ps -5 9 15 ps notes to table 5?100 : (1) the delay settings are linear. (2) the valid settings for phase offset are -64 to +63 for frequency mode 0 and -32 to +31 for frequency modes 1, 2, and 3. (3) the typical value equals the average of the minimum and maximum values. table 5?101. ddio outputs half-period jitter notes (1) , (2) name description max unit t outhalfjitter half-period jitter (pll driving ddio outputs) 200 ps notes to table 5?101 : (1) the worst-case half period is equal to th e ideal half period subtracted by the dcd and half-period jitter values. (2) the half-period jitter was characte rized using a pll driving ddio outputs. tdo tck t jpzx t jpco t jph t jpxz t jcp t jpsu t jcl t jch tdi tms
altera corporation 5?97 april 2011 stratix ii device handbook, volume 1 dc & switching characteristics table 5?102 shows the jtag timing parame ters and values for stratix ii devices. document revision history table 5?103 shows the revision hi story for this chapter. table 5?102. stratix ii jtag timing parameters & values symbol parameter min max unit t jcp tck clock period 30 ns t jch tck clock high time 13 ns t jcl tck clock low time 13 ns t jpsu jtag port setup time 3 ns t jph jtag port hold time 5 ns t jpco jtag port clock to output 11 (1) ns t jpzx jtag port high impedance to valid output 14 (1) ns t jpxz jtag port valid output to high impedance 14 (1) ns note to table 5?102 : (1) a 1 ns adder is required for each v ccio voltage step down from 3.3 v. for example, t jpco = 12 ns if v ccio of the tdo i/o bank = 2.5 v, or 13 ns if it equals 1.8 v. table 5?103. document revision history (part 1 of 3) date and document version changes made summary of changes april 2011, v4.5 updated ta b l e 5 ? 3 . added operating junction temperature for military use. july 2009, v4.4 updated ta b l e 5 ? 9 2 . updated the spread spectrum modulation frequency (f ss ) from (100 khz?500 khz) to (30 khz?150 khz). may 2007, v4.3 updated r conf in table 5?4. updated f in (min) in table 5?92. updated f in and f inpfd in table 5?93. ? moved the document revision history section to the end of the chapter. ?
5?98 altera corporation stratix ii device handbook, volume 1 april 2011 document revision history august, 2006, v4.2 updated table 5?73, table 5?75, table 5?77, table 5?78, table 5?79, table 5?81, table 5?85, and table 5?87. ? april 2006, v4.1 updated table 5?3. updated table 5?11. updated figures 5?8 and 5?9. added parallel on-chip termination information to ?on-chip termination s pecifications? section. updated tables 5?28, 5?30,5?31, and 5?34. updated table 5?78, tables 5?81 through 5?90, and tables 5?92, 5?93, and 5?98. updated ?pll timing specifications? section. updated ?external memory interface specifications? section. added tables 5?95 and 5?101. updated ?jtag timing specifications? section, including figure 5?10 and table 5?102. changed 0.2 mhz to 2 mhz in table 5?93. added new spec for half period jitter (table 5?101). added support for pll clock switchover for industrial temperature range. changed f inpfd (min) spec from 4 mhz to 2 mhz in table 5?92. fixed typo in t outjitter specification in table 5?92. updated v dif ac & dc max specifications in table 5?28. updated minimum values for t jch , t jcl , and t jpsu in table 5?102. update maximum values for t jpco , t jpzx , and t jpxz in table 5?102. december 2005, v4.0 updated ?external memory interface specifications? section. updated timing numbers throughout chapter. ? july 2005, v3.1 updated hypertransport technology information in table 5?13. updated ?timing model? section. updated ?pll timing specifications? section. updated ?external memory interface specifications? section. ? may 2005, v3.0 updated tables throughout chapter. updated ?power consumption? section. added various tables. replaced ?maximum input & output clock rate? section with ?maximum input & output clock toggle rate? section. added ?duty cycle distortion? section. added ?external memory interface specifications? section. ? march 2005, v2.2 updated tables in ?internal timing parameters? section. ? january 2005, v2.1 updated input rise and fall time. ? table 5?103. document revision history (part 2 of 3) date and document version changes made summary of changes
altera corporation 5?99 april 2011 stratix ii device handbook, volume 1 dc & switching characteristics january 2005, v2.0 updated the ?power consumption? section. added the ?high-speed i/o specifications? and ?on-chip termination s pecifications? sections. removed the esd protection specifications section. updated tables 5?3 through 5?13, 5?16 through 5?18, 5?21, 5?35, 5?39, and 5?40. updated tables in ?timing model? section. added tables 5?30 and 5?31. ? october 2004, v1.2 updated table 5?3. updated introduction text in the ?pll timing specifications? section. ? july 2004, v1.1 re-organized chapter. added typical values and c outfb to table 5?32. added undershoot specification to note (4) for tables 5?1 through 5?9. added note (1) to tables 5?5 and 5?6. added v id and v icm to table 5?10. added ?i/o timing meas urement methodology? section. added table 5?72. updated tables 5?1 through 5?2 and tables 5?24 through 5?29. ? february 2004, v1.0 added document to the stratix ii device handbook. ? table 5?103. document revision history (part 3 of 3) date and document version changes made summary of changes
5?100 altera corporation stratix ii device handbook, volume 1 april 2011 document revision history
altera corporation 6?1 april 2011 6. reference & ordering information software stratix ? ii devices are supported by the altera ? quartus ? ii design software, which provides a comprehe nsive environment for system-on-a- programmable-chip (sopc) design. the quartus ii software includes hdl and schematic design entry, comp ilation and logic synthesis, full simulation and advanced ti ming analysis, signaltap ? ii logic analyzer, and device configuration. see the quartus ii handbook for more information on the quartus ii software features. the quartus ii software supports the windows xp/2000/nt/98, sun solaris, linux red hat v7.1 and hp-ux operating systems. it also supports seamless integr ation with industry-leading eda tools through the nativelink ? interface. device pin-outs device pin-outs for stratix ii devices are available on the altera web site at ( www.altera.com ). ordering information figure 6?1 describes the ordering codes for stratix ii devices. for more information on a specific package, refer to the package information for stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii device handbook or the stratix ii gx device handbook . sii51006-2.2
6?2 altera corporation stratix ii device handbook, volume 1 april 2011 document revision history figure 6?1. stratix ii device pa ckaging ordering information note to figure 6?1 : (1) applicable to i4 devices. for more information, refer to the stratix ii military temperature range support technical brief. document revision history table 6?1 shows the revision history for this chapter. device type packa g e type 3, 4, or 5, w ith 3 b eing the fastest nu m b er of pins for a partic u lar fineline bga package es: f: fineline bga h: hy b rid fineline bga ep2s: stratix ii 15 30 60 90 130 1 8 0 optional suffix family si g nature operatin g temperature speed grade pin count engineering sample 7 ep2s 90 c 150 8 fes indicates specific de v ice options or shipment method. c: i: commercial temperat u re (t j = 0 c to 8 5 c) ind u strial temperat u re (t j = -40 c to 100 c) military temperat u re (t j = -55 c to 125 c) (1 ) table 6?1. document revision history date and document version changes made summary of changes april 2011, v2.2 updated figure 6?1 . added operating junction temperature for military use. may 2007, v2.1 moved the document revision history section to the end of the chapter. ? january 2005, v2.0 contact information was removed. ? october 2004, v1.1 updated figure 6?1. ? february 2004, v1.0 added document to the stratix ii device handbook. ?
101 innovation drive san jose, ca 95134 www.altera.com stratix ii device handbook, volume 2 sii5v2-4.5
ii altera corporation copyright ? 2009 altera corporation. all righ ts reserved. altera, the programmable solu tions company, the stylized altera logo, specific device des- ignations, and all other words and logos that are identified as tr ademarks and/or service marks ar e, unless noted otherwise, th e trademarks and service marks of altera corporation in the u.s. and other countries. all other product or service names are the property of the ir respective holders. al- tera products are protected under numerous u.s. and foreign patents and pending app lications, maskwork rights, and copyrights. altera warrants performance of its semiconductor products to current specifications in accordance with altera's standard warranty, but reserves the right to make changes to any products and services at any time with out notice. altera assumes no responsibility or liabil- ity arising out of the application or use of any information, produc t, or service described herein except as expressly agreed to in writing by al tera corporation. altera customers are advised to obtain the latest ver- sion of device specifications before relying on an y published information and before placing orders for products or services .
altera corporation iii contents chapter revision dates ........................................................................... xi about this handbook ............................................................................. xiii how to contact altera .......................................................................................................... ................ xiii typographic conventions ........................................................................................................ ............ xiii section i. clock management revision history ............................................................................................................... ........ section i?1 chapter 1. plls in stratix ii and stratix ii gx devices introduction ................................................................................................................... ......................... 1?1 enhanced plls .................................................................................................................. ..................... 1?5 enhanced pll hardware overview ............................................................................................. 1?5 enhanced pll software overview ................................................................................................ 1 ?9 enhanced pll pins .............................................................................................................. .......... 1?12 fast plls ...................................................................................................................... .............. ........... 1?15 fast pll hardware overview ..................................................................................................... 1?15 fast pll software overview ..................................................................................................... ... 1?16 fast pll pins .................................................................................................................. ................. 1?18 clock feedback modes ........................................................................................................... ............ 1?20 source-synchronous mode ...................................... .................................................................. ... 1?20 no compensation mode ........................................................................................................... .... 1?21 normal mode .................................................................................................................... .............. 1?22 zero delay buffer mode ......................................................................................................... ....... 1?23 external feedback mode ......................................................................................................... ...... 1?24 hardware features .............................................................................................................. ................ 1?25 clock multiplication and division .............................................................................................. 1?26 phase-shift implementation ..................................................................................................... .... 1?27 programmable duty cycle ........................................................................................................ ... 1?29 advanced clear and enable control ........................................................................................... 1?2 9 advanced features .............................................................................................................. ................ 1?32 counter cascading .............................................................................................................. ........... 1?32 clock switchover ............................................................................................................... ............. 1?33 reconfigurable bandwidth ................. ...................................................................................... ......... 1?44 pll reconfiguration ............................................................................................................ ......... ...... 1?51 spread-spectrum clocking ....................................................................................................... ......... 1?51 board layout ................................................................................................................... .......... ........... 1?56 v cca and gnda ...................................................................................................................... ...... 1?56
iv altera corporation contents stratix ii device handbook, volume 2 v ccd ............................................................................................................................ ....................................................................................... 1? 58 external clock output power .................................................................................................... .. 1?58 guidelines ..................................................................................................................... ................... 1?61 pll specifications ............................................................................................................. ........... ........ 1?62 clocking ....................................................................................................................... .............. ........... 1?62 global and hierarchical clocking ............................................................................................... .1?62 clock sources per region ....................................................................................................... ....... 1?64 clock input connections ........................................................................................................ ....... 1?69 clock source control for enhanced plls ...................... ............................................................ 1?73 clock source control fo r fast plls ............................................................................................. 1?73 delay compensation for fast plls ............................................................................................. 1? 75 clock output connections ....................................................................................................... ..... 1?76 clock control block ............................................................................................................ ........... ...... 1?86 clkena signals ................................................................................................................. ................. 1?90 conclusion ..................................................................................................................... ............ ........... 1?91 referenced documents ............................................ ............................................................... ............ 1?91 document revision history ...................................................................................................... ......... 1?92 section ii. memory revision history ............................................................................................................... ...... section ii?1 chapter 2. trimatrix embedded memory blocks in stratix ii and stratix ii gx devices introduction ................................................................................................................... ......................... 2?1 trimatrix memory overview ..................................... ................................................................. ........ 2?1 parity bit support ............................................................................................................. ................ 2?3 byte enable support ............................................................................................................ ............ 2?4 pack mode support .............................................................................................................. ............ 2?7 address clock enable support ................................................................................................... ... 2?8 memory modes ................................................................................................................... ................... 2?9 single-port mode ............................................................................................................... ............. 2?10 simple dual-port mode .......................................................................................................... ....... 2?12 true dual-port mode ............................................................................................................ ......... 2?15 shift-register mode ............................................................................................................ ........... 2?18 rom mode ....................................................................................................................... ............... 2?20 fifo buffers mode .............................................................................................................. ........... 2?20 clock modes .................................................................................................................... ..................... 2?20 independent clock mode ......................................................................................................... ..... 2?21 input/output clock mode ........................................................................................................ ... 2?23 read/write clock mode .......................................................................................................... ..... 2?26 single-clock mode .............................................................................................................. ........... 2?28 designing with trimatrix memory ................................................................................................ .. 2?31 selecting trimatrix memory blocks ............................................................................................ 2? 31 synchronous and pseudo-asynchronous modes ...................................................................... 2?32 power-up conditions and memory init ialization ..................................................................... 2?32 read-during-write operation at the sa me address ......... ........... ............ ........... ........... ......... ...... 2?33
altera corporation v contents contents same-port read-during-write mode .......................................................................................... 2?33 mixed-port read-during-write mode ............................ ............................................................ 2?34 conclusion ..................................................................................................................... ............ ........... 2?35 referenced documents ............................................ ............................................................... ............ 2?36 document revision history ...................................................................................................... ......... 2?36 chapter 3. external memory interfaces in stratix ii and stratix ii gx devices introduction ................................................................................................................... ......................... 3?1 external memory standards ...................................................................................................... .......... 3?4 ddr and ddr2 sdram ............................................................................................................. .... 3?4 rldram ii ...................................................................................................................... ................. 3?8 qdrii sram ..................................................................................................................... .............. 3?10 stratix ii and stratix ii gx ddr memory support overvi ew ................. ........... ........... ......... ...... 3?13 ddr memory interface pins ...................................................................................................... ... 3?14 dqs phase-shift circuitry ...................................................................................................... ...... 3?21 dqs logic block ................................................................................................................ ............. 3?28 ddr registers .................................................................................................................. ............... 3?31 pll ............................................................................................................................ ....................... 3?38 enhancements in stratix ii an d stratix ii gx devices ..... ............ ........... ........... ............ ........... ...... 3?38 conclusion ..................................................................................................................... ............ ........... 3?38 referenced documents ............................................ ............................................................... ............ 3?39 document revision history ...................................................................................................... ......... 3?39 section iii. i/o standards revision history ............................................................................................................... ..... section iii?1 chapter 4. selectable i/o standards in stratix ii and stratix ii gx devices introduction ................................................................................................................... ......................... 4?1 stratix ii and stratix ii gx i/o features ........................................................................................ .... 4?1 stratix ii and stratix ii gx i/o standards support .......................................................................... 4?2 single-ended i/o standards ..................................................................................................... ..... 4?3 differential i/o standards ..................................................................................................... ....... 4?10 stratix ii and stratix ii gx external memo ry interface ............. ........... ........... ........... ............ ........ 4?19 stratix ii and stratix ii gx i/o banks ............................................................................................ ... 4?20 programmable i/o standards ..................................................................................................... .4?22 on-chip termination ............................................................................................................ .............. 4?27 on-chip series termination without calibration ..................................................................... 4?28 on-chip series termination with calibration ........................................................................... 4?30 on-chip parallel termination with calibration ........................................................................ 4?31 design considerations .......................................................................................................... .............. 4?33 i/o termination ................................................................................................................ ............. 4?33 i/o banks restrictions ......................................................................................................... ......... 4?34 i/o placement guidelines ....................................................................................................... ..... 4?36 dc guidelines .................................................................................................................. ............... 4?39 conclusion ..................................................................................................................... ............ ........... 4?42
vi altera corporation contents stratix ii device handbook, volume 2 references ..................................................................................................................... ......... ......... ...... 4?42 referenced documents ............................................ ............................................................... ............ 4?43 document revision history ...................................................................................................... ......... 4?44 chapter 5. high-speed differen tial i/o interfaces with dpa in stratix ii and stratix ii gx devices introduction ................................................................................................................... ......................... 5?1 i/o banks ...................................................................................................................... .......................... 5?1 differential transmitter ...................................... ................................................................. ................. 5?6 differential receiver .......................................................................................................... .................... 5?8 receiver data realignment circuit .............................................................................................. . 5?9 dynamic phase aligner .......................................................................................................... ....... 5?10 synchronizer ................................................................................................................... ................ 5?12 differential i/o termination ................................................................................................... .......... 5?12 fast pll ...................................................................................................................... ........... ......... ...... 5?13 clocking ....................................................................................................................... .............. ........... 5?14 source synchronous timing budget ........................................................................................... 5?16 differential data orientation ........... ....................................................................................... ...... 5?17 differential i/o bit position .................................................................................................. ....... 5?17 receiver skew margin for non-dpa .......................................................................................... 5?19 differential pin placement guidelines .......................................................................................... ... 5?21 high-speed differential i/os and single-ended i/os ............................................................. 5?21 dpa usage guidelines ........................................................................................................... ....... 5?22 non-dpa differential i/o usage guidelines ................... ......................................................... 5?26 board design considerations .................................................................................................... ........ 5?27 conclusion ..................................................................................................................... ............ ........... 5?28 referenced documents ............................................ ............................................................... ............ 5?29 document revision history ...................................................................................................... ......... 5?29 section iv. digital sign al processing (dsp) revision history ............................................................................................................... ..... section iv?1 chapter 6. dsp blocks in stra tix ii and stratix ii gx devices introduction ................................................................................................................... ......................... 6?1 dsp block overview ............................................................................................................. ................ 6?1 architecture ................................................................................................................... ......................... 6?8 multiplier block ............................................................................................................... ................. 6?8 adder/output block ............................................................................................................. ........ 6?16 operational modes .............................................................................................................. ................ 6?21 simple multiplier mode ......................................................................................................... ....... 6?22 multiply accumulate mode ....................................................................................................... .. 6?25 multiply add mode .............................................................................................................. ......... 6?26 software support ............................................................................................................... .................. 6?32 conclusion ..................................................................................................................... ............ ........... 6?32 referenced documents ............................................ ............................................................... ............ 6?33
altera corporation vii contents contents document revision history ...................................................................................................... ......... 6?33 section v. configuration& remote system upgrades revision history ............................................................................................................... ...... section v?1 chapter 7. configuring strati x ii and stratix ii gx devices introduction ................................................................................................................... ......................... 7?1 configuration devices .......................................... ................................................................ ........... 7?1 configuration features ......................................... ................................................................ ................ 7?4 configuration data decompression ........ ...................................................................................... 7 ?5 design security using configuration bitstream encryp tion ..................................................... 7?8 remote system upgrade .......................................................................................................... ....... 7?9 power-on reset circuit ......................................................................................................... .......... 7?9 v ccpd pins .......................................................................................................................... ............. 7?10 vccsel pin ..................................................................................................................... ............... 7?10 output configuration pins ...................................................................................................... ..... 7?13 fast passive parallel configuration ... ......................................................................................... ...... 7?14 fpp configuration using a max ii device as an external host ............................................ 7?15 fpp configuration using a microprocessor ............................................................................... 7?26 fpp configuration using an enhanced configuration de vice ............................................... 7?26 active serial configuration (serial configuration devices) .... ........... ........... ........... ............ ........ 7?34 estimating active serial configuration time ............................................................................ 7?43 programming serial configurat ion devices .............................................................................. 7?43 passive serial configuration ................................... ................................................................ ........... 7?46 ps configuration using a max ii device as an external host ............................................... 7?47 ps configuration using a microprocessor ................................................................................. 7?54 ps configuration using a configuration device ....................................................................... 7?55 ps configuration using a download cable ................... ............................................................ 7?67 passive parallel asynchronous configuration ......... ........... ........... ............ ........... ........... ......... ...... 7?73 jtag configuration ............................................................................................................. ......... ...... 7?84 jam stapl ...................................................................................................................... ................ 7?91 device configuration pins ...................................................................................................... ........... 7?92 conclusion ..................................................................................................................... ............ ......... 7?106 referenced documents ............................................ ............................................................... .......... 7?106 document revision history ...................................................................................................... ....... 7?107 chapter 8. remote system upgrades w ith stratix ii and stratix ii gx devices introduction ................................................................................................................... ......................... 8?1 functional description ......................................................................................................... ................. 8?2 configuration image types and pages ......................................................................................... 8?5 remote system upgrade modes .................................................................................................... ..... 8?8 overview ....................................................................................................................... .................... 8?8 remote update mode ............................................................................................................. ......... 8?9 local update mode .............................................................................................................. .......... 8?12 dedicated remote system upgr ade circuitry ......... ........... ........... ............ ........... ........... ......... ...... 8?14
viii altera corporation contents stratix ii device handbook, volume 2 remote system upgrade registers .............................................................................................. 8? 15 remote system upgrade state machine ..................................................................................... 8?19 user watchdog timer ............................................................................................................ ........ 8?20 interface signals between remote system upgr ade circuitry and fpga logic array ...... 8?21 remote system upgrade pin descriptions ................................................................................. 8?23 quartus ii software support ..................................................................................................... ......... 8?24 altremote_update megafunction .................................................................................................. 8?24 remote system upgrade atom .................................................................................................... 8 ?28 system design guidelines ....................................................................................................... ........... 8?28 remote system upgrade with serial configuration de vices ................................................. 8?29 remote system upgrade with a max ii device or microprocessor and flash device ...... 8?29 remote system upgrade with enhanced configuration devices .......................................... 8?30 conclusion ..................................................................................................................... ............ ........... 8?31 referenced documents ............................................ ............................................................... ............ 8?31 document revision history ...................................................................................................... ......... 8?32 chapter 9. ieee 1149.1 (jtag) boundary- scan testing for stratix ii and stratix ii gx devices introduction ................................................................................................................... ......................... 9?1 ieee std. 1149.1 bst architectu re ........... ........... ............ ........... ........... ........... ......... ......... ......... ........ 9?2 ieee std. 1149.1 boundary-scan register ........ ........... ............ ........... ........... ......... ......... ......... ........ .. 9?4 boundary-scan cells of a stratix ii or stratix ii gx de vice i/o pin ........................................ 9?5 ieee std. 1149.1 bst operation control .... ........... ........... ........... ........... ........... ........... ............ ....... ... 9?7 sample/preload instruction mode ..................................................................................... 9?11 capture phase .................................................................................................................. ............... 9?12 shift and update phases ........................................................................................................ ........ 9?12 extest instruction mode ........................................................................................................ .... 9?13 capture phase .................................................................................................................. ............... 9?14 shift and update phases ........................................................................................................ ........ 9?14 bypass instruction mode ........................................................................................................ .... 9?15 idcode instruction mode ........................................................................................................ ... 9?16 usercode instruction mode ..................................................................................................... 9 ?16 clamp instruction mode ......................................................................................................... ... 9?17 highz instruction mode ......................................................................................................... .... 9?17 i/o voltage support in jtag chain .............................................................................................. .. 9?17 using ieee std. 1149.1 bst circuitry ........................................................................................... .... 9?19 bst for configured devices ..................................................................................................... .......... 9?19 disabling ieee std. 1149.1 bst circuitry ........... ............ ........... ........... ........... ........... ........... ......... .. 9?20 guidelines for ieee std. 1149.1 boundary -scan testing ...... ........... ........... ........... ......... ......... ...... 9?20 boundary-scan description language (b sdl) support ............. ........... ........... ............ ........... ...... 9?21 conclusion ..................................................................................................................... ............ ........... 9?21 references ..................................................................................................................... ......... ......... ...... 9?22 referenced documents ............................................ ............................................................... ............ 9?22 document revision history ...................................................................................................... ......... 9?22
altera corporation ix contents contents section vi. pcb layout guidelines revision history ............................................................................................................... ..... section vi?1 chapter 10. package information for stratix ii & stratix ii gx devices introduction ................................................................................................................... ............ ........... 10?1 thermal resistance ............................................................................................................. ........... ...... 10?2 package outlines ............................................................................................................... .................. 10?5 484-pin fbga - flip chip ....................................................................................................... ....... 10?5 672-pin fbga - flip chip ....................................................................................................... ....... 10?6 780-pin fbga - flip chip ....................................................................................................... ....... 10?9 1,020-pin fbga - flip chip .... ................. ........... ........... ........... ........... ......... ......... ......... ......... .... 10?11 1,152-pin fbga - flip chip .... ................. ........... ........... ........... ........... ......... ......... ......... ......... .... 10?13 1,508-pin fbga - flip chip .... ................. ........... ........... ........... ........... ......... ......... ......... ......... .... 10?15 document revision history ...................................................................................................... ....... 10?17 chapter 11. high-speed board layout guidelines introduction ................................................................................................................... ............ ........... 11?1 pcb material selection ......................................................................................................... ......... ...... 11?1 transmission line layout ....................................................................................................... ........... 11?3 impedance calculation .......................................................................................................... ........ 11?4 propagation delay .............................................................................................................. ............ 11?8 pre-emphasis ................................................................................................................... ............... 11?9 routing schemes for minimizing cr osstalk & maintaining signal inte grity .............. ............. 11?11 signal trace routing ........................................................................................................... ......... 11?13 termination schemes ............................................................................................................ ............ 11?19 simple parallel termination .................................................................................................... ... 11?19 thevenin parallel termination .................................................................................................. . 11?20 active parallel termination .................................................................................................... .... 11?21 series-rc parallel termination ............................... .................................................................. . 11?22 series termination ............................................................................................................. .......... 11?23 differential pair termination .................................................................................................. ... 11?23 simultaneous switching noise ................................................................................................... ..... 11?24 power filtering & distribution ................................................................................................. .. 11?26 electromagnetic interference (emi) ............................................................................................. ... 11?28 additional fpga-specific information .......................................................................................... 1 1?29 configuration .................................................................................................................. .............. 11?29 jtag ........................................................................................................................... ......... ........... 11?30 test point ..................................................................................................................... .................. 11?30 summary ........................................................................................................................ ............ ......... 11?30 references ..................................................................................................................... ......... ............. 11?31 document revision history ...................................................................................................... ....... 11?31
x altera corporation contents stratix ii device handbook, volume 2
altera corporation xi chapter revision dates the chapters in this book, stratix ii device handbook, volume 2 , were revised on the following dates. where chapters or groups of chapters are av ailable separately, part numbers are listed. chapter 1. plls in stratix ii and stratix ii gx devices revised: july 2009 part number: sii52001-4.6 chapter 2. trimatrix embedded memory blocks in stratix ii and stratix ii gx devices revised: january 2008 part number: sii52002-4.5 chapter 3. external memory interfaces in stratix ii and stratix ii gx devices revised: january 2008 part number: sii52003-4.5 chapter 4. selectable i/o standards in stratix ii and stratix ii gx devices revised: january 2008 part number: sii52004-4.6 chapter 5. high-speed differential i/o interfaces with dpa in stra tix ii and stratix ii gx devices revised: january 2008 part number: sii52005-2.2 chapter 6. dsp blocks in stra tix ii and stratix ii gx devices revised: january 2008 part number: sii52006-2.2 chapter 7. configuring stratix ii and stratix ii gx devices revised: january 2008 part number: sii52007-4.5 chapter 8. remote system upgrades with stratix ii and stratix ii gx devices revised: january 2008 part number: sii52008-4.5 chapter 9. ieee 1149.1 (jtag) boundary-scan te sting for stratix ii and stratix ii gx devices revised: january 2008 part number: sii52009-3.3
xii altera corporation chapter revision dates stratix ii device handbook, volume 2 chapter 10. package information for st ratix ii & stratix ii gx devices revised: may 2007 part number: sii52010-4.3 chapter 11. high-speed board layout guidelines revised: may 2007 part number: sii52012-1.4
altera corporation xiii preliminary about this handbook this handbook provides comprehe nsive information about the altera ? stratix ? ii family of devices. how to contact altera for the most up-to-date information about altera products, refer to the following table. typographic conventions this document uses the typogr aphic conventions shown below. contact (1) contact method address technical support website www.altera.com/support technical training website www.altera.com/training email custrain@altera.com product literature website www.altera.com/literature non-technical support (general) (software licensing) email nacomp@altera.com email authorization@altera.com note to table: (1) you can also contact your local altera sales office or sales representative. visual cue meaning bold type with initial capital letters command names, dialog box titles, checkbox options, and dialog box options are shown in bold, initial capital letters. example: save as dialog box. bold type external timing parameters, directory names, project names, disk drive names, filenames, filename extensions, and softw are utility names are shown in bold type. examples: f max , \qdesigns directory, d: drive, chiptrip.gdf file. italic type with initial capital letters document titles are shown in italic ty pe with initial capital letters. example: an 75: high-speed board design. italic type internal timing parameters and variables are shown in italic type. examples: t pia , n + 1. variable names are enclosed in angle br ackets (< >) and shown in italic type. example: , .pof file.
xiv altera corporation preliminary typographic conventions stratix ii device handbook, volume 2 initial capital letters keyboard keys and menu names ar e shown with initial capital letters. examples: delete key, the options menu. ?subheading title? references to sections within a document and titles of on-line help topics are shown in quotation marks. example: ?typographic conventions.? courier type signal and port names are shown in lowercase courier type. examples: data1 , tdi , input. active-low signals are denoted by suffix n , e.g., resetn . anything that must be typed exactly as it appears is shown in courier type. for example: c:\qdesigns\tutorial\chiptrip.gdf . also, sections of an actual file, such as a report file, refere nces to parts of files (e.g., the ahdl keyword subdesign ), as well as logic function names (e.g., tri ) are shown in courier. 1., 2., 3., and a., b., c., etc. numbered steps are used in a list of items when the sequence of the items is important, such as the steps listed in a procedure. ? bullets are used in a list of items when the sequence of the items is not important. v the checkmark indicates a procedur e that consists of one step only. 1 the hand points to information that requires special attention. c the caution indicates required informati on that needs special consideration and understanding and should be read prior to starting or continuing with the procedure or process. w the warning indicates information that should be read prior to starting or continuing the proce dure or processes r the angled arrow indicates you should press the enter key. f the feet direct you to more information on a particular topic. visual cue meaning
altera corporation section i?1 section i. clock management this section provides information on the different types of phase-locked loops (plls). the feature-rich enhanced plls assist designers in managing clocks internally and also ha ve the ability to drive off chip to control system-level clock networks. the fast plls offer general-purpose clock management with multiplication an d phase shifting as well as high- speed outputs to manage the high-speed differential i/o interfaces. this section contains detailed information on the features, the interconnections to the logic array and off chip, and the specifications for both types of plls. this section contains the following chapter: chapter 1, plls in stratix ii and stratix ii gx devices revision history refer to each chapter for its own specific revision history. for information on when each chapter was updated, refer to the chapter revision dates section, which appears in the full handbook.
section i?2 altera corporation clock management stratix ii device handbook, volume 2
altera corporation 1?1 july 2009 1. plls in stratix ii and stratix ii gx devices introduction stratix ? ii and stratix ii gx device phase-locked loops (plls) provide robust clock management and synthe sis for device clock management, external system clock management , and high-speed i/o interfaces. stratix ii devices have up to 12 plls, and stratix ii gx devices have up to 8 plls. stratix ii and stratix ii gx plls are highly versatile and can be used as a zero delay buffer, a jitter attenuator, low skew fan out buffer, or a frequency synthesizer. stratix ii and stratix ii gx devices feature both enhanced plls and fast plls. stratix ii and stratix ii gx de vices have up to four enhanced plls. stratix ii devices have up to eight fast plls and stratix ii gx devices have up to four plls. both enhanced and fast plls are feature rich, supporting advanced capabilities such as clock switchover, reconfigurable phase shift, pll reconfiguration, and reconfigurable bandwidth. plls can be used for general-purpos e clock management, suppo rting multiplication, phase shifting, and programmable du ty cycle. in addition, enhanced plls support external clock feedback mode, spread-spectrum clocking, and counter cascading. fast plls of fer high speed outputs to manage the high-speed differential i/o interfaces. stratix ii and stratix ii gx devices also support a power-down mode where clock networks that are not bein g used can easily be turned off, reducing the overall power consumpt ion of the device. in addition, stratix ii and stratix ii gx plls support dynamic selection of the pll input clock from up to five possible so urces, giving you the flexibility to choose from multiple (up to four) cl ock sources to feed the primary and secondary clock input ports. the altera ? quartus ? ii software enables the plls and their features without requiring any external devices. sii52001-4.6
1?2 altera corporation stratix ii device handbook, volume 2 july 2009 introduction tables 1?1 and 1?2 show the plls available for each stratix ii and stratix ii gx device, respectively. table 1?1. stratix ii devi ce pll availability note (1) device fast plls enhanced plls 1 2 3 4 7 8 9 10 5 6 11 12 ep2s15 vvvv vv ep2s30 vvvv vv ep2s60 vvvvv vv v vvvv ep2s90 (2) vvvvv vv v vvvv ep2s130 (3) vvvvvvvvvvvv ep2s180 vvvvvvvvvvvv notes for ta b l e 1 ? 1 : (1) the ep2s60 device in the 1,020-pin package contains 12 plls. ep2s60 devices in the 484-pin and 672-pin packages contain fast plls 1?4 and enhanced plls 5 and 6. (2) ep2s90 devices in the 1020-pin and 1508-pin packages co ntain 12 plls. ep2s90 devices in the 484-pin and 780-pin packages contain fast plls 1?4 and enhanced plls 5 and 6. (3) ep2s130 devices in the 1020-pin and 1508-pin packages contain 12 plls. the ep2s130 device in the 780-pin package contains fast plls 1?4 and enhanced plls 5 and 6. table 1?2. stratix ii gx de vice pll availability note (1) device fast plls enhanced plls 123 (3) 4 (3) 789 (3) 10 (3) 5 6 11 12 ep2sgx30 (2) vv vv ep2sgx60 (2) vv v v vvvv ep2sgx90 vv v v vvvv ep2sgx130 vv vv vvvv notes for ta b l e 1 ? 2 : (1) the global or regional clocks in a fast pll?s transceive r block can drive the fast pll input. a pin or other pll must drive the global or regional source. th e source cannot be driven by internal ly generated logic before driving the fast pll. (2) ep2sgx30c and ep2sgx60c devices only have two fast p lls (plls 1 and 2), but the connectivity from these two plls to the global and regional clock networ ks remains the same as shown in this table. (3) plls 3, 4, 9, and 10 are not available in stratix ii gx devices. however, these plls are listed in table 1?2 because the stratix ii gx pll numbering scheme is cons istent with stratix and stratix ii devices.
altera corporation 1?3 july 2009 stratix ii device handbook, volume 2 plls in stratix ii and stratix ii gx devices table 1?3 shows the enhanced pll and fast pll features in stratix ii and stratix ii gx devices. figure 1?1 shows a top-level diagram of stratix ii device and pll locations. figure 1?2 shows a top-level diagram of stratix ii device and pll locations. see ?clock control block? on page 1?86 for more detail on pll connections to global and regional clocks networks. table 1?3. stratix ii and stra tix ii gx pll features feature enhanced pll fast pll clock multiplication and division m/(n post-scale counter) (1) m/(n post-scale counter) (2) phase shift down to 125-ps increments (3) down to 125-ps increments (3) clock switchover vv (4) pll reconfiguration vv reconfigurable bandwidth vv spread-spectrum clocking v programmable duty cycle vv number of clock outputs per pll (5) 64 number of dedicated external clock outputs per pll three differential or six single-ended (6) number of feedback clock inputs per pll 1 (7) notes to ta b l e 1 ? 3 : (1) for enhanced plls, m and n range from 1 to 512 with 50% duty cycle. post-scale counters range from 1 to 512 with 50% duty cycle. for non-50% duty-cycle clock outputs, post-scale counters range from 1 to 256. (2) for fast plls, n can range from 1 to 4. the post-scale and m counters range from 1 to 32. for non-50% duty-cycle clock outputs, post-scale counters range from 1 to 16. (3) the smallest phase shift is determined by the voltage controlled osc illator (vco) period divided by eight. the supported phase-shift range is from 125 to 250 ps. st ratix ii and stratix ii gx devices can shift all output frequencies in increments of at least 45 ? . smaller degree increments are possible depending on the frequency and divide parameters. for non-50% duty cycle clock ou tputs post-scale counters range from 1 to 256. (4) stratix ii and stratix ii gx fast plls only support manual clock switchover. (5) the clock outputs can be driven to internal clock networks or to a pin. (6) the pll clock outputs of the fast plls can drive to any i/o pin to be used as an external clock output. for high-speed differential i/o pins, the device uses a da ta channel to generate the transmitter output clock ( txclkout ) . (7) if the design uses external feedback input pins, you will lose one (or two, if f bin is differential) dedicated output clock pin.
1?4 altera corporation stratix ii device handbook, volume 2 july 2009 introduction figure 1?1. stratix ii pll locations fpll7clk fpll10clk fpll9clk clk8-11 fpll8clk clk0-3 7 1 2 8 10 4 3 9 5 12 6 clk4-7 clk12-15 11 rclk0-3 rclk4-7 gclk0-3 gclk8-11 rclk20-23 rclk28-31 rclk24-27 gclk12-15 gclk4-7 rclk8-11 rclk12-15 q1 q4 q2 q3 rclk16-19 fast plls fast plls fast plls fast plls enhanced pll enhanced pll enhanced pll enhanced pll
altera corporation 1?5 july 2009 stratix ii device handbook, volume 2 plls in stratix ii and stratix ii gx devices figure 1?2. stratix ii gx pll locations enhanced plls stratix ii and stratix ii gx devices contain up to four enhanced plls with advanced clock manageme nt features. the main goal of a pll is to synchronize the phase and frequency of an internal and external clock to an input reference clock. there ar e a number of components that comprise a pll to achiev e this phase alignment. enhanced pll hardware overview stratix ii and stratix ii gx plls alig n the rising edge of the reference input clock to a feedback clock using the phase-frequency detector (pfd). the falling edges are determined by the duty-cycle specifications. the pfd produces an up or down signal that determines whether the vco needs to operate at a higher or lower frequency. fpll7clk fpll8clk clk[3..0] 7 1 2 8 5 11 6 12 clk [ 7..4 ] clk[15..12] plls
1?6 altera corporation stratix ii device handbook, volume 2 july 2009 enhanced plls the pfd output is applied to the charge pump and loop filter, which produces a control voltage for setti ng the vco frequency. if the pfd produces an up signal, then the vco frequency increases. a down signal decreases the vco frequency. the pfd outputs these up and down signals to a charge pump. if the charge pump receives an up signal, current is driven into the loop filter. conversely, if it receives a down signal, current is drawn from the loop filter. the loop filter converts these up an d down signals to a voltage that is used to bias the vco. the loop filt er also removes glitches from the charge pump and prevents voltage ov er-shoot, which filters the jitter on the vco. the voltage from the loop filter de termines how fast the vco operates. the vco is implemented as a four-stage differential ring oscillator. a divide counter ( m ) is inserted in the feedback loop to increase the vco frequency above the input reference frequency. vco frequency (f vco ) is equal to ( m ) times the input reference clock (f ref ). the input reference clock (f ref ) to the pfd is equal to the input clock (f in ) divided by the pre- scale counter ( n ). therefore, the feedback clock (f fb ) applied to one input of the pfd is locked to the f ref that is applied to the other input of the pfd. the vco output can feed up to six post-scale counters ( c0 , c1 , c2 , c3 , c4 , and c5 ). these post-scale counters al low a number of harmonically related frequencies to be produced within the pll. figure 1?3 shows a simplified block diagram of the major components of the stratix ii and stratix ii gx enhanced pll. figure 1?4 shows the enhanced pll?s outputs and dedicated clock outputs.
altera corporation 1?7 july 2009 stratix ii device handbook, volume 2 plls in stratix ii and stratix ii gx devices figure 1?3. stratix ii and st ratix ii gx enhanced pll notes to figure 1?3 : (1) each clock source can come from any of the four clock pins located on the same side of the device as the pll. (2) plls 5, 6, 11, and 12 each have six single-ended de dicated clock outputs or three differential dedicated clock outputs. (3) if the design uses external feedback in put pins, you will lose one (or two, if f bin is differential) dedicated output clock pin. every stratix ii and stratix ii gx device has at least two enhanced plls with one single-ended or differential external feedback input per pll. (4) the global or regional clock input can be driven by an output from another pll, a pi n-driven dedicated global or regional clock, or through a clock control block provided th e clock control block is fed by an output from another pll or a pin-driven dedicated global or regional clock. an internally generated global signal cannot drive the pll. charge pump vco c2 c3 c4 c0 8 4 6 4 global clocks c1 lock detect to i/o or general routing inclk[3..0] fbin global or regional clock pfd c5 from adjacent pll m n spread spectrum i/o buffers (2) (1) loop filter & filter post-scale counters clock switchover circuitry phase frequency detector vco phase selection selectable at each pll output port vco phase selection affecting all outputs shaded portions of the pll are reconfigurable regional clocks 8 6
1?8 altera corporation stratix ii device handbook, volume 2 july 2009 enhanced plls external clock outputs enhanced plls 5, 6, 11, and 12 each support up to six single-ended clock outputs (or three differential pairs). see figure 1?4 . figure 1?4. external clock outputs for enhanced plls 5, 6, 11 and 12 notes to figure 1?4 : (1) these clock output pins can be fed by any one of the c[5..0] counters. (2) these clock output pins are used as either external clock outputs or for external feedback. if the design uses external feedback input pins, you will lose one (or two, if f bin is differential) dedicated output clock pin. (3) these external clock enable signals are available only when using the altclkctrl megafunction. any of the six output counters c[5..0] can feed the dedicated external clock outputs, as shown in figure 1?5 . therefore, one counter or frequency can drive all output pins available from a given pll. the dedicated output clock pins ( pll_out ) from each enhanced pll are powered by a separate power pin (e.g., vcc_pll5_out , vcc_pll6_out , etc.), reducing the overal l output jitter by providing improved isolation from switching i/o pins. enhanced pll c0 c1 c2 c4 c5 c3 extclken0 extclken1 pll#_out0p (1) pll#_out0n (1) extclken2 extclken3 pll#_out1p (1) pll#_out1n (1) extclken4 extclken5 pll#_out2p (1), (2) pll#_out2n (1), (2) (3) (3) (3) (3) (3) (3)
altera corporation 1?9 july 2009 stratix ii device handbook, volume 2 plls in stratix ii and stratix ii gx devices figure 1?5. external clock output co nnectivity to pll output counter s for enhanced plls 5, 6, 11 and 12 note (1) note to figure 1?5 : (1) the design can use each external clock output pin as a general-purpose output pin from the logic array. these pins are multiplexed with i/o element (ioe) outputs. each pin of a single-ended output pair can either be in phase or 180 out of phase. the quartus ii software places the not gate in the design into the ioe to implement 180 phase with resp ect to the other pin in the pair. the clock output pi n pairs support the same i/o standards as standard output pins (in the top and bottom banks) as well as lvds, lvpecl, differential hstl, and differential sstl. see table 1?6 , in the ?enhanced pll pins? section on page 1?12 to determine which i/o standards the enhanced pll cloc k pins support. when in single-ended or differential mode, one power pin supports six single-ended or three differential ou tputs. both outputs use the same i/o standard in single-ended mode to maintain performance. you can also use the external clock ou tput pins as user outp ut pins if external enhanced pll clocking is not needed. the enhanced pll can also drive out to any regular i/o pin through the global or regional clock network. enhanced pll software overview stratix ii and stratix ii gx enhanced plls are enabled in the quartus ii software by using the altpll megafunction. figure 1?6 shows the available ports (as they are named in the quartus ii altpll megafunction) of the stratix ii an d stratix ii gx enhanced pll. c0 c1 c3 c4 c5 c6 from internal logic or ioe 6 6 6 to i/o pins (1) multiplexer selection set in configuration file
1?10 altera corporation stratix ii device handbook, volume 2 july 2009 enhanced plls figure 1?6. enhanced pll ports notes to figure 1?6 : (1) enhanced and fast plls share this input pin. (2) these are either single-e nded or differential pins. (3) the primary and secondary clock input can be fed from an y one of four clock pins locate d on the same side of the device as the pll. (4) can drive to the global or regional clock netw orks or the dedicated external clock output pins. (5) these dedicated output clocks are fed by the c[5..0] counters. tables 1?4 and 1?5 describe all the e nhanced pll ports. clkswitch scandata scanclk pllena c[5..0] locked physical pin clkloss areset pfdena signal driven by internal logic signal driven to internal logic internal clock signal scandone pll_out0p scandataout fbin clkbad[1..0] (1) (2), (3) pll_out0n pll_out1p pll_out1n pll_out2p pll_out2n (5) scanwrite scanread (5) (5) (5) (5) (5) activeclock inclk0 inclk1 (4) (2), (3) table 1?4. enhanced pll input signals (part 1 of 2) port description source destination inclk0 primary clock input to the pll. pin or another pll n counter inclk1 secondary clock input to the pll. pin or another pll n counter fbin external feedback input to the pll. pin pfd pllena enable pin for enabling or disabling all or a set of plls. active high. pin general pll control signal clkswitch switch-over signal used to initiate external clock switch-over control. active high. logic array pll switch-over circuit
altera corporation 1?11 july 2009 stratix ii device handbook, volume 2 plls in stratix ii and stratix ii gx devices areset signal used to reset the pll which resynchronizes all the counter outputs. active high. logic array general pll control signal pfdena enables the outputs from the phase frequency detector. active high. logic array pfd scanclk serial clock signal for the real-time pll reconfiguration feature. logic array reconfiguration circuit scandata serial input data stream for the real- time pll reconfiguration feature. logic array reconfiguration circuit scanwrite enables writing the data in the scan chain into the pll. active high. logic array reconfiguration circuit scanread enables scan data to be written into the scan chain. active high. logic array reconfiguration circuit table 1?5. enhanced pll output signals (part 1 of 2) port description source destination c[5..0] pll output counters driving regional, global or external clocks. pll counter internal or external clock pll_out [2..0]p pll_out [2..0]n these are three differential or six single-ended external clock output pins fed from the c[5..0] pll counters, and every output can be driven by any counter. p and n are the positive ( p ) and negative ( n ) pins for differential pins. pll counter pin(s) clkloss signal indicating the switch-over circuit detected a switch-over condition. pll switch-over circuit logic array clkbad[1..0] signals indicating which reference clock is no longer toggling. clkbad1 indicates inclk1 status, clkbad0 indicates inclk0 status. 1= good; 0=bad pll switch-over circuit logic array locked lock or gated lock output from lock detect circuit. active high. pll lock detect logic array activeclock signal to indicate which clock ( 0 = inclk0 or 1 = inclk1 ) is driving the pll. if this signal is low, inclk0 drives the pll, if this signal is high, inclk1 drives the pll pll clock multiplexer logic array table 1?4. enhanced pll input signals (part 2 of 2) port description source destination
1?12 altera corporation stratix ii device handbook, volume 2 july 2009 enhanced plls enhanced pll pins table 1?6 lists the i/o standards support by the enhanced pll clock outputs. scandataout output of the last shift register in the scan chain. pll scan chain logic array scandone signal indicating when the pll has completed reconfiguration. 1 to 0 transition indicates that the pll has been reconfigured. pll scan chain logic array table 1?5. enhanced pll output signals (part 2 of 2) port description source destination table 1?6. i/o standards supported for enhanced pll pins (part 1 of 2) note (1) i/o standard input output inclk fbin extclk lv t t l v v v lv c m o s v v v 2.5 v v v v 1.8 v v v v 1.5 v v v v 3.3-v pci v v v 3.3-v pci-x v v v sstl-2 class i v v v sstl-2 class ii v v v sstl-18 class i v v v sstl-18 class ii v v v 1.8-v hstl class i v v v 1.8-v hstl class ii v v v 1.5-v hstl class i v v v 1.5-v hstl class ii v v v 1.2-v hstl class i v v v 1.2-v hstl class ii v v v
altera corporation 1?13 july 2009 stratix ii device handbook, volume 2 plls in stratix ii and stratix ii gx devices table 1?7 shows the physical pins and th eir purpose for the stratix ii and stratix ii gx enhanced plls. for inclk port connections to pins see ?clock control block? on page 1?86 . differential sstl-2 class i v v v differential sstl-2 class ii v v v differential sstl-18 class i v v v differential sstl-18 class ii v v v 1.8-v differential hstl class i v v v 1.8-v differential hstl class ii v v v 1.5-v differential hstl class i v v v 1.5-v differential hstl class ii v v v lv d s v v v hypertransport technology differential lvpecl vv v note to ta b l e 1 ? 6 : (1) the enhanced pll external clock output bank does not allow a mixture of both single-ended and differential i/o standards. table 1?6. i/o standards supported for enhanced pll pins (part 2 of 2) note (1) i/o standard input output inclk fbin extclk table 1?7. stratix ii and st ratix ii gx enhanced pll pins (part 1 of 3) note (1) pin description clk4p/n single-ended or differential pins that can drive the inclk port for plls 6 or 12. clk5p/n single-ended or differential pins that can drive the inclk port for plls 6 or 12. clk6p/n single-ended or differential pins that can drive the inclk port for plls 6 or 12. clk7p/n single-ended or differential pins that can drive the inclk port for plls 6 or 12. clk12p/n single-ended or differential pins that can drive the inclk port for plls 5 or 11. clk13p/n single-ended or differential pins that can drive the inclk port for plls 5 or 11. clk14p/n single-ended or differential pins that can drive the inclk port for plls 5 or 11. clk15p/n single-ended or differential pins that can drive the inclk port for plls 5 or 11. pll5_fbp/n single-ended or differential pins that can drive the fbin port for pll 5.
1?14 altera corporation stratix ii device handbook, volume 2 july 2009 enhanced plls pll6_fbp/n single-ended or differential pins that can drive the fbin port for pll 6. pll11_fbp/n single-ended or differential pins that can drive the fbin port for pll 11. pll12_fbp/n single-ended or differential pins that can drive the fbin port for pll 12. pll_ena dedicated input pin that drives the pllena port of all or a set of plls. if you do not use this pin, connect it to ground. pll5_out[2..0]p/n single-ended or differential pins driven by c[5..0] ports from pll 5. pll6_out[2..0]p/n single-ended or differential pins driven by c[5..0] ports from pll 6. pll11_out[2..0]p/n single-ended or differential pins driven by c[5..0] ports from pll 11. pll12_out[2..0]p/n single-ended or differential pins driven by c[5..0] ports from pll 12. vcca_pll5 analog power for pll 5. you must connect this pin to 1.2 v, even if the pll is not used. gnda_pll5 analog ground for pll 5. you can connect this pin to the gnd plane on the board. vcca_pll6 analog power for pll 6. you must connect this pin to 1.2 v, even if the pll is not used. gnda_pll6 analog ground for pll 6. you can connect this pin to the gnd plane on the board. vcca_pll11 analog power for pll 11. you must connect this pin to 1.2 v, even if the pll is not used. gnda_pll11 analog ground for pll 11. you can connect this pin to the gnd plane on the board. vcca_pll12 analog power for pll 12. you must connect this pin to 1.2 v, even if the pll is not used. gnda_pll12 analog ground for pll 12. you can connect this pin to the gnd plane on the board. vccd_pll digital power for plls. you must connect this pin to 1.2 v, even if the pll is not used. vcc_pll5_out external clock output v ccio power for pll5_out0p , pll5_out0n , pll5_out1p , pll5_out1n , pll5_out2p , and pll5_out2n outputs from pll 5. vcc_pll6_out external clock output v ccio power for pll6_out0p , pll6_out0n , pll6_out1p , pll6_out1n and pll6_out2p , pll6_out2n outputs from pll 6. vcc_pll11_out external clock output v ccio power for pll11_out0p , pll11_out0n , pll11_out1p , pll11_out1n and pll11_out2p , pll11_out2n outputs from pll 11. table 1?7. stratix ii and st ratix ii gx enhanced pll pins (part 2 of 3) note (1) pin description
altera corporation 1?15 july 2009 stratix ii device handbook, volume 2 plls in stratix ii and stratix ii gx devices fast plls stratix ii devices contain up to eight fast plls and stratix ii gx devices contain up to four fast plls. fast pl ls have high-speed differential i/o interface capability along wi th general-purpose features. fast pll hardware overview figure 1?7 shows a diagram of the fast pll. figure 1?7. stratix ii and stratix ii gx fast pll block diagram notes to figure 1?7 : (1) stratix ii and stratix ii gx fast plls only support manual clock switchover. (2) the global or regional clock input can be driven by an output from another pll, a pi n-driven dedicated global or regional clock, or through a clock control block provided th e clock control block is fed by an output from another pll or a pin-driven dedicated global or regional clock. an internally generated global signal cannot drive the pll. (3) in high-speed differential i/o support mode, this high-s peed pll clock feeds the serdes. stratix ii devices only support one rate of data transfer per fast p ll in high-speed differential i/o support mode. (4) this signal is a high-speed differential i/o support serdes control signal. (5) if the design enables this 2 counter, then the device can use a vco frequency range of 150 to 520 mhz. vcc_pll12_out external clock output v ccio power for pll12_out0p , pll12_out0n , pll12_out1p , pll12_out1n and pll12_out2p , pll12_out2n outputs from pll 12. note to ta b l e 1 ? 7 : (1) the negative leg pins ( clkn , pll_fbn , and pll_outn ) are only required with differential signaling. table 1?7. stratix ii and st ratix ii gx enhanced pll pins (part 3 of 3) note (1) pin description charge pump vco c1 8 8 4 4 8 clock input pfd c0 m loop filter phase frequency detector vco phase selection selectable at each pll output port post-scale counters global clocks diffioclk0 (3) loaden0 (4) diffioclk1 (3) loaden1 (4) regional clocks to dpa block global or regional clock (2) global or regional clock (2) c2 c3 n 4 clock (1) switchover circuitry shaded portions of the pll are reconfigurable k (5)
1?16 altera corporation stratix ii device handbook, volume 2 july 2009 fast plls external clock outputs each fast pll supports differential or single-ended outputs for source-synchronous transmitters or for general-purpose external clocks. there are no dedicated external clock output pins. the fast pll global or regional outputs can drive any i/o pin as an external clock output pin. the i/o standards supported by any particular bank determines what standards are possible for an external clock output driven by the fast pll in that bank. f for more information, see the selectable i/o standards in stratix ii and stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook (or the stratix ii device handbook ). fast pll software overview stratix ii and stratix ii gx fast plls are enabled in the quartus ii software by using the altpll megafunction. figure 1?8 shows the available ports (as they are named in the quartus ii altpll megafunction) of the stratix ii or stratix ii gx fast pll. figure 1?8. stratix ii and stratix ii gx fast pll port s and physical destinations notes to figure 1?8 : (1) this input pin is either si ngle-ended or differential. (2) this input pin is shared by all enhanced and fast plls. tables 1?8 and 1?9 show the description of all fast pll ports. inclk0 inclk1 scanwrite pfdena pllena c[3..0] locked physical pin scandataout signal driven by internal logic signal driven to internal logic internal clock signal scandone (1) areset scanclk scandata scanread (1) (2) table 1?8. fast pll input signals (part 1 of 2) name description source destination inclk0 primary clock input to the fast pll. pin or another pll n counter inclk1 secondary clock input to the fast pll. pin or another pll n counter
altera corporation 1?17 july 2009 stratix ii device handbook, volume 2 plls in stratix ii and stratix ii gx devices pllena enable pin for enabling or disabling all or a set of plls. active high. pin pll control signal clkswitch switch-over signal used to initiate external clock switch-over control. active high. logic array reconfiguration circuit areset enables the up/down outputs from the phase-frequency detector. active high. logic array pll control signal pfdena enables the up/down outputs from the phase-frequency detector. active high. logic array pfd scanclk serial clock signal for the real-time pll control feature. logic array reconfiguration circuit scandata serial input data stream for the real-time pll control feature. logic array reconfiguration circuit scanwrite enables writing the data in the scan chain into the pll active high. logic array reconfiguration circuit scanread enables scan data to be written into the scan chain active high. logic array reconfiguration circuit table 1?9. fast pll output signals name description source destination c[3..0] pll outputs driving regional or global clock. pll counter internal clock locked lock or gated lock output from lock detect circuit. active high. pll lock detect logic array scandataout output of the last shift register in the scan chain. pll scan chain logic array scandone signal indicating when the pll has completed reconfiguration. 1 to 0 transition indicates the pll has been reconfigured. pll scan chain logic array table 1?8. fast pll input signals (part 2 of 2) name description source destination
1?18 altera corporation stratix ii device handbook, volume 2 july 2009 fast plls fast pll pins table 1?10 shows the i/o standards supported by the fast pll input pins. table 1?10. i/o standards supported for st ratix ii and stratix ii gx fast pll pins i/o standard inclk lv t t l v lv c m o s v 2.5 v v 1.8 v v 1.5 v v 3.3-v pci 3.3-v pci-x sstl-2 class i v sstl-2 class ii v sstl-18 class i v sstl-18 class ii v 1.8-v hstl class i v 1.8-v hstl class ii v 1.5-v hstl class i v 1.5-v hstl class ii v differential sstl-2 class i differential sstl-2 class ii differential sstl-18 class i differential sstl-18 class ii 1.8-v differential hstl class i 1.8-v differential hstl class ii 1.5-v differential hstl class i 1.5-v differential hstl class ii lv d s v hypertransport technology v differential lvpecl
altera corporation 1?19 july 2009 stratix ii device handbook, volume 2 plls in stratix ii and stratix ii gx devices table 1?11 shows the physical pins and th eir purpose for the fast plls. for inclk port connections to pins, see ?clocking? on page 1?62 . table 1?11. fast pll pins (part 1 of 2) note (1) pin description clk0p/n single-ended or differential pins that can drive the inclk port for plls 1, 2, 7 or 8. clk1p/n single-ended or differential pins that can drive the inclk port for plls 1, 2, 7 or 8. clk2p/n single-ended or differential pins that can drive the inclk port for plls 1, 2, 7 or 8. clk3p/n single-ended or differential pins that can drive the inclk port for plls 1, 2, 7 or 8. clk8p/n single-ended or differential pins that can drive the inclk port for plls 3, 4, 9 or 10. clk9p/n single-ended or differential pins that can drive the inclk port for plls 3, 4, 9 or 10. clk10p/n single-ended or differential pins that can drive the inclk port for plls 3, 4, 9 or 10. clk11p/n single-ended or differential pins that can drive the inclk port for plls 3, 4, 9 or 10. fpll7clkp/n single-ended or differential pins that can drive the inclk port for pll 7. fpll8clkp/n single-ended or differential pins that can drive the inclk port for pll 8. fpll9clkp/n single-ended or differential pins that can drive the inclk port for pll 9 . fpll10clkp/n single-ended or differential pins that can drive the inclk port for pll 10. pll_ena dedicated input pin that drives the pllena port of all or a set of plls. if you do not use this pin, connect it to gnd. vccd_pll digital power for plls. you must connect this pin to 1.2 v, even if the pll is not used. vcca_pll1 analog power for pll 1. you must connect this pin to 1.2 v, even if the pll is not used. gnda_pll1 analog ground for pll 1. your can connect this pin to the gnd plane on the board. vcca_pll2 analog power for pll 2. you must connect this pin to 1.2 v, even if the pll is not used. gnda_pll2 analog ground for pll 2. you can connect this pin to the gnd plane on the board. vcca_pll3 analog power for pll 3. you must connect this pin to 1.2 v, even if the pll is not used . gnda_pll3 analog ground for pll 3. you can connect this pin to the gnd plane on the board. vcca_pll4 analog power for pll 4. you must connect this pin to 1.2 v, even if the pll is not used. gnda_pll4 analog ground for pll 4. you can connect this pin to the gnd plane on the board. gnda_pll7 analog ground for pll 7. you can connect this pin to the gnd plane on the board. vcca_pll8 analog power for pll 8. you must connect this pin to 1.2 v, even if the pll is not used. gnda_pll8 analog ground for pll 8. you can connect this pin to the gnd plane on the board. vcca_pll9 analog power for pll 9. you must connect this pin to 1.2 v, even if the pll is not used. gnda_pll9 analog ground for pll 9. you can connect this pin to the gnd plane on the board. vcca_pll10 analog power for pll 10. you must connect this pin to 1.2 v, even if the pll is not used.
1?20 altera corporation stratix ii device handbook, volume 2 july 2009 clock feedback modes clock feedback modes stratix ii and stratix ii gx plls support up to five different clock feedback modes. each mode allows clock multiplication and division, phase shifting, and programmable duty cycle. each pll must be driven by one of its own dedicated clock input pins for proper clock compensation. the clock in put pin connections for ea ch pll are listed in table 1?20 on page 1?70 . table 1?12 shows which modes are supported by which pll type. source-synchronous mode if data and clock arrive at the same time at the input pins, they are guaranteed to keep the same phase re lationship at the clock and data ports of any ioe input register. figure 1?9 shows an example waveform of the clock and data in this mode. this mode is reco mmended for source- synchronous data transfers. data and clock signals at the ioe experience similar buffer delays as long as the same i/o standard is used. gnda_pll10 analog ground for pll 10. you can connect this pin to the gnd plane on the board. note to ta b l e 1 ? 11 : (1) the negative leg pins ( clkn and fpll_clkn ) are only required with differential signaling. table 1?11. fast pll pins (part 2 of 2) note (1) pin description table 1?12. clock feedback mode availability clock feedback mode mode available in enhanced plls fast plls source synchronous mode yes yes no compensation mode yes yes normal mode yes yes zero delay buffer mode yes no external feedback mode yes no
altera corporation 1?21 july 2009 stratix ii device handbook, volume 2 plls in stratix ii and stratix ii gx devices figure 1?9. phase relationship between clock and data in source-synchronous mode in source-synchronous mode, enhanced plls compensate for clock delay to the top and bottom io registers and fast plls compensate for clock delay to the side io registers. whil e implementing source-synchronous receivers in these io banks, use the corresponding pll type for best matching between clock and data de lays (from input pins to register ports). 1 set the input pin to the register delay chain within the ioe to zero in the quartus ii software for all data pins clocked by a source-synchronous mode pll. no compensation mode in this mode, the pll does not comp ensate for any clock networks. this provides better jitter performance be cause the clock f eedback into the pfd does not pass through as much ci rcuitry. both the pll internal and external clock outputs are phase shifted with respect to the pll clock input. figure 1?10 shows an example waveform of the pll clocks? phase relationship in this mode. data pin inclk data at register clock at register
1?22 altera corporation stratix ii device handbook, volume 2 july 2009 clock feedback modes figure 1?10. phase relationship between pll clocks in no compensation mode notes to figure 1?10 . (1) internal clocks fed by the pll are phase-aligned to each other. (2) the pll clock outputs can lead or lag the pll input clocks. normal mode an internal clock in normal mode is phase-aligned to th e input clock pin. the external clock output pin will have a phase delay relative to the clock input pin if connected in this mode. in normal mode, the delay introduced by the gclk or rclk network is fully compensated. figure 1?11 shows an example waveform of the pll clocks? phase relationship in this mode. pll reference clock at the input pin pll clock at the register clock port (1) , (2) external pll clock outputs (2) phase aligned
altera corporation 1?23 july 2009 stratix ii device handbook, volume 2 plls in stratix ii and stratix ii gx devices figure 1?11. phase relationship betw een pll clocks in normal mode note to figure 1?11 : (1) the external clock output can lead or lag the pll internal clock signals. zero delay buffer mode in the zero delay buffer mode, th e external clock output pin is phase-aligned with the cl ock input pin for zero delay through the device. figure 1?12 shows an example waveform of the pll clocks? phase relationship in this mode. when using this mode, altera requires that you use the same i/o standard on the in put clock, and outp ut clocks. when using single-ended i/o standards, the inclk port of the pll must be fed by the dedicated clkp input pin. pll clock at the register clock port external pll clock outputs (1) phase aligned pll reference clock at the input pin
1?24 altera corporation stratix ii device handbook, volume 2 july 2009 clock feedback modes figure 1?12. phase relationship between pll clocks in zero delay buffer mode note to figure 1?12 : (1) the internal pll clock output can lead or lag the external pll clock outputs. external feedback mode in the external feedback mode, th e external feedback input pin, fbin , is phase-aligned with the clock input pin, (see figure 1?13 ). aligning these clocks allows you to remove clock de lay and skew between devices. this mode is possible on all enhanced plls. plls 5, 6, 11, and 12 support feedback for one of the dedicate d external outputs, either one single-ended or one differential pair. in this mode, one c counter feeds back to the pll fbin input, becoming part of the feedback loop. in this mode, you will be using one of the de dicated external clock outputs (two if a differential i/o standard is used) as the pll fbin input pin. when using this mode, altera requires that you use the same i/o standard on the input clock, feedback input, and output clocks. when using single-ended i/o standards, the inclk port of the pll must be fed by the dedicated clkp input pin. pll clock at the register clock port external pll clock outputs (1) phase aligned pll reference clock at the input pin
altera corporation 1?25 july 2009 stratix ii device handbook, volume 2 plls in stratix ii and stratix ii gx devices figure 1?13. phase relationship between pll clocks in external feedback mode note to figure 1?13 : (1) the pll clock outputs can lead or lag the f bin clock input. hardware features stratix ii and stratix ii gx plls support a number of features for general-purpose clock management. this section discusses clock multiplication and division im plementation, ph ase-shifting implementations and prog rammable duty cycles. table 1?13 shows which feature is available in which type of stratix ii or stratix ii gx pll. external pll clock outputs (1) pll clock at the register clock port (1) f bin clock input phase aligned pll reference clock at the input pin table 1?13. stratix ii and stratix ii gx pll hardware features (part 1 of 2) hardware features availability enhanced pll fast pll clock multiplication and division m ( n post-scale counter) m ( n post-scale counter) m counter value ranges from 1 through 512 ranges from 1 through 32 n counter value ranges from 1 through 512 ranges from 1 through 4 post-scale counter values ranges from 1 through 512 (1) ranges from 1 through 32 (2)
1?26 altera corporation stratix ii device handbook, volume 2 july 2009 hardware features clock multiplication and division each stratix ii pll provides clock synthesis for pll output ports using m /( n post-scale counter) scaling factors. the input clock is divided by a pre-scale factor, n , and is then multiplied by the m feedback factor. the control loop drives the vco to match f in ( m / n ). each output port has a unique post-scale counter that di vides down the high-frequency vco. for multiple pll outputs with differen t frequencies, the vco is set to the least common multiple of the output frequencies that meets its frequency specifications. for example, if output frequencies required from one pll are 33 and 66 mhz, then the quartus ii software sets the vco to 660 mhz (the least common multiple of 33 and 66 mhz within the vco range). then, the post-scale counters scal e down the vco frequency for each output port. there is one pre-scale counter, n , and one multiply counter, m , per pll, with a range of 1 to 512 for both m and n in enhanced plls. for fast plls, m ranges from 1 to 32 while n ranges from 1 to 4. there are six generic post-scale counters in enhanced plls that can feed region al clocks, global clocks, or external clock outputs, all ranging from 1 to 512 with a 50% duty cycle setting for each pll. the post-scale counters range from 1 to 256 with any non-50% duty cycle settin g. in fast plls, there are four post-scale counters ( c0 , c1 , c2 , c3 ) for the regional and global clock output ports. all post-scale counte rs range from 1 to 32 with a 50% duty cycle setting. for non-50% duty cycle clock outputs, the post-scale counters range from 1 to 16. if the desi gn uses a high-speed i/o interface, you can connect the dedicated dffioclk clock output port to allow the high-speed vco frequency to drive the serializer/deserializer (serdes). phase shift down to 125-ps increments (3) down to 125-ps increments (3) programmable duty cycle yes yes notes to table 1?13 : (1) post-scale counters range from 1 through 512 if the output clock uses a 50% duty cycle. for any output clocks using a non-50% duty cycle, the post-scale counters range from 1 through 256. (2) post-scale counters range from 1 through 32 if the output clock uses a 50% duty cycle. for any output clocks using a non-50% duty cycle, the post-scale counters range from 1 through 16. (3) the smallest phase shift is determin ed by the vco period divided by 8. fo r degree increments, the stratix ii device can shift all output frequencies in increments of at least 45 ? . smaller degree increments are possible depending on the frequency and divide parameters. table 1?13. stratix ii and stratix ii gx pll hardware features (part 2 of 2) hardware features availability enhanced pll fast pll
altera corporation 1?27 july 2009 stratix ii device handbook, volume 2 plls in stratix ii and stratix ii gx devices the quartus ii software automatically chooses the appropriate scaling factors according to the input freque ncy, multiplication, and division values entered into the altpll megafunction. phase-shift implementation phase shift is used to implement a robust solution for clock delays in stratix ii and stratix ii gx devices. phase shift is implemented by using a combination of the vco phase output and the counter starting time. the vco phase output and counter starting time is the most accurate method of inserting delays, since it is purely based on counter settings, which are independent of process, voltage, and temperature. 1 stratix ii and stratix ii gx plls do not support programmable delay elements because thes e delay elements require considerable area on the die and are sensitive to process, voltage, and temperature. you can phase shift the output clocks from the stratix ii or stratix ii gx enhanced pll in either: fine resolution using vco phase taps coarse resolution usin g counter starting time the vco phase tap and coun ter starting time is implemented by allowing any of the output counters ( c[5..0] or m ) to use any of the eight phases of the vco as the reference clock. this allows you to adjust the delay time with a fine resolution. the minimum delay time that you can insert using this method is defined by: where f ref is input reference clock frequency. for example, if f ref is 100 mhz, n is 1, and m is 8, then f vco is 800 mhz and ? f ine equals 156.25 ps. this phase shift is defined by the pll operating frequency, which is govern ed by the reference clock frequency and the counter settings. you can also delay the start of the counters for a predetermined number of counter clocks. you ca n express phase shift as: fine = t vco = = 1 8 1 8 f vco n 8 mf ref coarse = = c ? 1 f (c ? 1)n mf ref v co
1?28 altera corporation stratix ii device handbook, volume 2 july 2009 hardware features where c is the count value set for the coun ter delay time, (this is the initial setting in the pll usage section of the compilation report in the quartus ii software). if the initial value is 1, c ? 1 = 0 phase shift. figure 1?14 shows an example of phase sh ift insertion using the fine resolution using vco phase taps meth od. the eight phases from the vco are shown and labeled for reference. for this example, clk0 is based off the 0 ? phase from the vco and has the c value for the counter set to one. the clk1 signal is divided by four, two vco clocks for high time and two vco clocks for low time. clk1 is based off the 135 ? phase tap from the vco and also has the c value for the counter set to one. the clk1 signal is also divided by 4. in this ca se, the two clocks are offset by 3 ? fine . clk2 is based off the 0phase from the vco but has the c value for the counter set to three. this creates a delay of 2 ? coarse , (two complete vco periods). figure 1?14. delay insertion using vco phase output and counter delay time you can use the coarse and fine ph ase shifts as described above to implement clock delays in stratix ii and stratix ii gx devices. the phase-shift parameters are set in the quartus ii software. t d0-1 t d0-2 1/8 t vco t vco 0 90 135 180 225 270 315 clk0 clk1 clk2 45
altera corporation 1?29 july 2009 stratix ii device handbook, volume 2 plls in stratix ii and stratix ii gx devices programmable duty cycle the programmable duty cycle allows enhanced and fast plls to generate clock outputs with a variable duty cy cle. this feature is supported on each enhanced and fast pll post-scale counter c[] . the duty cycle setting is achieved by a low and high time count setting for the post-scale counters. the quartus ii software uses the frequency input and the required multiply or divide rate to determine the duty cycle choices. the post-scale counter value determines th e precision of the duty cycle. the precision is defined by 50% divided by the post-scale counter value. the closest value to 100 % is not achievable for a given counter value. for example, if the c0 counter is ten, then steps of 5% are possible for duty cycle choices between 5 to 90%. if the device uses external feedback , you must set the duty cycle for the counter driving the fbin pin to 50%. combining the programmable duty cycle with programmable phase shift allows the generation of precise non-overlapping clocks. advanced clear and enable control there are several control signals for cl earing and enabling plls and their outputs. you can use these signals to control pll resynchronization and gate pll output clocks for low-power applications. enhanced lock detect circuit the lock output indicates that the pll has locked onto the reference clock. without any additional ci rcuitry, the lock signal may toggle as the pll begins tracking the refere nce clock. you may need to gate the lock signal for use as a system control. either a gated lock signal or an ungated lock signal from the locked port can drive the logic array or an output pin. the stratix ii and stratix ii gx enhanced and fast plls include a programmable counter that holds the lock signal low for a user-selected number of input clock tr ansitions. this allows the pll to lock before enabling the lock signal. you can use the quartus ii software to set the 20-bit counter value.
1?30 altera corporation stratix ii device handbook, volume 2 july 2009 hardware features figure 1?15 shows the timing waveform for the lock and gated lock signals. figure 1?15. timing waveform for lock and gated lock signals the device resets and enables both the counter and the pll simultaneously when the pllena signal is asserted or the areset signal is de-asserted. enhanced plls and fast plls support this feature. to ensure correct circuit operation, and to ensure that the output clocks have the correct phase relationship with respect to the input clock, altera recommends that the input clock be ru nning before the stratix ii device is finished configuring. pll_ena the pll_ena pin is a dedicated pin that enables or disables all plls on the stratix ii or stratix ii gx device. when the pll_ena pin is low, the clock output ports are driven low and all the plls go out of lock. when the pll_ena pin goes high again, the plls relock and resynchronize to the input clocks. you can choose which plls are controlled by the pllena signal by connecting the pllena input port of the altpll megafunction to the common pll_ena input pin. also, whenever the pll loses lock for any reason (be it excessive inclk jitter, clock switchover, pll reconfiguration, power supply noise, etc.), the pll must be reset with the areset signal to guaran tee correct phase relationship between the pll output clocks. if the ph ase relationship between the input clock versus outp ut clock, and between different output clocks from the pll is not im portant in your design, the pll need not be reset. filter counter reaches value count pll_ena reference clock feedback clock lock gated lock
altera corporation 1?31 july 2009 stratix ii device handbook, volume 2 plls in stratix ii and stratix ii gx devices the level of the vccsel pin selects the pll_ena input buffer power. therefore, if vccsel is high, the pll_ena pin?s 1.8/1.5-v input buffer is powered by v ccio of the bank that pll_ena resides in. if vccsel is low ( gnd ), the pll_ena pin?s 3.3/2.5-v input buffer is powered by v ccpd . f for more information about the vccsel pin, refer to the configuring stratix ii and stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook (or the stratix ii device handbook) . pfdena the pfdena signals control the phase frequency detector (pfd) output with a programmable gate. if you disa ble the pfd, the vco operates at its last set value of control voltage and frequency with some long-term drift to a lower frequency. the system continues running when the pll goes out of lock or the input clock is disabled. by maintaining the last locked frequency, the system has time to store its current settings before shutting down. you ca n either use your own control signal or clkloss or gated locked status signals, to trigger pfdena . areset the areset signal is the reset or resynchronization input for each pll. the device input pins or internal logic can drive these input signals. when driven high, the pll counters reset, clearing the pll output and placing the pll out of lock. the vco is set back to its nominal setting (~700 mhz). when driven low again, the pll will resynchronize to its input as it relocks. if the target vco frequency is below this nominal frequency, then the output frequency starts at a higher value than desired as the pll locks. the areset signal should be asserted ev ery time the pll loses lock to guarantee correct phase relationship between the pll input clock and output clocks. users should include the areset signal in designs if any of the following conditions are true: pll reconfiguration or clock swit chover enabled in the design. phase relationships between the pl l input clock and output clocks need to be maintained after a loss of lock condition. if the input clock to the pll is not toggling or is unstable upon power up, assert the areset signal after the input cl ock is toggling, making sure to stay within the input jitter specification. 1 altera recommends that you use the areset and locked signals in your designs to control and observe the status of your pll.
1?32 altera corporation stratix ii device handbook, volume 2 july 2009 advanced features clkena if the system cannot tolerate the high er output frequencies when using pfdena higher value, the clkena signals can disable the output clocks until the pll locks. the clkena signals control the regional, global, and external clock outputs. the clkena signals are registered on the falling edge of the counter output clock to enable or disable the clock without glitches. see figure 1?56 in the ?clock control block? section on page 1?86 of this document for more information about the clkena signals. advanced features stratix ii and stratix ii gx plls offer a variety of advanced features, such as counter cascading, clock switchover, pll reconfiguration, reconfigurable bandwidth, an d spread-spectrum clocking. table 1?14 shows which advanced features are avai lable in which type of stratix ii or stratix ii gx pll. counter cascading the stratix ii and stratix ii gx enha nced pll supports counter cascading to create post-scale counters larger than 512. this is implemented by feeding the output of one counter into the input of the next counter in a cascade chain, as shown in figure 1?16 . table 1?14. stratix ii and stratix ii gx pll advanced features advanced feature availability enhanced plls fast plls (1) counter cascading v clock switchover vv pll reconfiguration vv reconfigurable bandwidth vv spread-spectrum clocking v note to table 1?14 : (1) stratix ii and stratix ii gx fast plls only support manual clock switchover, not automatic clock switchover.
altera corporation 1?33 july 2009 stratix ii device handbook, volume 2 plls in stratix ii and stratix ii gx devices figure 1?16. counter cascading when cascading counters to implem ent a larger division of the high-frequency vco clock, the cascaded counters behave as one counter with the product of the in dividual counter settings. for example, if c0 = 4 and c1 = 2, then the cascaded value is c0 c1 = 8. 1 the stratix ii and stratix ii gx fast plls does not support counter cascading. counter cascading is set in the config uration file, meaning they can not be cascaded using pll reconfiguration. clock switchover the clock switchover feature allo ws the pll to switch between two reference input clocks. use this feature for clock re dundancy or for a dual clock domain application such as in a system that turns on the redundant clock if the prim ary clock stops running. the design can perform clock switchover automatically, when the cloc k is no longer toggling, or based on a user control signal, clkswitch . 1 enhanced plls support both au tomatic and manual switchover, while fast plls only support manual switchover. automatic clock switchover stratix ii and stratix ii gx device plls support a fully configurable clock switchover capability. figure 1?17 shows the block diagram of the switch-over circuit built into the enha nced pll. when the primary clock signal is not present, the clock sens e block automatically switches from c0 c1 c2 c5 c3 c4 vco output vco output vco output vco output vco output vco output
1?34 altera corporation stratix ii device handbook, volume 2 july 2009 advanced features the primary to the secondary clock fo r pll reference. the design sends out the clk0 _ bad, clk1 _ bad , and the clk _ loss signals from the pll to implement a custom switchover circuit. figure 1?17. automatic clock swit chover circuit block diagram there are two possible ways to use the clock switchover feature. use the switchover circuitry for switching from a primary to secondary input of the same frequency. for example, in applications that require a redundant clock wi th the same frequency as the primary clock, the switchover state machine generates a signal that controls the multiplexer select input shown on the bottom of figure 1?17 . in this case, the secondary clock becomes the reference clock for the pll. this automatic switchover feature only works for switching from the prim ary to secondary clock. use the clkswitch input for user- or system-controlled switch conditions. this is possible for same-frequency switchover or to switch between inputs of different frequencies. for example, if inclk0 is 66 mhz and inclk1 is 100 mhz, you must control the switchover because the automatic clock-sense circuitry cannot monitor primary and secondary clock frequencies with a frequency difference of more than 20%. this feature is useful when clock sources can originate from multi ple cards on the backplane, requiring a system-controlled swit chover between frequencies of operation. you should choose the secondary clock frequency so the switch-over state machine clock sense n counter pfd clkswitch provides manual switchover support. clkloss activeclock clk0_bad clk0_bad muxout clksw inclk0 inclk1 refclk fbclk
altera corporation 1?35 july 2009 stratix ii device handbook, volume 2 plls in stratix ii and stratix ii gx devices vco operates within the recommen ded range of 500 to 1,000 mhz. you should also set the m and n counters accordingly to keep the vco operating frequency in the recommended range. figure 1?18 shows an example waveform of the switchover feature when using the automatic clkloss detection. here, the inclk0 signal gets stuck low. after the inclk0 signal is stuck at lo w for approximately two clock cycles, the clock se nse circuitry drives the clk0 _ bad signal high. also, because the reference cloc k signal is no t toggling, the clk _ loss signal goes low, indicating a switch condition. then, the switchover state machine controls the multiplexer through the clksw signal to switch to the secondary clock.
1?36 altera corporation stratix ii device handbook, volume 2 july 2009 advanced features figure 1?18. automatic switchover upon clock loss detection notes to figure 1?18 : (1) the number of clock edges before allowing switchover is determined by the counter setting. (2) switchover is enabled on the falling edge of inclk1 . (3) the rising edge of fbclk causes the vco frequency to decrease. (4) the rising edge of refclk starts the pll lock process agai n, and the vco fr equency increases. inclk0 inclk1 muxout refclk fbclk clk0bad clk1bad lock activeclock clkloss pll clock output (1) (2) (3) (4)
altera corporation 1?37 july 2009 stratix ii device handbook, volume 2 plls in stratix ii and stratix ii gx devices the switch-over state machine has two counters that count the edges of the primary and the secondary clocks; counter0 counts the number of inclk0 edges and counter1 counts the number of inclk1 edges. the counters get reset to zero when the count values reach 1, 1; 1, 2; 2, 1; or 2, 2 for i nclock0 and i nclock1 , respectively. for example, if counter0 counts two edges, its coun t is set to two and if counter1 counts two edges before the counter0 sees another edge, they are both reset to 0. if for some reason one of the counters counts to three, it means the other clock missed an edge. the clkbad0 or clkbad1 signal goes high, and the switchover circuitry signals a switch condition. see figure 1?19 . figure 1?19. clock-edge dete ction for switchover manual override when using automatic switchover, you can switch input clocks by using the manual override feature with the clkswitch input. 1 the manual override feature available in automatic clock switchover is different from manual clock switchover. figure 1?20 shows an example of a waveform illustrating the switchover feature when controlled by clkswitch . in this case, both clock sources are functional and inclk0 is selected as the primary clock. clkswitch goes high, which starts the switchover sequence. on the falling edge of inclk0 , the counter?s reference clock, muxout , is gated off to prevent any clock glitching. on the falling edge of inclk1 , the reference clock multiplexer switches from inclk0 to inclk1 as the pll reference and the activeclock signal changes to indicate which clock is selected as primary and which is secondary. the clkloss signal mirrors the clkswitch signal and activeclock mirrors clksw in this mode. since both clocks are still functional during the manual switch, neither clk_bad signal goes high. since the inclk0 inclk1 clkbad0 count of three on single clock indicates other missed edge. reset
1?38 altera corporation stratix ii device handbook, volume 2 july 2009 advanced features switchover circuit is edge-sensi tive, the falling edge of the clkswitch signal does not cause the ci rcuit to switch back from inclk1 to inclk0 . when the clkswitch signal goes high again, the process repeats. clkswitch and automatic switch only work if the clock being switched to is available. if the clock is not available, the state machine waits until the clock is available. figure 1?20. clock switchover using the clkswitch control note (1) note to figure 1?20 : (1) both inclk0 and inclk1 must be running when the clkswitch signal goes high to initiate a manual clock switchover event. failing to meet this requirement causes the clock swit chover to not function properly. figure 1?21 shows a simulation of using switchover for two different reference frequencies. in this example simulation, the reference clock is either 100 or 66 mhz. th e pll begins with f in = 100 mhz and is allowed to lock. at 20 ? s, the clock is switched to the secondary clock, which is at 66 mhz. inclk0 inclk1 m u xo u t clks w itch acti v eclock clkloss clk0 b ad clk1 b ad
altera corporation 1?39 july 2009 stratix ii device handbook, volume 2 plls in stratix ii and stratix ii gx devices figure 1?21. switchover simulation note (1) note to figure 1?21 : (1) this simulation was performed un der the following conditions: the n counter is set to 2, the m counter is set to 16, and the output counter is set to 8. therefore, the vco operates at 800 mhz for the 100-mhz input references and at 528 mhz for the 66-mhz reference input. lock signal-based switchover the lock circuitry can initiate the auto matic switchover. this is useful for cases where the input clock is still cl ocking, but its characteristics have changed so that the pll is not locked to it. the switchover enable is based on both the gated and ungated lock sign als. if the ungated lock is low, the switchover is not enabled until the gated lock has reached its terminal count. you must activate the switchover enable if the gated lock is high, but the ungated lock goes low. the sw itchover timing for this mode is similar to the waveform shown in figure 1?20 for clkswitch control, except the switchover enable replaces clkswitch . figure 1?17 shows the switchover enable circuit when controlled by lock and gated lock. figure 1?22. switchover enable circuit pll output frequency (x10 mhz) time ( s) 0 1 2 3 4 5 6 7 8 9 10 5 10 152025 30 3540 0 lock gated lock switchover enable
1?40 altera corporation stratix ii device handbook, volume 2 july 2009 advanced features manual clock switchover stratix ii and stratix ii gx enhanc ed and fast plls support manual switchover, where the clkswitch signal controls whether inclk0 or inclk1 is the input clock to the pll. if clkswitch is low, then inclk0 is selected; if clkswitch is high, then inclk1 is selected. figure 1?23 shows the block diagram of the manual switchover circuit in fast plls. the block diagram of the manual switchover circuit in enhanced plls is shown in figure 1?23 . figure 1?23. manual clock switchov er circuitry in fast plls figure 1?24 shows an example of a waveform illustrating the switchover feature when controlled by clkswitch . in this case, both clock sources are functional and inclk0 is selected as the primary clock. clkswitch goes high, which starts the switch-over sequence. on the falling edge of inclk0 , the counter?s reference clock, muxout , is gated off to prevent any clock glitching. on the rising edge of inclk1 , the reference clock multiplex switches from inclk0 to inclk1 as the pll reference. when the clkswitch signal goes low, the process repeats, causing the circuit to switch back from inclk1 to inclk0 . n counter pfd fbclk clkswitch inclk0 inclk1 muxout refclk
altera corporation 1?41 july 2009 stratix ii device handbook, volume 2 plls in stratix ii and stratix ii gx devices figure 1?24. manual switchover note (1) note to figure 1?24 : (1) both inclk0 and inclk1 must be running when the clkswitch signal goes high to initiate a manual clock switchover event. failing to meet this requirement causes the clock swit chover to not function properly. software support table 1?15 summarizes the signals used for clock switchover. inclk0 inclk1 clkswitch muxout table 1?15. altpll megafunction clock switchover signals (part 1 of 2) port description source destination inclk0 reference clk0 to the pll. i/o pin clock switchover circuit inclk1 reference clk1 to the pll. i/o pin clock switchover circuit clkbad0 (1) signal indicating that inclk0 is no longer toggling. clock switchover circuit logic array clkbad1 (1) signal indicating that inclk1 is no longer toggling. clock switchover circuit logic array clkswitch switchover signal used to initiate clock switchover asynchronously. when used in manual switchover, cl kswitch is used as a select signal between inclk0 and inclk1 clswitch = 0 inclk0 is selected and vice versa. logic array or i/o pin clock switchover circuit clkloss (1) signal indicating that the switchover circuit detected a switch condition. clock switchover circuit logic array locked signal indicating that the pll has lost lock. pll clock switchover circuit
1?42 altera corporation stratix ii device handbook, volume 2 july 2009 advanced features all the switchover ports shown in table 1?15 are supported in the altpll megafunction in the quartus ii software. the altpll megafunction supports two me thods for clock switchover: when selecting an enhanced pll, you can enable both the automatic and the manual switchover, making all the clock switchover ports available. when selecting a fast pll, you can use only enable the manual clock switchover option to select between inclk0 or inclk1 . the clkloss , activeclock and the clkbad0 , and clkbad1 signals are not available when manual switchover is selected. if the primary and secondary cloc k frequencies are different, the quartus ii software selects the proper parameters to keep the vco within the recommended frequency range. f for more information about pll software support in the quartus ii software, see the altpll megafunction user guide . guidelines use the following guidelines to design with clock switchover in plls. when using automatic switchover, the clkswitch signal has a minimum pulse width based on the two reference clock periods. the clkswitch pulse width must be greater than or equal to the period of the current reference clock (t from_clk ) multiplied by two plus the rounded-up version of the ratio of the two reference clock periods. for example, if t to_clk is equal to t from_clk , then the clkswitch pulse width should be at least three ti mes the period of the clock pulse. t clkswitchch min ? t from_clk ? [2 + int round_up (t to_clk ?? t from_clk )] activeclock (1) signal to indicate which clock (0 = inclk0 , 1= inclk1 ) is driving the pll. pll logic array note for ta b l e 1 ? 1 5 : (1) these ports are only available for enhanced plls an d in auto mode and when using automatic switchover. table 1?15. altpll megafunction clock switchover signals (part 2 of 2) port description source destination
altera corporation 1?43 july 2009 stratix ii device handbook, volume 2 plls in stratix ii and stratix ii gx devices applications that require a cloc k switchover feature and a small frequency drift should use a low-bandwidth pll. the low-bandwidth pll reacts slower than a high-bandwidth pll to reference input clock changes. when the switchover happens, a low-bandwidth pll propagates th e stopping of the clock to the output slower than a high-band width pll. a low-bandwidth pll filters out jitter on the reference clock. however, be aware that the low-bandwidth pll also increases lock time. stratix ii and stratix ii gx device plls can use both the automatic clock switchover and the clkswitch input simultaneously. therefore, the switchover circuitry can automatically switch from the primary to the secondary clock. on ce the primary clock stabilizes again, the clkswitch signal can switch back to the primary clock. during switchover, the pll_vco continues to run and slows down, generating frequency drift on the pll outputs. the clkswitch signal controls switchover with its rising edge only. if the clock switchover event is gl itch-free, after the switch occurs, there is still a finite resynchronizat ion period to lock onto a new clock as the vco ramps up. the exact amou nt of time it takes for the pll to relock is dependent on the pll configuration. use the pll programmable bandwidth feature to adjust the relock time. if the phase relationship betwee n the input clock to the pll and output clock from the pll is im portant in your design, assert areset for 10ns after performing a clock switchover. wait for the locked signal (or gated lock) to go high before re-enabling the output clocks from the pll. figure 1?25 shows how the vco frequency gradually decreases when the primary clock is lost an d then increases as the vco locks on to the secondary clock. after the vco locks on to the secondary clock, some overshoot can occur (an over-frequency condition) in the vco frequency. figure 1?25. vco switchover operating frequency f vco primary clock stops running switchover occurs frequency overshoot vco tracks secondary clock
1?44 altera corporation stratix ii device handbook, volume 2 july 2009 reconfigurable bandwidth disable the system during switchover if it is not tolerant to frequency variations during the pll resync hronization period. there are two ways to disable the system. first, the system may require some time to stop before switchover occurs. the switchover circuitry includes an optional five-bit counter to de lay when the reference clock is switched. you have the option to cont rol the time-out setting on this counter (up to 32 cycles of latency) before the clock source switches. you can use these cycles for disaster recovery. the clock output frequency varies slightly during those 32 cycles since the vco can still drift without an input clock. programmable bandwidth can control the pll response to limit dr ift during this 32 cycle period. a second option available is the ab ility to use the pfd enable signal ( pfdena ) along with user-defined control logic. in this case you can use clk0 _ bad and clk1 _ bad status signals to turn off the pfd so the vco maintains its last frequency. you can also use the state machine to switch over to the second ary clock. upon re-enabling the pfd, output clock enable signals ( clkena ) can disable clock outputs during the switchover and resynchr onization period. once the lock indication is stable, the system can re-enable the output clock(s). reconfigurable bandwidth stratix ii and stratix ii gx enhanced and fast plls provide advanced control of the pll bandwidth us ing the pll loop?s programmable characteristics, including loop filter and charge pump. background pll bandwidth is the measure of the pll?s ability to track the input clock and jitter. the closed-loop gain 3-db frequency in the pll determines the pll bandwidth. the bandwidth is approximately the unity gain point for open loop pll response. as figure 1?26 shows, these points correspond to approximately the same frequency.
altera corporation 1?45 july 2009 stratix ii device handbook, volume 2 plls in stratix ii and stratix ii gx devices figure 1?26. open- and closed-loop response bode plots a high-bandwidth pll provid es a fast lock time and tracks jitter on the reference clock source, passing it through to the pll output. a low-bandwidth pll filters out reference clock, but increases lock time. stratix ii and stratix ii gx enhanced and fast plls allow you to control the bandwidth over a finite range to customize the pll characteristics for a particular applicatio n. the programmable bandwidth feature in stratix ii and stratix ii gx plls benefits applications requiring clock switchover (e.g., tdma frequency hopping wireless, and redundant clocking). increasing the pll's bandwidth in effect pushes the open loop response out. gain gain 0 db frequency frequency open-loop reponse bode plot closed-loop reponse bode plot
1?46 altera corporation stratix ii device handbook, volume 2 july 2009 reconfigurable bandwidth the bandwidth and stability of such a system is determined by the charge pump current, the loop filter resis tor value, the high -frequency capacitor value (in the loop filter), and the m -counter value. you can use the quartus ii software to control these factors and to set the bandwidth to the desired value within a given range. you can set the bandwidth to the appropriate value to balance the need for jitter filtering and lock time. figures 1?27 and 1?28 show the output of a low- and high-bandwidth pll, respectively, as it locks onto the input clock. figure 1?27. low-bandwidth pll lock time 05 15 10 time ( s) frequency (mhz) 120 125 130 135 140 145 150 155 160 lock time = 8 s
altera corporation 1?47 july 2009 stratix ii device handbook, volume 2 plls in stratix ii and stratix ii gx devices figure 1?28. high-bandwidth pll lock time a high-bandwidth pll can benefit a sy stem that has two cascaded plls. if the first pll us es spread spectrum (as user-induced jitter), the second pll can track the jitter that is fe eding it by using a high-bandwidth setting. a low-bandwidth pll can, in this case, lose lock due to the spread-spectrum-induced jitter on the input clock. a low-bandwidth pll benefits a system using clock switchover. when the clock switchover happens, the pll input temporarily stops. a low-bandwidth pll would react more slowly to changes to its input clock and take longer to drift to a lo wer frequency (caused by the input stopping) than a hi gh-bandwidth pll. figures 1?29 and 1?30 demonstrate this property. the two plots show the effects of clock switchover with a low- or high -bandwidth pll. when the clock switchover happens, the output of the low-bandwidth pll (see figure 1?29 ) drifts to a lower frequency more slowly than the high-bandwidth pl l output (see figure 1?30 ). 0 120 125 130 135 140 145 150 155 160 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 time ( s) frequency (mhz) lock time = 4 s
1?48 altera corporation stratix ii device handbook, volume 2 july 2009 reconfigurable bandwidth figure 1?29. effect of low bandwidth on clock switchover 0 150 152 154 156 158 160 162 164 5 10152025303540 time ( s) frequency (mhz) initial lock input clock stops re-lock switchover
altera corporation 1?49 july 2009 stratix ii device handbook, volume 2 plls in stratix ii and stratix ii gx devices figure 1?30. effect of high bandwidth on clock switchover implementation traditionally, external components such as the vco or loop filter control a pll?s bandwidth. most loop filters are made up of passive components such as resistors and capacitors that take up unnecessary board space and increase cost. with stratix ii and stra tix ii gx plls, all the components are contained within the device to increase performance and decrease cost. stratix ii and stratix ii gx device plls implement reconfigurable bandwidth by giving you control of the charge pump current and loop filter resistor (r) and high-frequency capacitor c h values (see table 1?16 ). the stratix ii and stratix ii gx devi ce enhanced pll bandwidth ranges from 130 khz to 16.9 mhz. the stratix i i and stratix ii gx device fast pll bandwidth ranges from 1.16 to 28 mhz. 0 125 130 135 140 145 150 155 160 2 4 6 8 10 12 14 16 18 20 time ( s) frequency (mhz) initial lock input clock stops re-lock switchover
1?50 altera corporation stratix ii device handbook, volume 2 july 2009 reconfigurable bandwidth the charge pump current directly affects the pll bandwidth. the higher the charge pump current, the higher the pll bandwidth. you can choose from a fixed set of values for the charge pump current. figure 1?31 shows the loop filter and the components th at can be set through the quartus ii software. the components are the loop filter resistor, r, and the high frequency capacitor, c h , and the charge pump current, i up or i dn . figure 1?31. loop filter programmable components software support the quartus ii software provides two levels of bandwidth control. megafunction-based bandwidth setting the first level of programmable bandwidth allows you to enter a value for the desired bandwidth directly in to the quartus ii software using the altpll megafunction. you can also set the bandwidth parameter in the altpll megafunction to the desired ba ndwidth. the quartus ii software selects the best bandwidth parameters available to match your bandwidth request. if the individual bandwidth setting request is not available, the quartus ii software se lects the closest achievable value. advanced bandwidth setting an advanced level of control is also possible using advanced loop filter parameters. you can dynamically change the charge pump current, loop filter resistor value, and the loop fi lter (high frequency) capacitor value. i up i dn c h pfd r c
altera corporation 1?51 july 2009 stratix ii device handbook, volume 2 plls in stratix ii and stratix ii gx devices the parameters for these changes are: charge _ pump _ current , loop _ filter _ r , and loop _ filter _ c . each parameter supports the specific range of values listed in table 1?16 . f for more information about quartus ii software support of reconfigurable bandwidth, see the design example: dynamic pll reconfiguration section in volume 3, ve r i f i c a t i o n , of the quartus ii development software handbook . pll reconfiguration plls use several divide counters and different vco phase taps to perform frequency synthesis and phase shifts. in stratix ii and stratix ii gx enhanced and fast plls, the counter value and phase are configurable in real time. in addition , you can change th e loop filter and charge pump components, which affect the pll bandwidth, on the fly. you can control these pll components to update the output clock frequency, pll bandwidth, and phase-sh ift variation in real time, without the need to reconfig ure the entire fpga. f for more information about pll reconfiguration, see an 367: implementing pll reconfigur ation in stratix ii devices . spread- spectrum clocking digital cloc ks are square waves with short rise times and a 50% duty cycle. these high-speed clocks concentrate a sign ificant amount of energy in a narrow bandwidth at the target frequency and at the higher frequency harmonics. this results in high energy peaks and increased electromagnetic interferen ce (emi). the radiated noise from the energy peaks travels in free air and, if not minimized, can lead to corrupted data and intermittent system errors, whic h can jeopardize system reliability. traditional methods for limiting emi include shielding, filtering, and multi-layer printed circuit boards (pcbs). however, these methods significantly increase the overall system cost and sometimes are not table 1?16. advanced loop filter parameters parameter values resistor values (k ? ) (1) high-frequency capacit ance values (pf) (1) charge pump current settings ( ??? (1) note to table 1?16 : (1) for more information, see an 367: implementing pll reconfiguration in stratix ii devices .
1?52 altera corporation stratix ii device handbook, volume 2 july 2009 spread-spectrum clocking enough to meet emi compliance. sp read-spectrum technology provides you with a simple and effective technique for reducing emi without additional cost and the trou ble of re-designing a board. spread-spectrum technology modulates the target frequency over a small range. for example, if a 100-mhz signal has a 0.5% down-spread modulation, then the frequency is swept from 99.5 to 100 mhz. figure 1?32 gives a graphical representation of the energy present in a spread-spectrum signal vs. a non-spre ad spectrum-signal. it is apparent that instead of concentrating the en ergy at the target frequency, the energy is re-distributed across a wider band of frequencies, which reduces peak energy. not only is there a reduction in the fundamental peak emi components, but there is also a reduction in emi of the higher order harmonics. since some regulations focus on peak emi emissions, rather than average emi emissions, spread-spectrum technology is a valuable method of emi reduction. figure 1?32. spread-spectrum signal energy ve rsus non-spread-spectrum signal energy spread-spectrum technology would benefit a design with high emi emissions and/or strict emi requir ements. device-generated emi is dependent on frequency and output voltage swing amplitude and edge rate. for example, a design using lvds already has low emi emissions = 0.5 % = ~5 db amplitude (db) frequency (mhz) spread-spectrum signal non-spread-spectrum signal
altera corporation 1?53 july 2009 stratix ii device handbook, volume 2 plls in stratix ii and stratix ii gx devices because of the low-voltage swing. th e differential lvds signal also allows for emi rejection within the si gnal. therefore, this situation may not require spread-spectrum technology. 1 spread-spectrum clocking is only supported in stratix ii enhanced plls, not fast plls. implementation stratix ii and stratix ii gx device enhanced plls feature spread-spectrum technology to reduce the emis emitted from the device. the enhanced pll provides approximately 0.5% down spread using a triangular, also known as linear, mo dulation profile. the modulation frequency is programmable and rang es from approximately 30 khz to 150 khz. the spread percentage is based on the clock input to the pll and the m and n settings. spread-spectrum technology reduces the peak energy by four to six db at the target frequency. however, this number is dependent on bandwidth and the m and n counter values and can vary from design to design. spread percentage, also known as mo dulation width, is defined as the percentage that the design modulates the target frequency. a negative (?) percentage indicates a down spread, a positive (+) percentage indicates an up spread, and a ( ? ) indicates a center spread. modulation frequency is the frequency of the spreading sign al, or how fast the signal sweeps from the minimum to the maximum frequency. down-spread modulation shifts the target freq uency down by half the spread percentage, centering the modulated waveforms on a new target frequency. the m and n counter values are toggled at the same time between two fixed values. the loop fi lter then slowly changes the vco frequency to provide the spreading effect, which results in a triangular modulation. an additional spread-spect rum counter (shown in figure 1?33 ) sets the modulation frequency. figure 1?33 shows how spread-spectrum technology is implemented in the stratix ii and stratix ii gx device enhanced pll.
1?54 altera corporation stratix ii device handbook, volume 2 july 2009 spread-spectrum clocking figure 1?33. stratix ii and stratix ii gx spread-spectrum ci rcuit block diagram figure 1?34 shows a vco frequency waveform when toggling between different counter values. since the enhanced pll switches between two different m and n values, the result is a straight line between two frequencies, which gives a linear modulation. the magnitude of modulation is determined by the ratio of two m / n sets. the percent spread is determined by: percent spread = (f vcomax -f vcomin )/f vcomax =1 [( m 2 n 1 )/( m 1 n 2 )]. the maximum and minimum vco frequency is defined as: f vcomax =( m 1 / n 1 )f ref f vcomin =( m 2 / n 2 )f ref figure 1?34. vco frequency modulation waveform n n count1 n count2 pfd up down spread- spectrum counter m m count1 m count2 refclk count2 values count1 values vco frequency
altera corporation 1?55 july 2009 stratix ii device handbook, volume 2 plls in stratix ii and stratix ii gx devices software support you can enter the desired down-spread percentage and modulation frequency in the altpll megafunction through the quartus ii software. alternatively, the downspread parameter in the altpll megafunction can be set to the desired down-spread percentage. timing analysis ensures the design operates at the maximum spread frequency and meets all timing requirements. f for more information about pll software support in the quartus ii software, see the altpll megafunction user guide . guidelines if the design cascades plls, the source (upstream) pll should have a low-bandwidth setting, while the destination (downstream) pll should have a high-bandwidth setting. the upstream pll must have a low-bandwidth setting because a pll do es not generate jitter higher than its bandwidth. the downstream pll mu st have a high bandwidth setting to track the jitter. the design must use the spread-spectrum feature in a low-bandwidth pll, and, theref ore, the quartus ii software automatically sets the spread-s pectrum pll bandwidth to low. 1 if the programmable or reconfig urable bandwidth features are used, then you cannot use spread spectrum. stratix ii and stratix ii gx devices can accept a spread-spectrum input with typical modulation frequenc ies. however, the device cannot automatically detect that the input is a spread-spectrum signal. instead, the input signal looks like determin istic jitter at the input of the downstream pll. spread spectrum can have a minor effect on the output clock by increasing the period jitter. period jitt er is the deviation of a clock?s cycle time from its previous cycle position . period jitter measures the variation of the clock output tran sition from its ideal po sition over consecutive edges. with down-spread modulation, the pe ak of the modulated waveform is the actual target frequency. therefore, the system never exceeds the maximum clock speed. to maintain reliable communication, the entire system and subsystem should use the stratix ii and strati x ii gx device as the clock source. communication could fail if the stratix ii or stratix ii gx logic array is clocked by the spread-spectrum clock, but the data it receives from another devi ce is not clocked by the spread spectrum.
1?56 altera corporation stratix ii device handbook, volume 2 july 2009 board layout since spread spectrum affects the m counter values, all spread-spectrum pll outputs are effected. therefore, if only one spread-spectrum signal is needed, the clock signal should use a separate pll without other outputs from that pll. no special considerations are needed when using spread spectrum with the clock switchover feature. this is because the clock switchover feature does not affect the m and n counter values, which are the counter values switching when using spread spectrum. board layout the enhanced and fast pll circuits in stratix ii and stratix ii gx devices contain analog components embedded in a digital device. these analog components have separate power an d ground pins to minimize noise generated by the digital components. stratix ii and stratix ii gx enhanced and fast plls use separate v cc and ground pins to isolate circuitry and improve noise resistance. v cca and gnda each enhanced and fast pll uses separate v cc and ground pin pairs for their analog circuitry. the analog ci rcuit power and ground pin for each pll is called vcca_pll < pll number > and gnda_pll < pll number >. connect the v cca power pin to a 1.2-v power supply, even if you do not use the pll. isolate the power connected to v cca from the power to the rest of the stratix ii or stratix ii gx device or any other digital device on the board. you can use one of three different methods of isolating the v cca pin: separate v cca power planes, a partitioned v cca island within the v ccint plane, and thick v cca traces. separate v cca power plane a mixed signal system is already partitioned into analog and digital sections, each with its own power plan es on the board. to isolate the v cca pin using a separate v cca power plane, connect the v cca pin to the analog 1.2-v power plane. partitioned v cca island within v ccint plane fully digital systems do not have a separate analog power plane on the board. since it is expensive to add ne w planes to the board, you can create islands for vcca_pll . figure 1?35 shows an example board layout with an analog power island. the dielectric boundary that creates the island should be 25 mils thick. figure 1?36 shows a partitioned plane within v ccint for v cca .
altera corporation 1?57 july 2009 stratix ii device handbook, volume 2 plls in stratix ii and stratix ii gx devices figure 1?35. v ccint plane partitioned for v cca island thick v cca trace because of board constraints, you may not be able to partition a v cca island. instead, run a thick trac e from the power supply to each v cca pin. the traces should be at least 20 mils thick. in each of these three cases, you should filter each vcca_pll pin with a decoupling circuit, as shown in figure 1?36 . place a ferrite bead that exhibits high impedance at freque ncies of 50 mhz or higher and a 10- ? f tantalum parallel capacitor where the power enters the board. decouple each vcca_pll pin with a 0.1- ? f and 0.001- ? f parallel combination of ceramic capacitors located as close as possible to the stratix ii or stratix ii gx device. you can connect the gnda_pll pins directly to the same ground plane as the device?s digital ground.
1?58 altera corporation stratix ii device handbook, volume 2 july 2009 board layout figure 1?36. pll power schematic for stratix ii and stra tix ii gx plls note to figure 1?36 (1) applies to plls 1 through 12. v ccd the digital power and ground pins are labeled vccd_pll < pll number > and gnd . the vccd pin supplies the power for the digital circuitry in the pll. connect these vccd pins to the quietest digi tal supply on the board. in most systems, this is the digital 1.2-v supply supplied to the device?s v ccint pins. connect the vccd pins to a power supply even if you do not use the pll. when connecting the v ccd pins to v ccint , you do not need any filtering or isolation. you can connect the gnd pins directly to the same ground plane as the device?s digital ground. see figure 1?36 . external clock output power enhanced plls 5, 6, 11, and 12 also have isolated power pins for their dedicated external clock outputs ( vcc_pll5_out , vcc_pll6_out , vcc_pll11_out and vcc_pll12_out , respectively). since the vcca_pll # gnda_pll # vccd_pll # gnd 1.2-v supply repeat for each pll power & ground set stratix ii device ferrite bead 0.1 f 0.001 f gnd gnd 10 f gnd gnd (1) (1) v ccint
altera corporation 1?59 july 2009 stratix ii device handbook, volume 2 plls in stratix ii and stratix ii gx devices dedicated external clock outputs fr om a particular enhanced pll are powered by separate power pins, they are less susceptibl e to noise. they also reduce the overall jitter of th e output clock by providing improved isolation from switching i/o pins. 1 i/o pins that reside in pll ba nks 9 through 12 are powered by the vcc_pll < 5, 6, 11, or 12 > _out pins, respectively. the ep2s60f484, ep2s60f780, ep 2s90h484, ep2s90f780, and ep2s130f780 devices do not support plls 11 and 12. therefore, any i/o pins that reside in bank 11 are powered by the vccio3 pin, and any i/o pins that reside in bank 12 are powered by the vccio8 pin. the vcc_pll_out pins can by powered by 3. 3, 2.5, 1.8, or 1.5 v, depending on the i/o standard for th e clock output from a particular enhanced pll, as shown in figure 1?37 .
1?60 altera corporation stratix ii device handbook, volume 2 july 2009 board layout figure 1?37. external clock output pi n association with output power filter each isolated power pin with a decoupling circuit shown in figure 1?38 . decouple the isolated power pi ns with parallel combination of 0.1- and 0.001- ? f ? ceramic capacitors located as close as possible to the stratix ii or stratix ii gx device. vcc_pll5_out pll5_out0p pll5_out0n pll5_out1p pll5_out1n pll5_out2p pll5_out2n
altera corporation 1?61 july 2009 stratix ii device handbook, volume 2 plls in stratix ii and stratix ii gx devices figure 1?38. stratix ii and strati x ii gx pll external cl ock output power ball connection note (1) note to figure 1?38 : (1) applies only to enhanced plls 5, 6, 11, and 12. guidelines use the following guidelines for optimal jitter performance on the external clock outputs from enhanced pl ls 5, 6, 11, and 12. if all outputs are running at the same frequency, these guidelines ar e not necessary to improve performance. use phase shift to ensure edges are not coincident on all the clock outputs. use phase shift to skew clock edges with respect to each other for best jitter performance. if you cannot drive multiple clocks of different frequencies and phase shifts or isolate banks, you should control the drive capability on the lower-frequency clock. reducing how much current the output buffer has to supply can reduce the noise. minimi ze capacitive load on the slower frequency output and configure the output buffer to lower current strength. the higher-frequency outp ut should have an improved performance, but this may degrade the performance of your lower- frequency clock output. vcc_pll#_out (1) vcc_pll#_out (1) v ccio supply stratix ii or stratix ii gx device 0.1 f 0.001 f gnd gnd 0.1 f 0.001 f gnd gnd
1?62 altera corporation stratix ii device handbook, volume 2 july 2009 pll specifications pll specifications f see the dc & switching characteristics chapter in volume 1 of the stratix ii gx device handbook (or the stratix ii device handbook ) for information about pll timing specifications clocking stratix ii and stratix ii gx devices pr ovide a hierarchical clock structure and multiple plls with ad vanced features. the large number of clocking resources in combination with the clock synthesis precision provided by enhanced and fast plls provides a complete clock-management solution. global and hierarchical clocking stratix ii and stratix ii gx devices provide 16 dedicated global clock networks and 32 regional clock networ ks. these clocks are organized into a hierarchical clock structure that al lows for 24 unique clock sources per device quadrant with low skew and delay. this hierarchical clocking scheme provides up to 48 unique clock domains within the entire stratix ii or stratix ii gx device. table 1?17 lists the clock resources available on stratix ii devices. there are 16 dedicated clock pins ( clk[15..0] ) on stratix ii and stratix ii gx devices to drive either th e global or region al clock networks. four clock pins drive each side of the stratix ii device, as shown in figures 1?39 and 1?40 . enhanced and fast pll outputs can also drive the global and regional clock networks. table 1?17. clock resource availability in st ratix ii and stratix ii gx devices (part 1 of 2) description stratix ii device availability stratix ii gx device availability number of clock input pins 24 12 number of global clock networks 16 16 number of regional clock networks 32 32 global clock input sources clock input pins, pll outputs, logic array clock input pins, pll outputs, logic array, inter-transceiver clocks regional clock input sources clock input pins, pll outputs, logic array clock input pins, pll outputs, logic array, inter-transceiver clocks number of unique clock sources in a quadrant 24 (16 global clocks and 8 regional clocks) 24 (16 gclk and 8 rclk clocks) number of unique clock sources in the entire device 48 (16 global clocks and 32 regional clocks) 48 (16 gclk and 32 rclk clocks)
altera corporation 1?63 july 2009 stratix ii device handbook, volume 2 plls in stratix ii and stratix ii gx devices global clock network global clocks drive throughout the entire device, feeding all device quadrants. all resources within the device ioes, adaptive logic modules (alms), digital signal processing (d sp) blocks, and all memory blocks can use the global clock networks as clock sources. these resources can also be used for control signals, such as clock enables and synchronous or asynchronous clears fed by an external pin. internal logic can also drive the global clock networks for internally generated global clocks and asynchronous clears, clock enables, or other control signals with large fanout. figure 1?39 shows the 16 dedicated clk pins driving global clock networks. figure 1?39. global clocking note (1) note to figure 1?39 : (1) stratix ii gx devices do not have plls 3, 4, 9, and 10 or clock pins 8, 9, 10, and 11. power-down mode global clock networks, regional clock networks, dual-regional clock region gclk, rclk networks, dual-regional clock region clocking regions for high fan-out applications quadrant region, dual-regional, entire device via global clock or regional clock networks quadrant region, dual-regional, entire device via gclk or rclk networks table 1?17. clock resource availability in st ratix ii and stratix ii gx devices (part 2 of 2) description stratix ii device availability stratix ii gx device availability 11 5 7 1 2 8 12 6 10 4 3 9 gclk0-3 gclk4-7 gclk8-11 gclk12 - 15 clk12-15 clk4-7 clk0-3 clk8-11 16 16 16 16
1?64 altera corporation stratix ii device handbook, volume 2 july 2009 clocking regional clock network eight regional clock networks within each quadrant of the stratix ii and stratix ii gx device are driven by the dedicated clk[15..0] input pins or from pll outputs. the regional clock networks only pertain to the quadrant they drive into. the regional clock networks provide the lowest clock delay and skew for logic cont ained within a single quadrant. internal logic can also drive the regi onal clock networks for internally generated regional clocks and asynch ronous clears, clock enables, or other control signals with large fanout.the clk clock pins symmetrically drive the rclk networks within a particular quadra nt, as shown in figure 1?40 . refer to table 1?18 on page 1?67 and table 1?19 on page 1?68 for rclk connections from clk pins and plls. figure 1?40. regional clocking note (1) note to figure 1?40 : (1) stratix ii gx devices do not have plls 3, 4, 9, and 10 or clock pins 8, 9, 10, and 11. clock sources per region each stratix ii and stratix ii gx device has 16 global clock networks and 32 regional clock networks that prov ide 48 unique clock domains for the entire device. there are 24 unique clocks available in each quadrant (16 global clocks and 8 regional clocks) as the input resources for registers (see figure 1?41 ). 11 5 7 1 2 8 6 10 4 3 9 rclk0-3 rclk4-7 rclk8-11 rclk12-15 rclk20-23 rclk24-27 rclk28-31 clk12-15 clk4-7 clk0 -3 clk8-11 rclk16-19 q1 q4 q2 q3 12
altera corporation 1?65 july 2009 stratix ii device handbook, volume 2 plls in stratix ii and stratix ii gx devices figure 1?41. hierarchical clock networks per quadrant stratix ii and stratix ii gx clock netw orks provide three different clocking regions: entire device clock region quadrant cl ock region dual-regional clock region these clock network option s provide more flexibility for routing signals that have high fan-out to improve th e interface timing. by having various sized clock regions, it is possible to prioritize the number of registers the network can reach versus the total delay of the network. in the first clock scheme, a source (not necessarily a clock signal) drives a global clock network that can be rout ed through the entire device. this has the maximum delay for a low skew high fan-out signal but allows the signal to reach every block within the device. this is a good option for routing global resets or clear signals. in the second clock scheme, a source drives a single-quadrant region. this represents the fastest, low-skew, high-fan-out signal-routing resource within a quadrant. the limitation to this resource is that it only covers a single quadrant. in the third clock scheme, a single source (clock pin or pll output) can generate a dual-regional clock by driving two regional clock network lines (one from each quadrant). this allows logic that spans multiple quadrants to utilize the same low-skew clock. the routing of this signal on an entire side has approximately the same speed as in a quadrant clock region. the internal logic-array rout ing that can drive a regional clock also supports this feature. this means internal logic can drive a clock [23..0] column i/o cell io_clk[7..0] lab row clock [5..0] row i/o cell io_clk[7..0] global clock network [15..0] regional clock network [7..0] clocks available to a quadrant or half-quadrant
1?66 altera corporation stratix ii device handbook, volume 2 july 2009 clocking dual-regional clock network. corner fast pll output s only span one quadrant and hence cannot form a dual-regional clock network. figure 1?42 shows this feature pictorially. figure 1?42. stratix ii and stratix ii gx dual-regional clock region the 16 clock input pins, enhanced or fa st pll outputs, and internal logic array can be the clock input sources to drive onto either global or regional clock networks. the clkn pins also drive the global clock network as shown in table 1?22 on page 1?72 . tables 1?18 and 1?19 for the connectivity between clk pins as well as the gl obal and regional clock networks. clock inputs the clock input pins clk[15..0] are also used for high fan-out control signals, such as asynchronous clears, presets, clock enables, or protocol signals such as trdy and irdy for pci through global or regional clock networks. internal logic array each global and regional clock networ k can also be driven by logic-array routing to enable internal logic to dr ive a high fan-out, low-skew signal. pll outputs all clock networks can be driven by the pll counter outputs. clock pins or pll outputs can drive half of the device to create dual-reginal clocking regions for improved i/o interface timing.
altera corporation 1?67 july 2009 stratix ii device handbook, volume 2 plls in stratix ii and stratix ii gx devices table 1?18 shows the connection of the clock pins to the global clock resources. the reason for the higher level of connectivity is to support user controllable global clock multiplexing. table 1?18. clock input pin connecti vity to global clock networks clock resource clk(p) (pin) 0123456789101112131415 gclk0 v v gclk1 v v gclk2 v v gclk3 v v gclk4 v v gclk5 v v gclk6 v v gclk7 v v gclk8 v (1) v (1) gclk9 v (1) v (1) gclk10 v (1) v (1) gclk11 v (1) v (1) gclk12 v v gclk13 v v gclk14 v v gclk15 v v note to table 1?18 : (1) clock pins 8, 9, 10, and 11 are not available in stratix ii gx devices. therefore, these connections do not exist in stratix ii gx devices.
1?68 altera corporation stratix ii device handbook, volume 2 july 2009 clocking table 1?19 summarizes the connectivity be tween the clock pins and the regional clock networks. here, each cl ock pin can drive two regional clock networks, facilitating stitching of the clock networks to support the ability to drive two quadrants wi th the same clock or signal. table 1?19. clock input pin connectivity to regional clock networks (part 1 of 2) clock resource clk(p) (pin) 0123456789101112131415 rclk0 v rclk1 v rclk2 v rclk3 v rclk4 v rclk5 v rclk6 v rclk7 v rclk8 v rclk9 v rclk10 v rclk11 v rclk12 v rclk13 v rclk14 v rclk15 v rclk16 v (1) rclk17 v (1) rclk18 v (1) rclk19 v (1) rclk20 v (1) rclk21 v (1) rclk22 v (1)
altera corporation 1?69 july 2009 stratix ii device handbook, volume 2 plls in stratix ii and stratix ii gx devices clock input connections four clk pins drive each enhanced pll. you can use any of the pins for clock switchover inputs into the pll. the clk pins are the primary clock source for clock switchover, which is controlled in the quartus ii software. enhanced plls 5, 6, 11, an d 12 also have feedback input pins, as shown in table 1?20 . input clocks for fast plls 1, 2, 3, and 4 come from clk pins. a multiplexer chooses one of two possible clk pins to drive each pll. this multiplexer is not a clock switchover multiplexer and is only used for clock input connectivity. either an fpllclk input pin or a clk pin can drive the fast plls in the corners (7, 8, 9, and 10) when used for general-purpose applications. clk pins cannot drive these fast plls in high-speed differential i/o mode. rclk23 v (1) rclk24 v rclk25 v rclk26 v rclk27 v rclk28 v rclk29 v rclk30 v rclk31 v note to table 1?19 : (1) clock pins 8, 9, 10, and 11 are not available in stratix ii gx devices. therefore, these connections do not exist in stratix ii gx devices. table 1?19. clock input pin connectivity to regional clock networks (part 2 of 2) clock resource clk(p) (pin) 0123456789101112131415
1?70 altera corporation stratix ii device handbook, volume 2 july 2009 clocking tables 1?20 and 1?21 show which plls are availa ble in each stratix ii and stratix ii gx device, respectively, and which input clock pin drives which plls. table 1?20. stratix ii device plls and pll clock pin drivers (part 1 of 2) input pin all devices ep2s60 to ep2s180 devices fast plls enhanced plls fast plls enhanced plls 12345678 9101112 clk0 v v v (1) v (1) clk1 (2) v v v (1) v (1) clk2 v v v (1) v (1) clk3 (2) v v v (1) v (1) clk4 vv clk5 vv clk6 v v clk7 v v clk8 v v v (1) v (1) clk9 (2) vv v (1) v (1) clk10 v v v (1) v (1) clk11 (2) v v v (1) v (1) clk12 vv clk13 v v clk14 v v clk15 v v pll5_fb v pll6_fb v pll11_fb v pll12_fb v pll_ena v v v v v v v v v v v v fpll7clk (2) v fpll8clk (2) v fpll9clk (2) v
altera corporation 1?71 july 2009 stratix ii device handbook, volume 2 plls in stratix ii and stratix ii gx devices fpll10clk (2) v notes to table 1?20 : (1) clock connection is available. for more information about the maximum frequency, contact altera applications. (2) this is a dedicated high-speed clock input. for more information about the maximum frequency, contact altera applications. table 1?21. stratix ii gx device plls and pll clock pin drivers (part 1 of 2) input pin all devices ep2sgx60 to ep2sgx130 devices fast plls enhanced plls fast plls enhanced plls 123 (1) 4 (1) 56789 (1) 10 (1) 11 12 clk0 v v v (2) v (2) clk1 (2) v v v (2) v (2) clk2 v v v (2) v (2) clk3 (2) v v v (2) v (2) clk4 vv clk5 vv clk6 v v clk7 v v clk8 (4) clk9 (3) , (4) clk10 (4) clk11 (3) , (4) clk12 vv clk13 v v clk14 v v clk15 v v pll5_fb v pll6_fb v pll11_fb v table 1?20. stratix ii device plls and pll clock pin drivers (part 2 of 2) input pin all devices ep2s60 to ep2s180 devices fast plls enhanced plls fast plls enhanced plls 12345678 9101112
1?72 altera corporation stratix ii device handbook, volume 2 july 2009 clocking clk(n) pin connectivity to global clock networks in stratix ii and stratix ii gx devices, the clk(n) pins can also feed the global clock network. table 1?22 shows the clk(n) pin connectivity to global clock networks. pll12_fb v pll_ena v v v v v v v v fpll7clk (3) v fpll8clk (3) v fpll9clk (3) fpll10clk (3) notes to table 1?21 : (1) plls 3, 4, 9, and 10 are not available in stratix ii gx devices. (2) clock connection is available. for more information about the maximum frequency, contact altera applications. (3) this is a dedicated high-speed cloc k input. for more information about th e maximum frequency, contact altera applications. (4) input pins clk[11..8] are not available in stratix ii gx devices. table 1?21. stratix ii gx device plls and pll clock pin drivers (part 2 of 2) input pin all devices ep2sgx60 to ep2sgx130 devices fast plls enhanced plls fast plls enhanced plls 123 (1) 4 (1) 56789 (1) 10 (1) 11 12 table 1?22. clk(n) pin connectivity to global clock network clock resource clk(n) pin 4 5 6 7 12 13 14 15 gclk4 v gclk5 v gclk6 v gclk7 v gclk12 v gclk13 v gclk14 v gclk15 v
altera corporation 1?73 july 2009 stratix ii device handbook, volume 2 plls in stratix ii and stratix ii gx devices clock source control for enhanced plls the clock input multiplexer for enhanced plls is shown in figure 1?43 . this block allows selection of th e pll clock reference from several different sources. the clock source to an enhanced pll can come from any one of four clock input pins clk[3..0] , or from a logic-array clock, provided the logic array clock is driv en by an output from another pll, a pin-driven dedicated global or region al clock, or through a clock control block, provided the clock control bloc k is fed by an ou tput from another pll or a pin-driven dedicated global or regional clock. an internally generated global signal cannot dr ive the pll. the clock input pin connections to the respective enhanced plls are shown in table 1?20 above. the multiplexer select lines ar e set in the configuration file only. once programmed, this block cannot be changed without loading a new configuration file. the quartus ii software automatically sets the multiplexer select signals depending on the clock sources that a user selects in the design. figure 1?43. enhanced pll clock input multiplex logic note to figure 1?43 : (1) the input clock multiplexing is controll ed through a configuration file only and cannot be dynamically controlled in user mode. clock source control for fast plls each center fast pll has five clock input sources, four from clock input pins, and one from a logic array signal , provided the logic array signal is driven by an output from another p ll, a pin-driven dedicated global or regional clock, or through a clock control block, provided the clock control block is fed by an output from another pll or a pin-driven dedicated global or regional clock. an internally generated global signal cannot drive the pll. when using cl ock input pins as the clock source, you can perform manual clock switchov er among the input clock sources. (1) clk[3..0] core_inclk inclk1 inclk0 to the clock switchover block (1) 4 4
1?74 altera corporation stratix ii device handbook, volume 2 july 2009 clocking the clock input multipl exer control signals for performing clock switchover are from core signals. figure 1?44 shows the clock input multiplexer control circuit for a center fast pll. figure 1?44. center fast pll cloc k input multiplexer control note to figure 1?44 : (1) the input clock multiplexing is controll ed through a configuration file only and cannot be dynamically controlled in user mode. each corner fast pll has three clock input sources, one from a dedicated corner clock input pin, one from a ce nter clock input pin, and one from a logic array clock, provided the logic a rray signal is driven by an output from another pll, a pin-driven dedicated global or regional clock, or through a clock control block, provided the clock control block is fed by an output from another pl l or a pin-driven dedicated global or regional clock. an internally generated global signal cannot drive the pll. figure 1?45 shows a block diagram showin g the clock input multiplexer control circuit for a corner fast pll. only the corner fpllclk pin is fully compensated. figure 1?45. corner fast pll cloc k input multiplexer control note to figure 1?45 : (1) the input clock multiplexing is controll ed through a configuration file only and cannot be dynamically controlled in user mode. 4 inclk0 inclk1 to the clock switchover block (1) (1) clk[3..0] core_inclk core_inclk 4 inclk0 inclk1 to the clock switchover block (1) (1) fpllclk center clocks core_inclk core_inclk
altera corporation 1?75 july 2009 stratix ii device handbook, volume 2 plls in stratix ii and stratix ii gx devices delay compensatio n for fast plls each center fast pll can be fed by any one of four possible input clock pins. among the four clock inpu t signals, only two are fully compensated, i.e., the clock delay to th e fast pll matches the delay in the data input path when used in the lvds receiver mode. the two clock inputs that match the data input path are located right next to the fast pll. the two clock inputs that do not match the data input path are located next to the neighboring fast pll. figure 1?46 shows the above description for the left-side center fast pll pair. if the pll is used in non-lvds modes, then any of the four dedicated clock inputs can be used and are compensated. fast pll 1 and pll 2 can choose among clk[3..0] as the clock input source. however, for fast pll 1, only clk0 and clk1 have their delay matched to the data input path delay when used in the lvds receiver mode operation. the delay from clk2 or clk3 to fast pll 1 does not match the data input delay. for fast pll 2, only clk2 and clk3 have their delay matched to the data input path delay in lvds receiver mode operation. the delay from clk0 or clk1 to fast pll 2 does not match the data input delay. the same arrangement applies to the right side center fast pll pair. for corner fast plls, only the corner fpllclk pins are fully compensated. for lvds receiver operation, it is recommended to use the delay compensated clock pins only. figure 1?46. delay compensated clock input pins for center fast pll pair clk0 clk1 clk2 clk3 fast pll 1 fast pll 2
1?76 altera corporation stratix ii device handbook, volume 2 july 2009 clocking clock output connections enhanced plls have outputs for eigh t regional clock outputs and four global clock outputs. there is line sharing between clock pins, global and regional clock networks and all pll outputs. see tables 1?18 through 1?23 and figures 1?47 through 1?53 to validate your clocking scheme. the quartus ii software automatically maps to regional and global clocks to avoid any restrictions . enhanced plls 5, 6, 11, and 12 drive out to single-ended pins as shown in table 1?23 . you can connect each fast pl l 1, 2, 3, or 4 output ( c0 , c1 , c2 , and c3 ) to either a global or a regional clock. there is line sharing between clock pins, fpllclk pins, global and regional clock networks, and all pll outputs. the quartus ii software will automatically map to regional and global clocks to avoid any restrictions. figure 1?47 shows the clock input and ou tput connections from the enhanced plls. 1 ep2s15, ep2s30, and ep2sgx30 devices have only two enhanced plls (5, 6), but the co nnectivity from these two plls to the global or regional cloc k networks remains the same. the ep2s60 device in the 1,020- pin package contains 12 plls. ep2s60 devices in the 484-pin and 672-pin packages contain fast plls 1?4 and enhanced plls 5 and 6. ep2s90 devices in the 1020-pin and 1508-pin packages contain 12 plls. ep2s90 devices in th e 484-pin and 780-pin packages contain fast plls 1?4 and enhanced plls 5 and 6. ep2s130 devices in the 1020-pin and 1508-pin packages contain 12 plls. the ep2s130 device in the 780-pin package contains fast plls 1?4 and enha nced plls 5 and 6.
altera corporation 1?77 july 2009 stratix ii device handbook, volume 2 plls in stratix ii and stratix ii gx devices figure 1?47. stratix ii and stratix ii gx top and bottom enhanced plls, clock pin and logic array signal connectivity to global and regional clock networks notes (1) and (2) notes to figure 1?47 : (1) the redundant connection dots facilitate stitching of the clock networks to support the ability to drive two quadrants with the same clock. (2) the enhanced plls can also be driven through the global or regional clock networks. the global or regional clock input can be driven by an output from another pll, a pi n-driven dedicated global or regional clock, or through a clock control block, provided the clock control block is fed by an output from another pl l or a pin-driven dedicated global or regional clock. an internally generated global signal cannot drive the pll. g15 g14 g13 g12 rclk31 rclk30 rclk29 rclk28 rclk27 rclk26 rclk25 rclk24 g7 g6 g5 g4 rclk15 rclk14 rclk13 rclk12 rclk11 rclk10 rclk9 rclk8 pll 6 clk7 clk6 clk5 clk4 pll 12 pll 5 c0 c1 c2 c3 c4 c5 c0 c1 c2 c3 c4 c5 c0 c1 c2 c3 c4 c5 c0 c1 c2 c3 c4 c5 clk14 clk15 clk13 clk12 pll 11 pll11_fb pll5_out[2..0]p pll5_out[2..0]n pll11_out[2..0]p pll11_out[2..0]n pll12_out[2..0]p pll12_out[2..0]n pll6_out[2..0]p pll6_out[2..0]n pll5_fb pll12_fb pll6_fb global clocks regional clocks regional clocks
1?78 altera corporation stratix ii device handbook, volume 2 july 2009 clocking tables 1?23 and 1?24 show the global and regional clocks that the pll outputs drive. table 1?23. stratix ii global and regional cl ock outputs from plls (part 1 of 3) clock network pll number and type ep2s15 through ep2s30 devices ep2s60 through ep2s180 devices fast plls enhanced plls fast plls enhanced plls 123456789101112 gclk0 v v v v gclk1 v v v v gclk2 v v v v gclk3 v v v v gclk4 v v gclk5 vv gclk6 v v gclk7 v v gclk8 v v v v gclk9 vv vv gclk10 v v v v gclk11 v v v v gclk12 v v gclk13 vv gclk14 vv gclk15 vv rclk0 v v v rclk1 v v v rclk2 v v v rclk3 v v v rclk4 v v v rclk5 v v v rclk6 v v v rclk7 v v v rclk8 v v rclk9 v v
altera corporation 1?79 july 2009 stratix ii device handbook, volume 2 plls in stratix ii and stratix ii gx devices rclk10 v v rclk11 v v rclk12 v v rclk13 v v rclk14 v v rclk15 vv rclk16 vv v rclk17 v v v rclk18 v v v rclk19 v v v rclk20 v v v rclk21 vv v rclk22 v v v rclk23 v v v rclk24 v v rclk25 v v rclk26 v v rclk27 v v rclk28 v v rclk29 vv rclk30 v v rclk31 v v external clock output pll5_out[3..0]p/ n v pll6_out[3..0]p/ n v table 1?23. stratix ii global and regional cl ock outputs from plls (part 2 of 3) clock network pll number and type ep2s15 through ep2s30 devices ep2s60 through ep2s180 devices fast plls enhanced plls fast plls enhanced plls 123456789101112
1?80 altera corporation stratix ii device handbook, volume 2 july 2009 clocking pll11_out[3..0]p /n v pll12_out[3..0]p /n v table 1?24. stratix ii gx global and regional clock output s from plls (part 1 of 3) clock network pll number and type ep2sgx30 devices ep2sgx60 through ep2sgx130 devices notes (2) , (3) , and (4) fast plls enhanced plls fast plls enhanced plls 123 (1) 4 (1) 56789 (1) 10 (1) 11 12 gclk0 v v v v gclk1 v v v v gclk2 v v v v gclk3 v v v v gclk4 v v gclk5 vv gclk6 v v gclk7 v v gclk8 gclk9 gclk10 gclk11 gclk12 v v gclk13 vv gclk14 vv gclk15 vv table 1?23. stratix ii global and regional cl ock outputs from plls (part 3 of 3) clock network pll number and type ep2s15 through ep2s30 devices ep2s60 through ep2s180 devices fast plls enhanced plls fast plls enhanced plls 123456789101112
altera corporation 1?81 july 2009 stratix ii device handbook, volume 2 plls in stratix ii and stratix ii gx devices rclk0 v v v rclk1 v v v rclk2 v v v rclk3 v v v rclk4 v v v rclk5 v v v rclk6 v v v rclk7 v v v rclk8 v v rclk9 v v rclk10 v v rclk11 v v rclk12 v v rclk13 v v rclk14 v v rclk15 vv rclk16 rclk17 rclk18 rclk19 rclk20 rclk21 rclk22 rclk23 rclk24 v v rclk25 v v rclk26 v v rclk27 v v table 1?24. stratix ii gx global and regional clock output s from plls (part 2 of 3) clock network pll number and type ep2sgx30 devices ep2sgx60 through ep2sgx130 devices notes (2) , (3) , and (4) fast plls enhanced plls fast plls enhanced plls 123 (1) 4 (1) 56789 (1) 10 (1) 11 12
1?82 altera corporation stratix ii device handbook, volume 2 july 2009 clocking the fast plls also drive high-speed serdes clocks for differential i/o interfacing. for information about these fpllclk pins, contact altera applications. rclk28 v v rclk29 vv rclk30 v v rclk31 v v external clock output pll5_out[3..0]p /n v pll6_out[3..0]p /n v pll11_out[3..0] p/n v pll12_out[3..0] p/n v notes to table 1?24 : (1) plls 3, 4, 9, and 10 are not available in stratix ii gx devices. (2) the ep2s60 device in the 1,020-pin package contains 12 plls. ep2s60 devices in the 484-pin and 672-pin packages contain fast plls 1?4 and enhanced plls 5 and 6. (3) ep2s90 devices in the 1020-pin and 1508-pin packages cont ain 12 plls. ep2s90 devices in the 484-pin and 780-pin packages contain fast plls 1?4 and enhanced plls 5 and 6. (4) ep2s130 devices in the 1020-pin and 1508-pin packages contain 12 plls. the ep2s130 device in the 780-pin package contains fast plls 1?4 and enhanced plls 5 and 6. table 1?24. stratix ii gx global and regional clock output s from plls (part 3 of 3) clock network pll number and type ep2sgx30 devices ep2sgx60 through ep2sgx130 devices notes (2) , (3) , and (4) fast plls enhanced plls fast plls enhanced plls 123 (1) 4 (1) 56789 (1) 10 (1) 11 12
altera corporation 1?83 july 2009 stratix ii device handbook, volume 2 plls in stratix ii and stratix ii gx devices figures 1?48 through 1?51 show the global and re gional clock input and output connections from the stratix ii fast plls. figure 1?48. stratix ii cent er fast plls, clock pin and logic array signal connectivity to global and regional clock networks notes (1) and (2) notes to figure 1?48 : (1) the redundant connection do ts facilitate stitching of the clock networks to support the ability to drive two qua drants with the same clock. (2) the global or regional clocks in a fast pll's quadrant can drive the fast pll input. the global or regional clock input can be driven by an output from another pll, a pin-driven dedicated global or regional clock, or through a clock control block, provided the clock control block is fed by an output from another pll or a pin-driven dedicated global or regional clock. an internally generated global signal cannot drive the pll. c0 c1 c2 c3 fast pll 1 rck0 rck2 rck1 rck3 gck0 gck2 gck9 gck11 gck1 gck3 gck8 gck10 rck4 rck6 rck5 rck7 rck17 rck16 rck18 rck19 rck21 rck23 rck20 rck22 c0 c1 c2 c3 fast pll 2 logic array signal input to clock network clk0 clk1 clk2 clk3 c0 c1 c2 c3 fast pll 4 c0 c1 c2 c3 fast pll 3 clk11 clk10 clk9 clk8
1?84 altera corporation stratix ii device handbook, volume 2 july 2009 clocking figure 1?49. stratix ii gx center fas t plls, clock pin and logic array si gnal connectivity to global and regional clock networks notes (1) and (2) notes to figure 1?49 : (1) the redundant connection dots facilitate stitching of the clock networks to support the ability to drive two quadrants with the same clock. (2) the global or regional clocks in a fast pll's quadrant can drive the fast pll input. the global or regional clock input can be driven by an output from another pll, a pin-driven dedicated global or regional clock, or through a clock control block, provided the clock control block is fed by an output from another pl l or a pin-driven dedicated global or regional clock. an internally generated global signal cannot drive the pll. c0 c1 c2 c3 fast pll 1 rck0 rck2 rck1 rck3 gck0 gck2 gck1 gck3 rck4 rck6 rck5 rck7 c0 c1 c2 c3 fast pll 2 logic array signal input to clock network clk0 clk1 clk2 clk3
altera corporation 1?85 july 2009 stratix ii device handbook, volume 2 plls in stratix ii and stratix ii gx devices figure 1?50. stratix ii corner fast p lls, clock pin and logic array signal connectivity to global and regional clock networks note (1) note to figure 1?50 : (1) the corner fplls can also be driven throu gh the global or regional clock networks. the global or regional clock input can be driven by an output from another pll, a pin-driven dedicated global or regional clock, or through a clock control block, provided the clock control block is fed by an output from another pll or a pin-driven dedicated global or regional clock. an internally generated global signal cannot drive the pll. c0 c1 c2 c3 fast pll 7 rck0 rck2 rck1 rck3 gck0 gck2 gck9 gck11 gck1 gck3 gck8 gck10 rck4 rck6 rck5 rck7 rck17 rck16 rck18 rck19 rck21 rck23 rck20 rck22 c0 c1 c2 c3 fast pll 8 c0 c1 c2 c3 fast pll 10 c0 c1 c2 c3 fast pll 9 fpll7clk fpll 8clk fpll10cl k fpll 9cl k
1?86 altera corporation stratix ii device handbook, volume 2 july 2009 clock control block figure 1?51. stratix ii gx co rner fast plls, clock pin and logic array signal connectivity to global and regional clock networks note (1) note to figure 1?51 : (1) the corner fplls can also be driven throu gh the global or regional clock networks. the global or regional clock input can be driven by an output from another pll, a pin-driven dedicated global or regional clock, or through a clock control block, provided the clock control block is fed by an output from another pll or a pin-driven dedicated global or regional clock. an internally generated global signal cannot drive the pll. clock control block each global and regional clock ha s its own clock control block. the control block has two functions: clock source selection (dynamic selection for global clocks) clock power-down (dynamic clock enable or disable) c0 c1 c2 c3 fast pll 7 rck0 rck2 rck1 rck3 gck0 gck2 gck1 gck3 rck4 rck6 rck5 rck7 c0 c1 c2 c3 fast pll 8 fpll 7clk fpll 8clk
altera corporation 1?87 july 2009 stratix ii device handbook, volume 2 plls in stratix ii and stratix ii gx devices figures 1?52 and 1?53 show the global clock an d regional clock select blocks, respectively. figure 1?52. stratix ii global clock control block notes to figure 1?52 : (1) these clock select signals can only be dynamically controlled through internal logic when the device is operating in user mode. (2) these clock select signals can only be set through a configuration file and cannot be dynamically controlled during user-mode operation. clkp pins pll counter outputs internal logic static cloc k select (2) clkselect[1..0] this multiplexer supports user-controllable dynamic switching (1) 2 2 2 clkn pin enable/ disable gclk internal logic
1?88 altera corporation stratix ii device handbook, volume 2 july 2009 clock control block figure 1?53. regional clock control block notes to figure 1?53 : (1) these clock select signals can only be dynamically controlled through a configuration file and ca nnot be dynamically controlled during user-mode operation. (2) only the clk n pins on the top and bottom for th e device feed to regional clock select blocks. for the global clock select block, the clock source selection can be controlled either statically or dyna mically. you have the option to statically select the clock source in configuration file generated by the quartus ii software, or you can cont rol the selection dynamically by using internal logic to drive the multiplexer select inputs. when selecting statically, the clock source can be set to any of the inputs to the select multiplexer. when selecting the clock source dynamically, you can either select two pll outputs (such as clk0 or clk1 ), or a combination of clock pins or pll outputs. when using the altclkctrl megafunction to implement clock source (dynamics) selection, the inputs from the clock pins feed the inclock[0..1] ports of the multiplexer, while the pll outputs feed the inclock[2..3] ports. you can choose from among these inputs using the clkselect[1..0] signal. for the regional clock select block, the clock source selection can only be controlled statically using configuration bits. any of the inputs to the clock select multiplexer can be set as the clock source. the stratix ii and stratix ii gx clock networks can be disabled (powered down) by both static and dynamic approaches. when a clock net is powered down, all the logic fed by the clock net is in an off-state, thereby reducing the overall power consumption of the device. clkp pin pll counter outputs internal logic clkn pin enable/ disable rclk internal logic static clock select (1 ) 2 (2) (3)
altera corporation 1?89 july 2009 stratix ii device handbook, volume 2 plls in stratix ii and stratix ii gx devices the global and regional clock networks that are not used are automatically powered down through configuration bit settings in the configuration file (sram object file ( .sof ) or programmer object file ( .pof )) generated by the quartus ii software. the dynamic clock enable or disable feature allows the internal logic to control power up or down synchronously on gclk and rclk nets, including dual-regional clock regions. this function is independent of the pll and is applied directly on the clock network, as shown in figure 1?52 on page 1?87 and figure 1?53 on page 1?88 . the input clock sources and the clkena signals for the global and regional clock network multiplexers can be set through the quartus ii software using the altclkctrl megafunction. the dedicated external clock output pins can also be enabled or disabled using the altclkctrl megafunction. figure 1?54 shows the external pll output clock control block. figure 1?54. stratix ii ex ternal pll output clock control block notes to figure 1?54 : (1) these clock select signals can only be set through a configuration file and cannot be dynamically controlled during user mode operation. (2) the clock control block feed s to a multiplexer within the pll_out pin?s ioe. the pll_out pin is a dual-purpose pin. therefore, this multiplexer selects either an internal signal or the output of the clock control block. pll counter outputs (c[5..0]) enable/ disable pll_out pin internal logic static clock select ioe (1) static clock select (1) 6 internal logic (2)
1?90 altera corporation stratix ii device handbook, volume 2 july 2009 clock control block clkena signals figure 1?55 shows how clkena is implemented. figure 1?55. clkena implementation in stratix ii devices, the clkena signals are supported at the clock network level. this allows you to gate off the clock even when a pll is not being used. the clkena signals can also be used to control the dedicated external clocks from enhanced plls. upon re -enabling, the pll does not need a resynchronization or relo ck period unless the pll is using external feedback mode. figure 1?56 shows the waveform example for a clock output enable. clkena is synchronous to the falling edge of the counter output. figure 1?56. clkena signals note to figure 1?56 (1) the clkena signals can be used to enable or disable the global and regional networks or the pll_out pins. dq clkena clkena_out clk_out clk counter output clkena clkout
altera corporation 1?91 july 2009 stratix ii device handbook, volume 2 plls in stratix ii and stratix ii gx devices the pll can remain locked independent of the clkena signals since the loop-related counters are not affe cted. this feature is useful for applications that require a low power or sleep mode. upon re-enabling, the pll does not need a resynchr onization or relock period. the clkena signal can also disable clock output s if the system is not tolerant to frequency overshoot during resynchronization. conclusion stratix ii and stratix ii gx device enhanced and fast plls provide you with complete control of device cloc ks and system timing. these plls are capable of offering flexible system -level clock mana gement that was previously only available in discrete pll devices. the embedded plls meet and exceed the features offered by these high-end discrete devices, reducing the need for other ti ming devices in the system. referenced documents this chapter references the following documents: altpll megafunction user guide an 367: implementing pll reconf iguration in stratix ii devices configuring stratix ii an d stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook (or the stratix ii device handbook) dc & switching characteristics chapter in volume 1 of the stratix ii gx device handbook (or the stratix ii device handbook ) selectable i/o standards in stratix ii and stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook (or the stratix ii device handbook ) verification , volume 3 of the quartus ii development software handbook
1?92 altera corporation stratix ii device handbook, volume 2 july 2009 document revision history document revision history table 1?25 shows the revision history for this chapter. table 1?25. document revision history (part 1 of 2) date and document version changes made summary of changes july 2009, v4.6 updated ?manual override? , ?manual clock switchover? , and ?spread-spectrum clocking? sections. updated notes to figure 1?20 and figure 1?24 . both inclk0 and inclk1 must be running when the clkswitch signal goes high to initiate a manual clock switchover. updated the spread spectrum modulation frequency from (100 khz?500 khz) to (30 khz?150 khz). january 2008, v4.5 updated ?external clock outputs? section. ? added the ?referenced documents? section. ? minor text edits. ? no change for the stratix ii gx device handbook only: formerly chapter 6. the chapter number changed due to the addition of the stratix ii gx dynamic reconfiguration chapter. no content change. ? may 2007, v4.4 updated table 7?6. ? updated notes to: figure 7?7 figure 7?47 figure 7?48 figure 7?49 figure 7?50 figure 7?51 ? updated the ?clock source control for enhanced plls? sec- tion. ? updated the ?clock source control for fast plls? section. ? february 2007 v4.3 added ?document revision history? section to this chapter. ? deleted paragraph beginning with ?the stratix ii gx plls have the ability...? in the ?enhanced lock detect circuit? sec- tion. ? april 2006, v4.2 chapter updated as part of the stratix ii device handbook up- date. ? no change formerly chapter 5. chapter number change only due to chap- ter addition to section i in february 2006; no content change. ?
altera corporation 1?93 july 2009 stratix ii device handbook, volume 2 plls in stratix ii and stratix ii gx devices december 2005, v4.1 chapter updated as part of the stratix ii device handbook up- date. ? october 2005 v4.0 added chapter to the stratix ii gx device handbook .? table 1?25. document revision history (part 2 of 2) date and document version changes made summary of changes
1?94 altera corporation stratix ii device handbook, volume 2 july 2009 document revision history
altera corporation section ii?1 preliminary section ii. memory this section provides information on the trimatrix? embedded memory blocks internal to stratix ? ii devices and the supported external memory interfaces. this section contains the following chapters: chapter 2, trimatrix embedded me mory blocks in stratix ii and stratix ii gx devices chapter 3, external memory interfac es in stratix ii and stratix ii gx devices revision history refer to each chapter for its own specific revision history. for information on when each chapter was updated, refer to the chapter revision dates section, which appears in the full handbook.
section ii?2 altera corporation preliminary memory stratix ii device handbook, volume 2
altera corporation 2?1 january 2008 2. trimatrix embedded memory blocks in stratix ii and stratix ii gx devices introduction stratix ? ii and stratix ii gx devices feature the trimatrix? memory structure, consisting of three si zes of embedded ram blocks that efficiently address the memory needs of fpga designs. trimatrix memory includes 512-bit m 512 blocks, 4-kbit m4k blocks, and 512-kbit m-ram blocks, which are each configurable to support many features. trimatrix memory provides up to 9 megabits of ram at up to 550 mhz operation, and up to 16 tera bits per second of total memory bandwidth per device. this chapter describes trimatrix memory blocks, modes, and features. trimatrix memory overview the trimatrix architecture provid es complex memory functions for different applications in fpga desi gns. for example, m512 blocks are used for first-in first-out (fifo) functions and clock domain buffering where memory bandwidth is critical; m4k blocks are ideal for applications requiring medium-sized memory, such as asynchronous transfer mode (atm) cell processing ; and m-ram blocks are suitable for large buffering applications, such as internet protocol (ip) packet buffering and system cache. the trimatrix memory blocks support various memory configurations, including single-port, simple dual-p ort, true dual-port (also known as bidirectional dual-port), shift register, and read-only memory (rom) modes. the trimatrix memory archit ecture also includes advanced features and capabilities, such as pa rity-bit support, byte enable support, pack mode support, address clock en able support, mixed port width support, and mixed clock mode support. when applied to input registers, the asynchronous clear signal for the trimatrix embedded memory immediately clears the input registers. however, the output of the memory block does not show the effects until the next clock edge. when applied to output registers, the asynchronous clear signal clears the output registers and the effects are seen immediately. sii52002-4.5
2?2 altera corporation stratix ii device handbook, volume 2 january 2008 trimatrix memory overview table 2?1 summarizes the features supported by the three sizes of trimatrix memory. table 2?1. summary of trimatrix memory features feature m512 blocks m4k blocks m-ram blocks maximum performance 500 mhz 550 mhz 420 mhz total ram bits (including parity bits) 576 4,608 589,824 configurations 512 1 256 2 128 4 64 8 64 9 32 16 32 18 4k 1 2k 2 1k 4 512 8 512 9 256 16 256 18 128 32 128 36 64k 8 64k 9 32k 16 32k 18 16k 32 8k 64 8k 72 4k 128 4k 144 parity bits vvv byte enable vvv pack mode vv address clock enable vv single-port memory vvv simple dual-port memory vvv true dual-port memory vv embedded shift register vv rom vv fifo buffer vvv simple dual-port mixed width support vvv true dual-port mixed width support vv memory initialization file (. mif ) vv mixed-clock mode vvv power-up condition outputs cleared outputs cleared outputs unknown register clears output registers only output registers only output registers only same-port read-during-write new data available at positive clock edge new data available at positive clock edge new data available at positive clock edge mixed-port read-during-write outputs set to unknown or old data outputs set to unknown or old data unknown output
altera corporation 2?3 january 2008 stratix ii device handbook, volume 2 trimatrix embedded memory blocks in stratix ii and stratix ii gx devices tables 2?2 and 2?3 show the capacity and dis tribution of the trimatrix memory blocks in each stratix ii and stratix ii gx family member, respectively. parity bit support all trimatrix memory blocks (m51 2, m4k, and m-ram) support one parity bit for each byte. parity bits add to the amount of me mory in each random access memory (ram) block. for example, the m512 block has 576 bits, 64 of which are optionally used for parity bit storag e. the parity bit, along with logic implemented in adaptive logic modules (alms), implements parity checking for error detection to ensure data integrity. parity-size data words can also be used for other purp oses such as storing user-specified control bits. table 2?2. trimatrix memory capacity a nd distribution in stratix ii devices device m512 columns/blocks m4k columns/blocks m-ram blocks total ram bits ep2s15 4/104 3/78 0 419,328 ep2s30 6/202 4/144 1 1,369,728 ep2s60 7/329 5/255 2 2,544,192 ep2s90 8/488 6/408 4 4,520,448 ep2s130 9/699 7/609 6 6,747,840 ep2s180 11/930 8/768 9 9,383,040 table 2?3. trimatrix memory capacity and distribution in stratix ii gx devices device m512 columns/blocks m4k columns/blocks m-ram blocks total ram bits ep2sgx30c ep2sgx30d 6/202 4/144 1 1,369,728 ep2sgx60c ep2sgx60d ep2sgx60e 7/329 5/255 2 2,544,192 ep2sgx90e ep2sgx90f 8/488 6/408 4 4,520,448 ep2sgx130g 9/699 7/609 6 6,747,840
2?4 altera corporation stratix ii device handbook, volume 2 january 2008 trimatrix memory overview f refer to the using parity to detect memory errors white paper for more information on using the parity bit to detect memory errors. byte enable support all trimatrix memory blocks support byte enables that mask the input data so that only specific bytes, nibbl es, or bits of data are written. the unwritten bytes or bits retain the prev ious written value. the write enable ( wren ) signals, along with the byte enable ( byteena ) signals, control the ram blocks? write operations. the de fault value for the byte enable signals is high (enabled), in which case writing is controlled only by the write enable signals. there is no clear port to the byte enable registers. m512 blocks m512 blocks support byte enables for data widths of 16 and 18 bits only. for memory block configurations with widths of less than two bytes (16/18), the byte-enable feature is not supported. for memory configurations less than two bytes wi de, the write enable or clock enable signals can optionally be used to control the write operation. table 2?4 summarizes the byte selection. m4k blocks m4k blocks support byte enables for any combination of data widths of 16, 18, 32, and 36 bits only. for memory block configurations with widths of less than two bytes (16/18), the byte-enable feature is not supported. for memory configurations less than two bytes wide, the write enable or clock enable signals can optionally be used to control the write operation. table 2?4. byte enable for stratix ii and stratix ii gx m512 blocks note (1) byteena[1..0] data 16 data 18 [0] = 1 [7..0] [8..0] [1] = 1 [15..8] [17..9] note to ta b l e 2 ? 4 : (1) any combination of byte enables is possible.
altera corporation 2?5 january 2008 stratix ii device handbook, volume 2 trimatrix embedded memory blocks in stratix ii and stratix ii gx devices table 2?5 summarizes the byte selection. m-ram blocks m-ram blocks support byte enables fo r any combination of data widths of 16, 18, 32, 36, 64, and 72 bits. fo r memory block configurations with widths of less than two bytes (16/ 18), the byte-enable feature is not supported. in the 128 and 144 simple dual-port modes, the two sets of byte enable signals ( byteena_a and byteena_b ) combine to form the necessary 16 byte enables. in 128 an d 144 modes, byte enables are only supported when using single clock mode. however, the quartus ii software can implement byte enables in other clocking modes for 128 or 144 widths but will use twice as many m-ram resources. if clock enables are used in 128 or 144 mode, you must use the same clock enable setting for both the a and b ports. table 2?6 summarizes the byte selection for m-ram blocks. table 2?5. byte enable for stratix ii and stratix ii gx m4k blocks note (1) byteena [3..0] data 16 data 18 data 32 data 36 [0] = 1 [7..0] [8..0] [7..0] [8..0] [1] = 1 [15..8] [17..9] [15..8] [17..9] [2] = 1 - - [23..16] [26..18] [3] = 1 - - [31..24] [35..27] note to ta b l e 2 ? 5 : (1) any combination of byte enables is possible. table 2?6. byte enable for stratix ii and stratix ii gx m-ram blocks note (1) byteena data 16 data 18 data 32 data 36 data 64 data 72 [0] = 1 [7..0] [8..0] [7..0] [8..0] [7..0] [8..0] [1] = 1 [15..8] [17..9] [15..8] [17..9] [15..8] [17..9] [2] = 1 - - [23..16] [26..18] [23..16] [26..18] [3] = 1 - - [31..24] [35..27] [31..24] [35..27] [4] = 1 - - - - [39..32] [44..36] [5] = 1 - - - - [47..40] [53..45] [6] = 1 - - - - [55..48] [62..54] [7] = 1 - - - - [63..56] [71..63] note to ta b l e 2 ? 6 : (1) any combination of byte enables is possible.
2?6 altera corporation stratix ii device handbook, volume 2 january 2008 trimatrix memory overview table 2?7 summarizes the byte selection for 144 mode. byte enable functional waveform figure 2?1 shows how the write enable ( wren ) and byte enable ( byteena ) signals control the operations of the ram. when a byte enable bit is de-asserted during a write cycle, the corresponding data byte output appe ars as a ?don't care? or unknown value. when a byte enable bit is asserted during a write cycle, the corresponding data byte output will be the newly written data. table 2?7. stratix ii and stratix ii gx m- ram combined byte selection for 144 mode note (1) byteena data 128 data 144 [0] = 1 [7..0] [8..0] [1] = 1 [15..8] [17..9] [2] = 1 [23..16] [26..18] [3] = 1 [31..24] [35..27] [4] = 1 [39..32] [44..36] [5] = 1 [47..40] [53..45] [6] = 1 [55..48] [62..54] [7] = 1 [63..56] [71..63] [8] = 1 [71..64] [80..72] [9] = 1 [79..72] [89..73] [10] = 1 [87..80] [98..90] [11] = 1 [95..88] [107..99] [12] = 1 [103..96] [116..108] [13] = 1 [111..104] [125..117] [14] = 1 [119..112] [134..126] [15] = 1 [127..120] [143..135] note to ta b l e 2 ? 7 : (1) any combination of byte enables is possible.
altera corporation 2?7 january 2008 stratix ii device handbook, volume 2 trimatrix embedded memory blocks in stratix ii and stratix ii gx devices figure 2?1. stratix ii and st ratix ii gx byte enable functional waveform 1 for more information about mram and byte enable for the stratix ii device family, refer to the stratix ii fpga errata sheet at the altera web site at www.altera.com . pack mode support stratix ii and stratix ii gx m4k and m-ram memory blocks support pack mode. in m4k and m-ram me mory blocks, two single-port memory blocks can be implemented in a single block under the following conditions: each of the two independent block si zes is equal to or less than half of the m4k or m-ram block size. each of the single-port memory blocks is configured in single-clock mode. thus, each of the single-port memory blocks access up to half of the m4k or m-ram memory resources such as clock, clock enables, and asynchronous clear signals. refer to ?single-port mode? on page 2?10 and ?single-clock mode? on page 2?28 for more information. inclock wren address data q (asynch) byteena xxxx abcd xxxx xx 10 01 11 xx an a0 a1 a2 a0 a1 a2 abcd ffff ffff abff ffff ffcd contents at a0 contents at a1 contents at a2 doutn abxx xxcd abcd abff ffcd abcd
2?8 altera corporation stratix ii device handbook, volume 2 january 2008 trimatrix memory overview address clock enable support stratix ii and stratix ii gx m4k and m-ram memory blocks support address clock enable, which is used to hold the previous address value for as long as the signal is enabled. when the memory blocks are configured in dual-port mode, each port has its own independent address clock enable. figure 2?2 shows an address clock enable block diagram. placed in the address register, the address signal ou tput by the address register is fed back to the input of the register via a multiplexer. the multiplexer output is selected by the address clock enable ( addressstall ) signal. address latching is enabled when the addressstall signal turns high. the output of the address register is th en continuously fed into the input of the register; therefore, the address value can be held until the addressstall signal turns low. figure 2?2. stratix ii and st ratix ii gx address clock enable block diagram address clock enable is typically used for cache memory applications, which require one port for read and another port for write. the default value for the address clock enable signals is low (disabled). figures 2?3 and 2?4 show the address clock enable waveform during the read and write cycles, respectively. address[0] address[n] addressstall clock 1 0 address[0] register address[n] register address[n] address[0] 1 0
altera corporation 2?9 january 2008 stratix ii device handbook, volume 2 trimatrix embedded memory blocks in stratix ii and stratix ii gx devices figure 2?3. stratix ii and stratix ii gx address clock enable during read cycle waveform figure 2?4. stratix ii and st ratix ii gx address clock enable during write cycle waveform memory modes stratix ii and stratix ii gx trimatrix memory blocks include input registers that synchronize writes, and output registers to pipeline data to improve system performance. all tr imatrix memory blocks are fully synchronous, meaning that all inputs are registered, but outputs can be either registered or unregistered. inclock rden rdaddress q (synch) a0 a1 a2 a3 a4 a5 a6 q (asynch) an a0 a4 a5 latched address (inside memory) dout0 dout1 dout1 dout4 dout1 dout4 dout5 addressstall a1 doutn-1 dout1 doutn doutn dout1 dout0 dout1 inclock wren wraddress a0 a1 a2 a3 a4 a5 a6 an a0 a4 a5 latched address (inside memory) addressstall a1 data 00 01 02 03 04 05 06 contents at a0 contents at a1 contents at a2 contents at a3 contents at a4 contents at a5 xx 04 xx 00 03 01 xx 02 xx xx xx 05
2?10 altera corporation stratix ii device handbook, volume 2 january 2008 memory modes 1 trimatrix memory does not support asynchronous memory (unregistered inputs). depending on which trimatrix memory block you use, the memory has various modes, including: single-port simple dual-port true dual-port (bidirectional dual-port) shift-register rom fifo 1 violating the setup or hold time on the memory block address registers could corrupt memory contents. this applies to both read and write operations. single-port mode all trimatrix memory blocks support the single-port mode that supports non-simultaneous read and write operations. figure 2?5 shows the single-port memory configur ation for trimatrix memory. figure 2?5. single-port memory note (1) note to figure 2?5 : (1) two single-port memory blocks can be implemented in a si ngle m4k or m-ram block. m4k and m-ram memory blocks can al so be halved and used for two independent single-port ram blocks. the altera ? quartus ? ii software automatically uses this single-port memory pa cking when running low on memory resources. to force two single-port memories into one m4k or m-ram block, first ensure that each of the two independent ram blocks is equal to or less than half the size of the m4k or m-ram block. secondly, assign both single-port rams to the same m4k or m-ram block. data[ ] address[ ] wren byteena[] addressstall inclock inclocken outaclr outclocken outclock q[]
altera corporation 2?11 january 2008 stratix ii device handbook, volume 2 trimatrix embedded memory blocks in stratix ii and stratix ii gx devices in single-port ram configuration, the outputs can only be in read-during-write mode, which means that during the write operation, data written to the ram flows thro ugh to the ram outputs. when the output registers are bypassed, the new da ta is available on the rising edge of the same clock cycle on wh ich it was written. refer to ?read-during- write operation at the same address? on page 2?33 for more information about read-during-write mode. table 2?8 shows the port width configurations for trimatrix blocks in single-port mode. figure 2?6 shows timing waveforms for read and write operations in single-port mode. figure 2?6. stratix ii and st ratix ii gx single-port timing waveforms note to figure 2?6 : (1) the crosses in the data waveform during read mean ?don?t care.? table 2?8. stratix ii and stratix ii gx po rt width configur ations for m512, m4k, and m-ram blocks (single-port mode) m512 blocks m4k blocks m-ram blocks port width configurations 512 1 256 2 128 4 64 8 64 9 32 16 32 18 4k 1 2k 2 1k 4 512 8 512 9 256 16 256 18 128 32 128 36 64k 8 64k 9 32k 16 32k 18 16k 32 16k 36 8k 64 8k 72 4k 128 4k 144 inclock wren address q (synch) an-1 an a0 a1 a2 a3 a4 a5 a6 q (asynch) din-1 din din4 din5 din6 data din-2 din-1 din dout0 dout1 dout2 dout3 din4 din-1 din dout0 dout1 dout2 dout3 din4 din5 (1)
2?12 altera corporation stratix ii device handbook, volume 2 january 2008 memory modes simple dual-port mode all trimatrix memory blocks support simple dual-port mode which supports a simultaneous read and write operation. figure 2?7 shows the simple dual-port memory configuration for trimatrix memory. figure 2?7. stratix ii and stratix ii gx simple dual-port memory note (1) note to figure 2?7 : (1) simple dual-port ram supports input/output clock mode in addition to the read/write clock mode shown. data[ ] wraddress[ ] wren byteena[] wr_addressstall wrclock wrclocken rdaddress[ ] rden q[ ] rd_addressstall rdclock rdclocken rd_aclr
altera corporation 2?13 january 2008 stratix ii device handbook, volume 2 trimatrix embedded memory blocks in stratix ii and stratix ii gx devices trimatrix memory supports mixed-width configurations, allowing different read and write port widths. tables 2?9 through 2?11 show the mixed width configurations for th e m512, m4k, and m-ram blocks, respectively. table 2?9. stratix ii and stratix ii gx m512 block mixed-width configurations (sim ple dual-port mode) read port write port 512 1 256 2 128 4 64 8 32 16 64 9 32 18 512 1 vvvvv 256 2 vvvvv 128 4 vvvvv 64 8 vvvvv 32 16 vvvvv 64 9 vv 32 18 vv table 2?10. stratix ii and stra tix ii gx m4k block mi xed-width configurations (simple dual-port mode) read port write port 4k 1 2k 2 1k 4 512 8 256 16 128 32 512 9 256 18 128 36 4k 1 vvvvvv 2k 2 vvvvvv 1k 4 vvvvvv 512 8 vvvvvv 256 16 vvvvvv 128 32 vvvvvv 512 9 vvv 256 18 vvv 128 36 vvv
2?14 altera corporation stratix ii device handbook, volume 2 january 2008 memory modes in simple dual-port mode, m512 and m4k blocks have one write enable and one read enable signal. howeve r, m-ram blocks contain only a write-enable signal, which is held high to perform a write operation. m-ram blocks are always enabled for read operations. if the read address and the write address select the same address location during a write operation, m-ram bl ock output is unknown. trimatrix memory blocks do not support a clear port on the write enable and read enable registers. when th e read enable is deactivated, the current data is retained at the output ports. if the read enable is activated during a write operation with the sa me address location selected, the simple dual-port ram output is either unknown or can be set to output the old data stored at the memory address. refer to ?read-during-write operation at the same address? on page 2?33 for more information. figure 2?8 shows timing waveforms for read and write operations in simple dual-port mode. table 2?11. stratix ii and stratix ii gx m-ra m block mixed-width configurations (sim ple dual-port mode) read port write port 64k 9 32k 18 18k 36 8k 72 4k 144 64k 9 vvv v 32k 18 vvv v 18k 36 vvv v 8k 72 vvv v 4k 144 v
altera corporation 2?15 january 2008 stratix ii device handbook, volume 2 trimatrix embedded memory blocks in stratix ii and stratix ii gx devices figure 2?8. stratix ii and stra tix ii gx simple dual -port timing waveforms notes to figure 2?8 : (1) the crosses in the data waveform during read mean ?don?t care.? (2) the read enable rden signal is not available in m-ram blocks. the m-ram block in simple dual-port mode always reads out the data stored at the current read address location. true dual-port mode stratix ii and stratix ii gx m4k and m-ram memory blocks support the true dual-port mode. true dual-port mode supports any combination of two-port operations: two reads, two wr ites, or one read and one write at two different clock frequencies. figure 2?9 shows stratix ii and stratix ii gx true dual-port memory configuration. figure 2?9. stratix ii and stratix ii gx true dual-port memory note (1) note to figure 2?9 : (1) true dual-port memory supports input/output clock mode in addition to the independent clock mode shown. wrclock wren wraddress q (synch) rdclock an-1 an a0 a1 a2 a3 a4 a5 a6 q (asynch) rden (2) rdaddress bn b0 b1 b2 b3 doutn-2 doutn-1 doutn doutn-1 doutn dout0 dout0 din-1 din din4 din5 din6 data (1) data_a[ ] address_a[ ] wren_a byteena_a[] addressstall_a clock_a enable_a aclr_a q_a[] data_b[ ] address_b[] wren_b byteena_b[] addressstall_b clock_b enable_b aclr_b q_b[]
2?16 altera corporation stratix ii device handbook, volume 2 january 2008 memory modes the widest bit configuration of the m4k and m-ram blocks in true dual- port mode is as follows: 256 16-bit (18-bit wi th parity) (m4k) 8k 64-bit (72-bit wi th parity) (m-ram) the 128 32-bit (36-bit with parity) configuration of the m4k block and the 4k 128-bit (144-bit with parity) configuration of the m-ram block are unavailable because the number of output drivers is equivalent to the maximum bit width of the respective memory block. because true dual-port ram has outputs on two port s, the maximum width of the true dual-port ram equals half of the total number of output drivers. table 2?12 lists the possible m4k block mixed-port width configurations. table 2?13 lists the possible m-ram block mixed-port width configurations. table 2?12. stratix ii and stra tix ii gx m4k block mixed-port wi dth configurations (true dual-port) read port write port 4k 1 2k 2 1k 4 512 8 256 16 512 9 256 18 4k 1 vvvvv 2k 2 vvvvv 1k 4 vvvvv 512 8 vvvvv 256 16 vvvvv 512 9 vv 256 18 vv table 2?13. stratix ii and st ratix ii gx m-ram bl ock mixed-port width configurations (true dual-port) read port write port 64k 9 32k 18 18k 36 8k 72 64k 9 v vvv 32k 18 v vvv 18k 36 v vvv 8k 72 v vvv
altera corporation 2?17 january 2008 stratix ii device handbook, volume 2 trimatrix embedded memory blocks in stratix ii and stratix ii gx devices in true dual-port configuration, the ram outputs can only be configured for read-during-write mode. this means that during write operation, data being written to the a or b port of the ram flows through to the a or b outputs, respectively. when th e output registers are bypassed, the new data is available on the rising ed ge of the same clock cycle on which it was written. refer to ?read-during-write operation at the same address? on page 2?33 for waveforms and information on mixed-port read-during-write mode. potential write contentions must be resolved external to the ram because writing to the same address location at both ports results in unknown data storage at that location. for a valid write operation to the same address of the m-ram block, the rising edge of the write clock for port a must occur following the maximum writ e cycle time interval after the rising edge of the write clock for port b. data is written on the rising edge of the write clock for the m-ram block. because data is written into the m512 and m4k blocks at the falling edge of the write clock, the rising edge of the write clock for port a should occur following half of the maximum write cycle time interval after the falling edge of the write clock for port b. if this timing is not met, the data stored in that particular address will be invalid. f refer to the stratix ii device family data sheet (volume 1) of the stratix ii device handbook or the stratix ii gx device family data sheet (volume 1) of the stratix ii gx device handbook for the maximum synchronous write cycle time.
2?18 altera corporation stratix ii device handbook, volume 2 january 2008 memory modes figure 2?10 shows true dual-port timi ng waveforms for the write operation at port a and the read operation at port b. figure 2?10. stratix ii and stratix ii gx true dual-port timing waveforms note to figure 2?10 : (1) the crosses in the data_a waveform during write mean ?don?t care.? shift-register mode all stratix ii memory blocks su pport the shift register mode. embedded memory block configurations can implement shift registers for digital signal processing (dsp) applications, such as finite impulse response (fir) filters, pseudo-ran dom number generators, multi-channel filtering, and auto-correlation and cr oss-correlation functions. these and other dsp applications require local data storage, traditionally implemented with standard flip-flops that quickly exhaust many logic cells for large shift registers. a more efficient alternative is to use embedded memory as a shift-register block, which saves logic cell and routing resources. the size of a (w m n) shift regist er is determined by the input data width (w), the length of the taps (m ), and the number of taps (n), and must be less than or equal to the maxi mum number of memory bits in the respective block: 576 bits for the m512 block, 4,608 bits for the m4k block, and 589,824 bits for the mram block. in addition, the size of w n must be less than or equal to the maximu m width of the respective block: 18 clk_a wren_a address_a q_a (synch) q_b (synch) clk_b an-1 an a0 a1 a2 a3 a4 a5 a6 q_b (asynch) wren_b address_b bn b0 b1 b2 b3 doutn-2 doutn-1 doutn doutn-1 doutn dout0 dout0 q_a (asynch) din-1 din din4 din5 din6 data_a (1) din-2 din-1 din dout0 dout1 dout2 dout3 din4 din-1 din dout0 dout1 dout2 dout3 din4 din5 dout1 dout2 dout1
altera corporation 2?19 january 2008 stratix ii device handbook, volume 2 trimatrix embedded memory blocks in stratix ii and stratix ii gx devices bits for the m512 block, 36 bits for the m4k block, and 144 bits for the mram block. if a larger shift register is required, the memory blocks can be cascaded. in m512 and m4k blocks, data is writte n into each address location at the falling edge of the clock and read from the address at the rising edge of the clock. the shift-register mode logic automatically controls the positive and negative edge clocking to shift the da ta in one clock cycle. the mram block performs reads an d writes on the rising edge. figure 2?11 shows the trimatrix memory block in the shift-register mode. figure 2?11. stratix ii and stratix ii gx shift-register memory configuration w w m n shift register m-bit shift register m-bit shift register m-bit shift register m-bit shift register w w w w w w w n number of taps
2?20 altera corporation stratix ii device handbook, volume 2 january 2008 clock modes rom mode m512 and m4k memory blocks support rom mode. a memory initialization file ( .mif ) initializes the rom conten ts of these blocks. the address lines of the rom are registered. the outputs can be registered or unregistered. the rom read operation is identical to the read operation in the single-port ram configuration. fifo buffers mode trimatrix memory blocks support th e fifo mode. m512 memory blocks are ideal for designs with many sh allow fifo buffers. all memory configurations have synchronous in puts; however, the fifo buffer outputs are always combinational. si multaneous read and write from an empty fifo buffer is not supported. f refer to the single- and dual-clock fifo megafunctions user guide and fifo partitioner megafunction user guide for more information on fifo buffers. clock modes depending on which trimatrix memory mode is selected, the following clock modes are available: independent input/output read/write single-clock table 2?14 shows these clock modes support ed by all trimatrix blocks when configured as respective memory modes. table 2?14. stratix ii and st ratix ii gx trimatri x memory clock modes clocking modes true dual-port mode simple dual-port mode single-port mode independent v input/output vvv read/write v single clock vvv
altera corporation 2?21 january 2008 stratix ii device handbook, volume 2 trimatrix embedded memory blocks in stratix ii and stratix ii gx devices independent clock mode the trimatrix memory blocks can implement independent clock mode for true dual-port memory. in this mo de, a separate clock is available for each port (a and b). clock a controls all registers on the port a side, while clock b controls all registers on the port b side. each port also supports independent clock enables for port a and b registers. asynchronous clear signals for the registers, however, are supported.
2?22 altera corporation stratix ii device handbook, volume 2 january 2008 clock modes figure 2?12 shows a trimatrix memory block in independent clock mode. figure 2?12. stratix ii and stra tix ii gx trimatrix me mory block in independent clock mode note (1) note to figure 2?12 : (1) violating the setup or hold time on the memory block address registers could corrupt the memory contents. this appl ies to both read and write operations. 6 d ena q d ena q d ena q data_a[ ] address_a[ ] memory block 256 16 (2) 512 8 1,024 4 2,04 8 2 4,096 1 data in address a write/read enable data out data in address b write/read enable data out enable_a clock_a d ena q wren_a 6 lab row clocks q_a[ ] 6 data_b[ ] address_b[ ] q_b[ ] ena ab ena d q ena d q ena d q d q d ena q byteena_a[ ] byte enable a byte enable b byteena_b[ ] ena d q write pulse generator write pulse generator wren_b enable_b clock_b addressstall_a address clock enable a address clock addressstall_b enable b
altera corporation 2?23 january 2008 stratix ii device handbook, volume 2 trimatrix embedded memory blocks in stratix ii and stratix ii gx devices input/output clock mode stratix ii and stratix ii gx trimatrix memory blocks can implement input/output clock mode for true and simple dual-port memory. on each of the two ports, a and b, one clock controls all registers for the following inputs into the memory bl ock: data input, write enable, and address. the other clock controls the blocks? data output registers. each memory block port also supports independent cl ock enables for input and output registers. asynchronous clear signals for the registers, however, are not supported. figures 2?13 through 2?15 show the memory block in input/output clock mode for true dual-port, simple dual-port, and single-port modes, respectively.
2?24 altera corporation stratix ii device handbook, volume 2 january 2008 clock modes figure 2?13. stratix ii and stratix ii gx input/output clock mode in true dual-port mode note (1) note to figure 2?13 : (1) violating the setup or hold time on the memory block address registers could corrupt the memory contents. this appl ies to both read and write operations. 6 d ena q d ena q d ena q data_a[ ] address_a[ ] memory block 256 16 (2) 512 8 1,024 4 2,04 8 2 4,096 1 data in address a write/read enable data out data in address b write/read enable data out inclocken inclock d ena q wren_a 6 lab row clocks q_a[ ] 6 data_b[ ] address_b[ ] q_b[ ] ena ab ena d q ena d q ena d q d q d ena q byteena_a[ ] byte enable a byte enable b byteena_b[ ] ena d q write pulse generator write pulse generator wren_b outclocken outclock addressstall_a address clock enable a address clock addressstall_b enable b
altera corporation 2?25 january 2008 stratix ii device handbook, volume 2 trimatrix embedded memory blocks in stratix ii and stratix ii gx devices figure 2?14. stratix ii and stratix ii gx input/o utput clock mode in simple dual-port mode note (1) notes to figure 2?14 : (1) violating the setup or hold time on the memory block address registers could corrupt the memory contents. this applies to both read and write operations. (2) the read enable rden signal is not available in the m-ram block. an m-ram block in simple dual-port mode is always reading out the data stored at the current read address location. (3) refer to the stratix ii device family data sheet (volume 1) of the stratix ii device handbook or the stratix ii gx device family data sheet (volume 1) of the stratix ii gx device handbook for more information on the multitrack? interconnect. 6 d ena q d ena q d ena q d ena q d ena q data[ ] d ena q wraddress[ ] rdaddress[ ] memory block 256 16 512 8 1,024 4 2,048 2 4,096 1 data in read address write address write enable read enable data out outclocken inclocken inclock outclock wren rden 6 lab row clocks to multitrack interconnect (3) d ena q byteena[ ] byte enable write pulse generator (2) rd_addressstall wr_addressstall read address clock enable write address clock enable
2?26 altera corporation stratix ii device handbook, volume 2 january 2008 clock modes figure 2?15. stratix ii and stratix ii gx inpu t/output clock mode in single-port mode note (1) notes to figure 2?15 : (1) violating the setup or hold time on the memory block address registers could corrupt the memory contents. this applies to both read and write operations. (2) refer to the stratix ii device family data sheet (volume 1) of the stratix ii device handbook or the stratix ii gx device family data sheet (volume 1) of the stratix ii gx device handbook for more information on the multitrack interconnect. read/write clock mode stratix ii and stratix ii gx trimatri x memory blocks can implement read/write clock mode for simple dual-port memory. this mode uses up to two clocks. the write clock controls the bloc ks? data inputs, write address, and write enable signals. the read clock controls the data output, read address, and read enable si gnals. the memory blocks support independent clock enables for each clock for the read- and write-side registers. asynchronous clear signals for the registers, however, are not supported. figure 2?16 shows a memory block in read/write clock mode. 6 d ena q d ena q d ena q d ena q data[ ] address[ ] memory block 256 16 512 8 1,024 4 2,048 2 4,096 1 data in address write enable data out outclocken inclocken inclock outclock wren 6 lab row clocks to multitrack interconnect (2) d ena q byteena[ ] byte enable write pulse generator addressstall address clock enable
altera corporation 2?27 january 2008 stratix ii device handbook, volume 2 trimatrix embedded memory blocks in stratix ii and stratix ii gx devices figure 2?16. stratix ii and strati x ii gx read/write clock mode note (1) notes to figure 2?16 : (1) violating the setup or hold time on the memory block address registers could corrupt the memory contents. this applies to both read and write operations. (2) the read enable rden signal is not available in the m-ram block. an m-ram block in simple dual-port mode is always reading the data stored at the current read address location. (3) refer to the stratix ii device family data sheet (volume 1) of the stratix ii device handbook or the stratix ii gx device family data sheet (volume 1) of the stratix ii gx device handbook for more information on the multitrack interconnect. 6 d ena q d ena q d ena q d ena q d ena q data[ ] d ena q wraddress[ ] rdaddress[ ] memory block 256 16 512 8 1,024 4 2,048 2 4,096 1 data in read address write address write enable read enable data out rdclocken wrclocken wrclock rdclock wren rden 6 lab row clocks to multitrack interconnect (3 ) d ena q byteena[ ] byte enable write pulse generator (2) rd_addressstall wr_addressstall read address clock enable write address clock enable
2?28 altera corporation stratix ii device handbook, volume 2 january 2008 clock modes single-clock mode stratix ii and stratix ii gx trimat rix memory blocks implement single-clock mode for true dual-port, simple dual-port, and single-port memory. in this mode, a single clock, together with clock enable, is used to control all registers of the memory block. asynchronous clear signals for the registers, however, are not supported. figures 2?17 through 2?19 show the memory block in single-clock mode for true dual-port, simple dual-port, and single-port modes, respectively.
altera corporation 2?29 january 2008 stratix ii device handbook, volume 2 trimatrix embedded memory blocks in stratix ii and stratix ii gx devices figure 2?17. stratix ii and stratix ii gx si ngle-clock mode in true dual-port mode note (1) note to figure 2?17 : (1) violating the setup or hold time on the memory block address registers could corrupt the memory contents. this appl ies to both read and write operations. 6 d ena q d ena q d ena q data_a[ ] address_a[ ] memory block 256 16 (2) 512 8 1,024 4 2,04 8 2 4,096 1 data in address a write/read enable data out data in address b write/read enable data out enable clock d ena q wren_a 6 lab row clocks q_a[ ] 6 data_b[ ] address_b[ ] q_b[ ] ena ab ena d q ena d q ena d q d q d ena q byteena_a[ ] byte enable a byte enable b byteena_b[ ] ena d q write pulse generator write pulse generator wren_b a ddressstall_a address clock enable a address clock addressstall_b enable b
2?30 altera corporation stratix ii device handbook, volume 2 january 2008 clock modes figure 2?18. stratix ii andstratix ii gx single-c lock mode in simple dual-port mode note (1) notes to figure 2?18 : (1) violating the setup or hold time on the memory block address registers could corrupt the memory contents. this applies to both read and write operations. (2) the read enable rden signal is not available in the m-ram block. an m-ram block in simple dual-port mode is always reading the data stored at the current read address location. (3) refer to the stratix ii device family data sheet (volume 1) of the stratix ii device handbook or the stratix ii gx device family data sheet (volume 1) of the stratix ii gx device handbook for more information on the multitrack interconnect. 6 d ena q d ena q d ena q d ena q d ena q data[ ] d ena q wraddress[ ] rdaddress[ ] memory block 256 16 512 8 1,024 4 2,048 2 4,096 1 data in read address write address write enable read enable data out enable clock wren rden 6 lab row clocks to multitrack interconnect (3) d ena q byteena[ ] byte enable write pulse generator (2) rd_addressstall wr_addressstall read address clock enable write address clock enable
altera corporation 2?31 january 2008 stratix ii device handbook, volume 2 trimatrix embedded memory blocks in stratix ii and stratix ii gx devices figure 2?19. stratix ii and stratix ii gx si ngle-clock mode in single-port mode note (1) notes to figure 2?19 : (1) violating the setup or hold time on the memory block address registers could corrupt the memory contents. this applies to both read and write operations. (2) refer to the stratix ii device family data sheet (volume 1) of the stratix ii device handbook or the stratix ii gx device family data sheet (volume 1) of the stratix ii gx device handbook for more information on the multitrack interconnect. designing with trimatrix memory when instantiating trimatrix memory, it is important to understand the features that set it apart from othe r memory architectures. the following sections describe the unique attributes and functionality of trimatrix memory. selecting trimatri x memory blocks the quartus ii software automatically partitions user-defined memory into embedded memory blocks using the most efficient size combinations. the memory can also be manually assigned to a specific block size or a mixture of block sizes. table 2?1 on page 2?2 is a guide for selecting a trimatrix memory block size based on supported features. 6 d ena q d ena q d ena q d ena q data[ ] address[ ] memory block 256 16 512 8 1,024 4 2,048 2 4,096 1 data in address write enable data out enable clock wren 6 lab row clocks to multitrack interconnect (2) d ena q byteena[ ] byte enable write pulse generator addressstall address clock enable
2?32 altera corporation stratix ii device handbook, volume 2 january 2008 designing with trimatrix memory f refer to an 207: trimatrix memory selection using the quartus ii software for more information on selectin g the appropriate memory block. synchronous and pseudo-asynchronous modes the trimatrix memory architecture implements sync hronous ram by registering the input and output sign als to the ram block. the inputs to all trimatrix memory blocks are registered providing synchronous write cycles, while the output registers can be bypassed. in a synchronous operation, ram generates its own self-timed strobe write enable signal derived from the global or regional clock. in contrast, a circuit using asynchronous ram must generate th e ram write enable signal while ensuring that its data and address signals meet setup and hold time specifications relative to the write enable signal. during a synchronous operation, the ram is used in pipelined mode (inputs and outputs registered) or flow-through mode (onl y inputs registered). however, in an asynchronous memory, neither the input nor the output is registered. while stratix ii and stratix ii gx devices do not support asynchronous memory, they do support a pseudo-a synchronous read where the output data is available during the clock cy cle when the read address is driven into it. pseudo-asynchronous reading is possible in the simple and true dual-port modes of the m512 and m4k bl ocks by clocking the read enable and read address registers on the ne gative clock edge and bypassing the output registers. f refer to an 210: converting memory from asynchronous to synchronous for stratix and stratix gx designs for more information. power-up conditions and memory initialization upon power up, trimatrix memory is in an idle state. the m512 and m4k block outputs always power-up to zero, regardless of whether the output registers are used or bypassed. even if an mif is used to pre-load the contents of the ram block, the outputs will still power-up as cleared. for example, if address 0 is pre-initialized to ff, the m512 and m4k blocks power up with the output at 00. m-ram blocks do not support mifs; ther efore, they cannot be pre-loaded with data upon power up. m-ram blocks asynchronous outputs and memory controls always power up to an unknown state. if m-ram block outputs are registered, the registers power up as cleared. when a read is performed immediately after power up, the output from the read operation will be undefined since th e m-ram contents are not initialized. the read operation will continue to be undefined for a given address until a write operation is performed for that address.
altera corporation 2?33 january 2008 stratix ii device handbook, volume 2 trimatrix embedded memory blocks in stratix ii and stratix ii gx devices read-during- write operation at the same address the ?same-port read-during-write mode? on page 2?33 and ?mixed- port read-during-write mode? on page 2?34 sections describe the functionality of the various ram conf igurations when reading from an address during a write operation at that same address. there are two read-during-write data flows: same-port and mixed-port. figure 2?20 shows the difference between these flows. figure 2?20. stratix ii and stratix ii gx read-during-write data flow same-port read-during-write mode for read-during-write operation of a single-port ram or the same port of a true dual-port ram, the new data is available on the rising edge of the same clock cycle on which it was written. this behavior is valid on all memory block sizes. figure 2?21 shows a sample functional waveform. when using byte enables in true dual-port ram mode, the outputs for the masked bytes on the same port are unknown (refer to figure 2?1 on page 2?7 ). the non-masked bytes ar e read out as shown in figure 2?21 . port a data in port b data in port a data out port b data out mixed-port data flow same-port data flow
2?34 altera corporation stratix ii device handbook, volume 2 january 2008 read-during-write operation at the same address figure 2?21. stratix ii and stratix ii g x same-port read-during-write functionality note (1) note to figure 2?21 : (1) outputs are not registered. mixed-port read-during-write mode this mode is used when a ram in simple or true dual-port mode has one port reading and the other port writin g to the same addr ess location with the same clock. the read_during_write_mode_mixed_ports parameter for m512 and m4k memory blocks determines wh ether to output the old data at the address or a ?don?t care? value. setting this parameter to old_data outputs the old data at that addr ess. setting this parameter to dont_care outputs a ?don?t care? or unknown value. figures 2?22 and 2?23 show sample functional waveforms where b oth ports have the same address. these figures assume that the outputs are not registered. the dont_care setting allows memory implementation in any trimatrix memory block, whereas the old_data setting restricts memory implementation to only m512 or m4k memory blocks. selecting dont_care gives the compiler more flex ibility when placing memory functions into trimatrix memory. the ram outputs are unknown for a mixed-port read-during-write operation of the same address location of an m-ram block, as shown in figure 2?23 . inclock data wren q a b a old
altera corporation 2?35 january 2008 stratix ii device handbook, volume 2 trimatrix embedded memory blocks in stratix ii and stratix ii gx devices figure 2?22. stratix ii and stratix ii g x mixed-port read-during-write: old_data figure 2?23. stratix ii and stratix ii g x mixed-port read-during-write: dont_care mixed-port read-during-write is not supported when two different clocks are used in a dual-port ram. the output value is unknown during a mixed-port read-during-write operation. conclusion the trimatrix memory structure of stratix ii and stratix ii gx devices provides an enhanced ram architectu re with high memory bandwidth. it addresses the needs of different memory applications in fpga designs with features such as different me mory block sizes and modes, byte enables, parity bit storage, address clock enables, mixed clock mode, shift register mode, mixed-port width support, and true dual-port mode. inclock data_a wren_a q_b ab a old wren_b b address q address_a and address_b inclock data_a wren_a q_b ab wren_b b address q address_a and address_b unknown
2?36 altera corporation stratix ii device handbook, volume 2 january 2008 referenced documents referenced documents this chapter references the following documents: an 207: trimatrix memory selection using the quartus ii software an 210: converting memory from asynchronous to synchronous for stratix and stratix gx designs fifo partitioner megafunction user guide single- and dual-clock fifo megafunctions user guide stratix ii device family data sheet (volume 1) of the stratix ii device handbook stratix ii gx device family data sheet (volume 1) of the stratix ii gx device handbook using parity to de tect memory errors white paper document revision history table 2?15 shows the revision history for this chapter. table 2?15. document revision history date and document version changes made summary of changes january 2008, v4.5 added ?referenced documents? section. ? minor text edits. ? no change for the stratix ii gx device handbook only: formerly chapter 7. the chapter number changed due to the addition of the stratix ii gx dynamic reconfiguration chapter. no content change. ? may 2007, v4.4 added note to ?byte enable functional waveform? section. ? updated ?byte enable support? section. ? february 2007 v4.3 added the ?document revision history? section to this chapter. ? april 2006, v4.2 chapter updated as part of the stratix ii device handbook update. ? no change formerly chapter 6. chapter number change only due to chapter addition to section i in february 2006; no content change. ? december 2005, v4.1 chapter updated as part of the stratix ii device handbook update. ? october 2005 v4.0 added chapter to the stratix ii gx device handbook .?
altera corporation 3?1 january 2008 3. external memory interfaces in stratix ii and stratix ii gx devices introduction stratix ? ii and stratix ii gx devices su pport a broad range of external memory interfaces such as doub le data rate (ddr) sdram, ddr2 sdram, rldram ii, qdrii sram, and single data rate (sdr) sdram. its dedicated phase-shift circuitry al lows the stratix ii or stratix ii gx device to interface with an external memory at twice the system clock speed (up to 300 mhz/600 megabits per second (mbps) with rldram ii). in addition to external memory interfaces, you can also use the dedicated phase-shift circuitry fo r other applications that require a shifted input signal. typical i/o architectures transmit a single data word on each positive clock edge and are limited to the associated clock speed. to achieve a 400-mbps transfer rate, a sdr system requires a 400-mhz clock. many new applications have introduced a ddr i/o architecture as an alternative to sdr architectures. whil e sdr architectures capture data on one edge of a clock, the ddr archit ectures captures data on both the rising and falling edges of the clock, doubling the throughput for a given clock frequency and accelerating pe rformance. for example, a 200-mhz clock can capture a 400-mbps data stream, enhancing system performance and simplifying board design. most new memory architectures us e a ddr i/o interface. although stratix ii and stratix ii gx devices also support the mature and well established sdr external memory, th is chapter focuses on ddr memory standards. these ddr memory standards cover a broad range of applications for embedded processor systems, image processing, storage, communications, and networking. stratix ii devices offer external memo ry support in every i/o bank. the side i/o banks support the pll-base d interfaces running at up to 200 mhz, while the top and bottom i/o banks support pll- and dll-based interfaces. figure 3?1 shows stratix ii device memory support. sii52003-4.5
3?2 altera corporation stratix ii device handbook, volume 2 january 2008 introduction figure 3?1. external memory support bank 3 bank 4 bank 11 bank 9 pll11 pll5 pll7 pll1 pll2 pll4 pll3 pll10 support pll- and dll-based implementations support pll-based implementation support pll-based implementation support pll- and dll-based implementations vref0b3 vref1b3 vref2b3 vref3b3 vref4b3 vref0b4 vref1b4 vref2b4 vref3b4 vref4b4 bank 8 bank 7 bank 12 bank 10 pll12 pll6 pll8 pll9 vref4b8 vref3b8 vref2b8 vref1b8 vref0b8 vref4b7 vref3b7 vref2b7 vref1b7 vref0b7 vref3b 2 vref2b2 vref1b2 vref0b2 bank 2 vref3b1 vref2b1 vref1b1 vref0b1 bank 1 vref1b 5 vref2b5 vref3b5 vref4b5 bank 5 vref1b6 vref2b6 vref3b6 vref4b6 bank 6 vref4b2 vref0b5 vref4b1 vref0b6 dqs4t dqs3t dqs2t dqs1t dqs0t dqs4b dqs3b dqs2b dqs1b dqs0b dqs8b dqs7b dqs6b dqs5b dqs8t dqs7t dqs6t dqs5t
altera corporation 3?3 january 2008 stratix ii device handbook, volume 2 external memory interfaces in stratix ii and stratix ii gx devices table 3?1 summarizes the maximum clock rate stratix ii and stratix ii gx devices can support with external memory devices. this chapter describes the hardware features in stratix ii and stratix ii gx devices that facilitate the high-speed memory interfacing for each ddr memory standard. this chapter focuses primarily on the dll-based implementation. the pll-based im plementation is described in application notes. it then lists the stratix ii and stratix ii gx feature enhancements from stratix device s and briefly explains how each memory standard uses the stratix ii and stratix ii gx features. f you can use this document wi th the following documents: an 325: interfacing rldram ii wi th stratix ii & stratix gx devices an 326: interfacing qdrii & qdrii+ sram with stratix ii, stratix, & stratix gx devices an 327: interfacing ddr sdram with stratix ii devices an 328: interfacing ddr2 sdra m with stratix ii devices table 3?1. stratix ii and stra tix ii gx maximum clock rate suppor t for external memory interfaces notes (1) , (2) memory standards ?3 speed grade (mhz) ?4 speed grade (mhz) ?5 speed grade (mhz) dll-based pll-based dll-based pll-based dll-based pll-based ddr2 sdram (3) , (5) 333 200 267 167 233 167 ddr sdram (3) 200 150 200 133 200 100 rldram ii 300 200 250 (4) 175 200 175 qdrii sram 300 200 250 167 250 167 qdrii+ sram 300 (6) 250 (6) 250 (6) notes to ta b l e 3 ? 1 : (1) memory interface timing specifications are dependent on the memory, board, physical interface, and core logic. refer to each memory interface application note for more details on how each specification was generated. (2) the respective altera megacore function and the ep 2s60f1020c3 timing information featured in the quartus ? ii software version 6.0 was used to define these clock rates. (3) this applies for interfaces with both modules and components. (4) you must underclock a 300-mhz rldram ii device to achieve this clock rate. (5) to achieve speeds greater than 267 mhz (533 mbps) up to 333 mhz (667 mbps), you must use the altera ddr2 sdram controller megacore function that features a new dy namic auto-calibration circuit in the data path for resynchronization. for more informat ion, see the altera web site at www.altera.com . for interfaces running at 267 mhz or below, continue to use the static resynchron ization data path currently supported by the released version of the megacore function. (6) the lowest frequency at which a qdrii+ sram device can operate is 238 mhz. therefore, the pll-based implementation does not supp ort the qdrii+ sram interface.
3?4 altera corporation stratix ii device handbook, volume 2 january 2008 external memory standards external memory standards the following sections briefly descri be the external memory standards supported by stratix ii and stratix ii gx devices. altera offers a complete solution for these memories, includ ing clear-text data path, memory controller, and timing analysis. ddr and ddr2 sdram ddr sdram is a memory architecture that transmits and receives data at twice the clock speed. these devices transfer data on both the rising and falling edge of the clock signal . ddr2 sdram is a second generation memory based on the ddr sdram architecture and transfers data to stratix ii and stratix ii gx devices at up to 333 mhz/667 mbps. stratix ii and stratix ii gx devices can support ddr sdram at up to 200 mhz/400 mbps. for pll-based im plementations, stratix ii and stratix ii gx devices support ddr and ddr2 sdram up to 150 mhz and 200 mhz, respectively. interface pins ddr and ddr2 sdram devices use inte rface pins such as data (dq), data strobe (dqs), clock, command, and address pins. data is sent and captured at twice the system clock rate by transferring data on the clock?s positive and negative edge. the commands and addresses still only use one active (positive) edge of a clock. ddr and ddr2 sdram use single-ended data strobes (dqs). ddr2 sdram can also use optional differential data strobes (dqs and dqs#). however, stratix ii and stratix ii gx devices do not use the op tional differential data strobes for ddr2 sdram interfaces since dqs an d dqsn pins in stratix ii and stratix ii gx devices are not differential. you can leave the ddr sdram memory dqs# pin unconnected. only the shifted dqs signal from the dqs logic block is used to capture data. ddr and ddr2 sdram 16 devices use two dqs pins, and each dqs pin is associated with eight dq pins. however, this is not the same as the 16/18 mode in stratix ii and stratix ii gx devices (see ?data and data strobe pins? on page 3?14 ). to support a 16 ddr sdram device, you need to configure stratix ii and stratix ii gx devices to use two sets of dq pins in 8/9 mode. similarly if your 32 memory device uses four dqs pins where each dqs pin is associated with eight dq pins, you need to configure stratix ii and stratix ii gx devices to use four sets of dqs/dq groups in 8/9 mode. connect the memory device?s dq and dqs pins to stratix ii and stratix ii gx dq and dqs pins, respectively, as listed in stratix ii and stratix ii gx pin tables. ddr and ddr 2 sdram also uses active-high data mask, dm, pins for writes. you can connect the memory?s dm pins
altera corporation 3?5 january 2008 stratix ii device handbook, volume 2 external memory interfaces in stratix ii and stratix ii gx devices to any of stratix ii and stratix ii gx i/o pins in the same bank as the dq pins of the fpga. there is one dm pin per dqs/dq group in a ddr or ddr2 sdram device. you can also use i/o pins in banks 1, 2, 5, or 6 to interface with ddr and ddr2 sdram devices. these banks do not have dedicated circuitry, though, and can only support ddr sd ram at speeds up to 150 mhz and ddr2 sdram at speeds up to 200 mhz. ddr2 sdram interfaces using these banks are supported using th e sstl-18 class i i/o standard. f for more information, see an 327: interfacing ddr sdram with stratix ii devices and an 328: interfacing ddr2 sdram with stratix ii devices . if the ddr or ddr2 sdram device supports error correction coding (ecc), the design will use an extr a dqs/dq group for the ecc pins. you can use any of the user i/o pins for commands and addresses to the ddr and ddr2 sdram. you may need to generate these signals from the system clock?s negative edge. the clocks to the sdram device are ca lled ck and ck# pins. use any of the user i/o pins via the ddr regi sters to generate the ck and ck# signals to meet the ddr sdram or ddr2 sdram device?s t dqss requirement. the memory device?s t dqss specification requires that the write dqs signal?s positive edge must be within 25% of the positive edge of the ddr sdram or ddr2 sdram clock input. us ing regular i/o pins for ck and ck# also ensures th at any pvt variations on the dqs signals are tracked the same wa y by these ck and ck# pins. figure 3?2 shows a diagram that illustrate s how to generate these clocks.
3?6 altera corporation stratix ii device handbook, volume 2 january 2008 external memory standards figure 3?2. clock generation for exter nal memory interfaces in strati x ii and stratix ii gx devices notes to figure 3?2 : (1) ck and ck# are the clocks to the memory devices. (2) dk and dk# are for rldram ii interfaces. you can generate dk# and dk from separate pins if the difference of the quartus ii software?s reported clock-to-out time for these pins meets the rldram ii device?s t ckdk specification. read and write operations when reading from the memory, ddr and ddr2 sdram devices send the data edge-aligned with respect to the data strobe. to properly read the data in, the data strobe needs to be ce nter-aligned with respect to the data inside the fpga. stratix ii and stratix ii gx devices feature dedicated circuitry to shift this data strobe to the middle of the data window. figure 3?3 shows an example of how the memory sends ou t the data and data strobe for a burst-of-two operation. q d q d le ioe v cc v cc ck# (1 ) dk# (2 ) ck (1) dk (2) q d q d clk v cc v cc gnd gnd
altera corporation 3?7 january 2008 stratix ii device handbook, volume 2 external memory interfaces in stratix ii and stratix ii gx devices figure 3?3. example of a 90 shift on the dqs signal notes (1) , (2) notes to figure 3?3 : (1) rldram ii and qdrii sram memory interfaces do not have preamble and postamble specifications. (2) ddr2 sdram does not support a burst length of two. (3) the phase shift required for your system should be based on your timing analysis and may not be 90. during write operations to a ddr or ddr2 sdram device, the fpga needs to send the data to the memory center-aligned with respect to the data strobe. stratix ii and stratix ii g x devices use a pll to center-align the data by generating a 0 phase-shif ted system clock for the write data strobes and a ?90 phase-shifted write clock for the write data pins for ddr and ddr2 sdram. figure 3?4 shows an example of the relationship between the data and da ta strobe during a burst-of-four write. dqs at fpga pin dq at fpga pin dqs at ioe registers dq at ioe registers 90? degree dq pin to r egister delay dqs pin to r egister delay preamble postamble (3)
3?8 altera corporation stratix ii device handbook, volume 2 january 2008 external memory standards figure 3?4. dq and dqs relationship during a ddr and ddr2 sdram write notes (1) , (2) notes to figure 3?4 : (1) this example shows a write for a burst length of four. ddr sdram also supports burst lengths of two. (2) the write clock signals never go to hi-z state on rldram ii and qdrii sram memory interfaces because they use free-running clocks. however, the general timing relationship between data and the read clock shown in this figure still applies. f for more information on ddr sdram and ddr2 sdram specifications, refer to jedec standard publications jesd79c and jesd79-2, respectively, from www.jedec.org , or see an 327: interfacing ddr sdram with stratix ii devices and an 327: interfacing ddr sdram with stratix ii devices . rldram ii rldram ii provides fast random acce ss as well as high bandwidth and high density, making this memory technology ideal for high-speed network and communication data storage applications. the fast random access speeds in rldram ii device s make them a viable alternative to sram devices at a lower cost. additionally, rldram ii devices have minimal latency to support designs th at require fast response times. interface pins rldram ii devices use interface pins such as data, clock, command, and address pins. there are two types of rldram ii memory: common i/o (cio) and separate i/o (sio). the data pins in a rldram ii cio device are bidirectional while the data pins in a rldram ii sio device are unidirectional. instead of bidirectional data strobes, rldram ii uses differential free-running read and wr ite clocks to accompany the data. as in ddr or ddr2 sdram, data is sent and captured at twice the system clock rate by transferring data on th e clock?s positive and negative edge. the commands and addresses still only use one active (positive) edge of a clock. if the data pins are bidirectional, as in rldram ii cio devices, connect them to stratix ii and stratix ii gx dq pins. if the data pins are unidirectional, as in rldram ii si o devices, connect the rldram ii device q ports to the stratix ii and stratix ii gx device dq pins and dqs at fpga pin dq at fpga pin
altera corporation 3?9 january 2008 stratix ii device handbook, volume 2 external memory interfaces in stratix ii and stratix ii gx devices connect the d ports to any user i/o pins in i/o banks 3, 4, 7, or 8 for optimal performance. rldram ii also uses active-high data mask, dm, pins for writes. you can connect dm pins to any of the i/o pins in the same bank as the dq pins of the fpga when interfacing with rldram ii cio devices to any of the i/ o pins in the same bank as the d pins when interfacing with rldram ii sio devices. there is one dm pin per rldram ii device. you can also use i/o pins in banks 1, 2, 5, or 6 to interface with rldram ii devices. however, these ba nks do not have dedicated circuitry and can only su pport rldram ii devices at speeds up to 200 mhz. rldram ii interfaces using these banks are supported using the 1.8-v hstl class i i/o support. connect the rldram ii device?s read clock pins (qk) to stratix ii or stratix ii gx dqs pins. because of software requirements, you must configure the dqs signals as bidirectional pins. however, since qk pins are output-only pins from the memo ry, rldram ii memory interfacing in stratix ii and stratix ii gx devices requires that you ground the dqs pin output enables. stratix ii and st ratix ii gx devices use the shifted qk signal from the dqs logic block to capture data. you can leave the qk# signal of the rldram ii device un connected, as dqs and dqsn in stratix ii and stratix ii gx device s are not differential pins. rldram ii devices also have inpu t clocks (ck and ck#) and write clocks (dk and dk#). you can use any of the user i/o pins for commands and addresses. rldram ii also offers qvld pins to indicate the read data availability. connect the qvld pins to the stra tix ii or stratix ii gx dqvld pins, listed in the pin table. 1 because the quartus ii software treats the dqvld pins like dq pins, you should ensure that th e dqvld pin is assigned to the pin table?s recommended pin. read and write operations when reading from the rldram ii device, data is sent edge-aligned with the read clock qk and qk#. when writing to the rldram ii device, data must be center-aligned with the write clock (dk and dk#). the rldram ii interface uses the same scheme as in ddr or ddr2 sdram interfaces, where the dedicated circuitry is used during reads to center-align the data and the read clock inside the fpga and the pll center-aligns the data and write clock outputs. the data and clock relationship for reads and writes in rldram ii is similar to those in ddr and ddr2 sdram as shown in figures 3?3 and 3?4 .
3?10 altera corporation stratix ii device handbook, volume 2 january 2008 external memory standards f for details on rldram ii, see an 325: interfacing rldram ii with stratix ii & stratix gx devices . qdrii sram qdrii sram is the second generati on of qdr sram devices. both devices can transfer four words per clock cycle, fulfilling the requirements facing next-generation communications system designers. qdrii sram devices provide concurrent reads and writes, zero latency, and increased data throughput, allowing simultaneous access to the same address location. qdrii sram is avai lable in burst-of-2 and burst-of-4 devices. burst-of-2 devices support tw o-word data transfer on all read and write transactions, and burst-of-4 devices support four-word data transfer interface pins qdrii sram uses two separate, unidir ectional data ports for read and write operations, enabling qdr data transfer. qdrii sram uses shared address lines for reads and writes. qdrii sram burst-of-two devices sample the read address on the rising edge of the clock and sample the write address on the falling edge of the clock while qdrii sram burst-of-four devices sample both read and write addresses on the clock?s rising edge. connect the memory device?s q ports (read data) to the stratix ii or stratix ii gx dq pins. yo u can use any of the stratix ii or stratix ii gx device user i/o pins in i/o banks 3, 4, 7, or 8 for the d ports (write data), commands, and addresses. the control signals are sampled on the rising edge of the clock. you can also use i/o pins in banks 1, 2, 5, or 6 to interface with qdrii sram de vices. however, these banks do not have dedicated circuitry and can only support qdrii sram devices at speeds up to 200 mhz. qdrii sram in terfaces using these banks are supported using the 1.8-v hstl class i i/o support. qdrii sram uses the fo llowing clock signals: input clocks k and k# output clocks c and c# echo clocks cq and cq# clocks c#, k#, and cq# are logical complements of clocks c, k, and cq, respectively. clocks c, c#, k, and k# are inputs to the qdrii sram while clocks cq and cq# are outputs fr om the qdrii sram. stratix ii and stratix ii gx devices use single-clock mode for single-device qdrii sram interfacing where the k and k# are used for write operations, and cq and cq# are used for read operat ions. you should use both c or c# and k or k# clocks when interfacing with a bank of multiple qdrii sram devices with a single controller.
altera corporation 3?11 january 2008 stratix ii device handbook, volume 2 external memory interfaces in stratix ii and stratix ii gx devices you can generate c, c#, k, and k# cl ocks using any of the i/o registers via the ddr registers. because of stri ct skew requirements between k and k# signals, use adjacent pins to generate the clock pair. connect cq and cq# pins to the stratix ii or stratix ii gx dqs and dqsn pins for dll-based implementation s. you must configure dqs and dqsn as bidirectional pins. howe ver, since cq and cq# pins are output-only pins from the memory, th e stratix ii or stratix ii gx device qdrii sram memory interface requir es that you ground the dqs and dqsn output enable. to capture data presented by the memory, connect the shifted cq signal to the input la tch and connect the active-high input registers and the shifted cq# signal is connected to the active-low input register. for pll-based implementation s, connect qk to the input of the read pll and leave qk# unconnected. read and write operations figure 3?5 shows the data and clock relationships in qdrii sram devices at the memory pins during re ads. data is output one-and-a-half clock cycles after a read command is latched into memory. qdrii sram devices send data within a t co time after each rising edge of the read clock c or c# in multi-clock mode, or the input clock k or k# in single clock mode. data is valid until t doh time after each rising edge of the read clock c or c# in multi-clock mode or the input clock k or k# in single clock mode. the cq and cq# clocks are edge-a ligned with the read data signal. these clocks accompany the read data for data capture in stratix ii and stratix ii gx devices.
3?12 altera corporation stratix ii device handbook, volume 2 january 2008 external memory standards figure 3?5. data and clock relations hip during a qd rii sram read note (1) notes to figure 3?5 : (1) this relationship is at the memory device. the timing parameter nomencla ture is based on the cypress qdrii sram data sheet for cy7c1313v18. (2) t co is the data clock-to-out time and t doh is the data output hold time between burst. (3) t clz and t chz are bus turn-on and turn -off times respectively. (4) t cqd is the skew between the rising edge of cq or cq# and the data edges. (5) t ccqo and t cqoh are skew measurements between the c or c# clocks (or the k or k# clocks in single-clock mode) and the cq or cq# clocks. when reading from the qdrii sram, da ta is sent edge-aligned with the rising edge of the echo clocks cq and cq#. both cq and cq# are shifted inside the fpga using dqs and dqsn logic blocks to capture the data in the ddr ioe registers in dll-based implementations. in pll-based implementations, cq feeds a pll, wh ich generates the clock to capture the data in the ddr ioe registers. when writing to qdrii sram devices, data is generated by the write clock while the k clock is 90 shifted from the write clock, creating a center-aligned arrangement. read and write operations occur during the same clock cycle on independent read and write data pa ths along with th e cycle-shared address bus. performing concurrent re ads and writes does not change the functionality of either transaction. if a read request occurs simultaneously with a write request at the same addr ess, the new data on d is forwarded to q. therefore, latency is not required to access valid data. f for more information on qdrii sram, go to www.qdrsram.com or see an 326: interfacing qdrii & qdrii+ sr am with stratix ii, stratix, & stratix gx devices . qa qa + 1 qa + 2 qa + 3 c/k c#/k# cq cq# q t co (2) t co (2) t clz (3) t ccqo (5) t cqoh (5) t cqd (4) t cqd (4) t doh (2) t chz (3)
altera corporation 3?13 january 2008 stratix ii device handbook, volume 2 external memory interfaces in stratix ii and stratix ii gx devices stratix ii and stratix ii gx ddr memory support overview this section describes stratix ii and stratix ii gx features that enable high-speed memory interfacing. it first describe s stratix ii and stratix ii gx memory pins and then th e dqs phase-shift circuitry and the ddr i/o registers. table 3?2 shows the i/o standard associated with the external memory interfaces. stratix ii and stratix ii gx devices suppo rt the data strobe or read clock signal (dqs) used in ddr sdra m, ddr2 sdram, rldram ii, and qdrii sram devices with dedicated ci rcuitry. stratix ii and stratix ii gx devices also support the dqsn signal (the dqs complement signal) for external memory types that requ ire them, for example qdrii sram. dqs and dqsn signals are usually asso ciated with a group of data (dq) pins. however, these are not differential buffers and cannot be used in ddr2 sdram or rldram ii interfaces. 1 you can also interface with these external memory devices without the use of dedicated circ uitry at a lower performance. f for more information, see the appr opriate stratix ii or stratix ii gx memory interfaces applic ation note available at www.altera.com . stratix ii and stratix ii gx devices cont ain dedicated circuitry to shift the incoming dqs signals by 0, 22.5, 30, 36, 45, 60, 67.5, 72, 90, 108, 120, or 144, depending on the delay-locked loop (dll) mode. there are four dll modes. the dqs phase-shift circuitry uses a frequency reference to dynamically generate control signals for the delay chains in each of the dqs and dqsn pins, allo wing it to compensate for process, table 3?2. external memory support in stratix ii and strati x ii gx devices memory standard i/o standard ddr sdram sstl-2 class ii ddr2 sdram sstl-18 class ii (1) rldram ii (2) 1.8-v hstl class i or ii (1) qdrii sram (2) 1.8-v hstl class i or ii (1) notes to ta b l e 3 ? 2 : (1) stratix ii and stratix ii gx devices support 1.8-v hstl/sstl-18 class i and ii i/o standards in i/o banks 3, 4, 7, and 8. in i/o banks 1, 2, 5, and 6, class i is supported for both input and output operat ions, while class ii is only supported for input operations for these i/o standards. (2) for maximum performance, altera recommends using the 1.8-v hstl i/o standard. rldram ii and qdrii sram de vices also support the 1.5-v hstl i/o standard.
3?14 altera corporation stratix ii device handbook, volume 2 january 2008 stratix ii and stratix ii gx ddr memory support overview voltage, and temperature (pvt) variat ions. this phase-shift circuitry has been enhanced in stratix ii and stratix ii gx devices to support more phase-shift options with less jitter. besides the dqs dedicated phase-shift circuitry, each dqs and dqsn pin has its own dqs logic block that sets the delay for the signal input to the pin. using the dqs dedicated phase- shift circuitry wi th the dqs logic block allows for phase-shift fine-tun ing. additionally, every ioe in a stratix ii or stratix ii gx device contains six registers and one latch to achieve ddr operation. ddr memory interface pins stratix ii and stratix ii gx devices use data (dq), data strobe (dqs and dqsn), and clock pins to inte rface with external memory. figure 3?6 shows the dq, dqs, and dqsn pins in the stratix ii or stratix ii gx i/o banks on the top of the device. a similar arrangement is repeated at the bottom of the device. figure 3?6. dq and dqs pins per i/o bank data and data strobe pins stratix ii and stratix ii gx data pins for the ddr memory interfaces are called dq pins. stratix ii and stratix ii gx devices can use either bidirectional data strobes or unidirectional read clocks. depending on the external memory interface, either th e memory device?s read data strobes or read clocks feed the stratix ii or stratix ii gx dqs (and dqsn) pins. pll 11 pll 5 i/o bank 11 i/o bank 3 i/o bank 9 i/o bank 4 dqs phase shift circuitry dq pins dq pins dqs pin dqsn pin dqsn pin dqs pin up to 8 sets of dq & dqs pins up to 10 sets of dq & dqs pins
altera corporation 3?15 january 2008 stratix ii device handbook, volume 2 external memory interfaces in stratix ii and stratix ii gx devices stratix ii and stratix ii gx dqs pins connect to the dqs pins in ddr and ddr2 sdram interfaces or to the qk pi ns in rldram ii interfaces. the dqsn pins are not used in these in terfaces. connect the stratix ii or stratix ii gx dqs and dqsn pins to the qdrii sram cq and cq# pins, respectively. in every stratix ii or stratix ii gx device, the i/o banks at the top (i/o banks 3 and 4) and bottom (i/o banks 7 and 8) of the device support ddr memory up to 300 mhz/600 mbps (wit h rldram ii). these i/o banks support dqs signals and its comple ment dqsn signals with dq bus modes of 4, 8/9, 16/18, or 32/36. in 4 mode, each dqs/dqsn pin drives up to four dq pins within that group. in 8/9 mode, each dqs/dqsn pin drives up to nine dq pins within that group to support one parity bit and the eight data bits. if the parity bit or any data bit is not used , the extra dq pins can be used as regular user i/o pins. similarly, wi th 16/18 and 32/36 modes, each dqs/dqsn pin drives up to 18 and 36 dq pins respectively. there are two parity bits in the 16/18 mode and four parity bits in the 32/36 mode. tables 3?3 through 3?6 show the number of dqs/dq groups and non-dqs /dq supported in each stratix ii or stratix ii gx density/package combination, respectively, for dll-based implementations. table 3?3. stratix ii dqs and dq bus mode support (part 1 of 2) note (1) device package number of 4 groups number of 8/9 groups number of 16/18 groups number of 32/36 groups ep2s15 484-pin fineline bga 8 4 0 0 672-pin fineline bga 18 8 4 0 ep2s30 484-pin fineline bga 8 4 0 0 672-pin fineline bga 18 8 4 0 ep2s60 484-pin fineline bga 8 4 0 0 672-pin fineline bga 18 8 4 0 1,020-pin fineline bga 36 18 8 4 ep2s90 484-pin hybrid fineline bga 8 4 0 0 780-pin fineline bga 18 8 4 0 1,020-pin fineline bga 36 18 8 4 1,508-pin fineline bga 36 18 8 4 ep2s130 780-pin fineline bga 18 8 4 0 1,020-pin fineline bga 36 18 8 4 1,508-pin fineline bga 36 18 8 4
3?16 altera corporation stratix ii device handbook, volume 2 january 2008 stratix ii and stratix ii gx ddr memory support overview ep2s180 1,020-pin fineline bga 36 18 8 4 1,508-pin fineline bga 36 18 8 4 note to ta b l e 3 ? 3 : (1) check the pin table for each dq s/dq group in the different modes. table 3?3. stratix ii dqs and dq bus mode support (part 2 of 2) note (1) device package number of 4 groups number of 8/9 groups number of 16/18 groups number of 32/36 groups table 3?4. stratix ii non-dqs and dq bus mode support note (1) device package number of 4 groups number of 8/9 groups number of 16/18 groups number of 32/36 groups ep2s15 484-pin fineline bga 13 7 3 1 672-pin fineline bga 24 9 4 2 ep2s30 484-pin fineline bga 13 7 3 1 672-pin fineline bga 36 15 7 3 ep2s60 484-pin fineline bga 13 7 3 1 672-pin fineline bga 36 15 7 3 1,020-pin fineline bga 51 26 13 6 ep2s90 780-pin fineline bga 40 24 12 6 1,020-pin fineline bga 51 25 12 6 1,508-pin fineline bga 51 25 12 6 ep2s130 780-pin fineline bga 40 24 12 6 1,020-pin fineline bga 51 25 12 6 1,508-pin fineline bga 51 25 12 6 ep2s180 1,020-pin fineline bga 51 25 12 6 1,508-pin fineline bga 51 25 12 6 note to ta b l e 3 ? 4 : (1) check the pin table for each dq s/dq group in the different modes.
altera corporation 3?17 january 2008 stratix ii device handbook, volume 2 external memory interfaces in stratix ii and stratix ii gx devices 1 to support the rldram ii qvld pin, some of the unused 4 dqs pins, whose dq pins were combined to make the bigger 8/9, 16/18, or 32/36 groups, are listed as dqvld pins in the stratix ii or stratix ii gx pin table. dqvld pins are for input-only operations. the signal coming into this pin can be captured by the shifted dqs signal like any of the dq pins. table 3?5. stratix ii gx dq s and dq bus mode support note (1) device package number of 4 groups number of 8/9 groups number of 16/18 groups number of 32/36 groups ep2sgx30c ep2sgx30d 780-pin fineline bga 18 8 4 0 ep2sgx60c ep2sgx60d 780-pin fineline bga 18 8 4 0 ep2sgx60e 1,152-pin fineline bga 36 18 8 4 ep2sgx90e 1,152-pin fineline bga 36 18 8 4 ep2sgx90f 1,508-pin fineline bga 36 18 8 4 ep2sgx130g 1,508-pin fineline bga 36 18 8 4 note to ta b l e 3 ? 5 : (1) check the pin table for each dq s/dq group in the different modes. table 3?6. stratix ii gx non-dqs and dq bus mode support note (1) device package number of 4 groups number of 8/9 groups number of 16/18 groups number of 32/36 groups ep2sgx30 780-pin fineline bga 18 8 4 2 ep2sgx60 780-pin fineline bga 18 8 4 2 1,152-pin fineline bga 25 13 6 3 ep2sgx90 1,152-pin fineline bga 25 13 6 3 1,508-pin fineline bga 25 12 6 3 ep2sgx130 1,508-pin fineline bga 25 12 6 3 note to ta b l e 3 ? 6 : (1) check the pin table for each dq s/dq group in the different modes.
3?18 altera corporation stratix ii device handbook, volume 2 january 2008 stratix ii and stratix ii gx ddr memory support overview the dqs pins are listed in the stra tix ii or stratix ii gx pin tables as dqs[17..0]t or dqs[17..0]b . the t denotes pins on the top of the device and the b denotes pins on the bottom of the device. the complement dqsn pins are marked as dqsn[17..0]t or dqsn[17..0]b . the corresponding dq pins are marked as dq[17..0]t[3..0] , where [17..0] indicates which dqs group the pins belong to. similarly, the corr esponding dqvld pins are marked as dqvld[8..0]t , where [8..0] indicates which dqs group the pins belong to. the numbering scheme starts from right to left on the package bottom view. when not used as dq, dq s, or dqsn pins, these pins are available as regular i/o pins. figure 3?7 shows the dqs pins in stratix ii or stratix ii gx i/o banks. 1 the quartus ii software treats dq vld pins as regular dq pins. therefore, you must ensure that the dqvld pin assigned in your design corresponds to the pin table?s recommended dqvld pins. figure 3?7. dqs pins in stratix ii and stratix ii gx i/o banks notes (1) , (2) , (3) notes to figure 3?7 : (1) there are up to 18 pairs of dqs and dqsn pins on both the top and bottom of the device. see table 3?3 for the exact number of dqs and dqsn pin pairs in each device package. (2) see table 3?7 for the available dqs and dqsn pins in each mode and package. (3) each dqs pin has a complement dqsn pin. dqs and dqsn pins are not differential. the dq pin numbering is based on 4 mode. there are up to 8 dqs/dq groups in 4 mode in i/o banks 3 and 8 and up to 10 dqs/dq groups in 4 mode in i/o banks 4 and 7. in 8/9 mode, two adjacent 4 dqs/dq groups plus one parity pin are comb ined; one pair of dqs/dqsn pins from the combined groups can drive all the dq and parity pins. since there is an even number of dqs/dq groups in an i/o bank, combining groups is efficient. similarly, in 16/18 mode, four adjacent 4 dqs/dq groups plus two parity pins are combined and one pair of dqs/dqsn pins from the combined groups can dr ive all the dq and parity pins. in pll 11 pll 5 i/o bank 11 i/o bank 3 i/o bank 9 i/o bank 4 dqs phase shift circuitry dq pins dq pins dqs pin dqsn pin dqsn pin dqs pin up to 8 sets of dq & dqs pins up to 10 sets of dq & dqs pins
altera corporation 3?19 january 2008 stratix ii device handbook, volume 2 external memory interfaces in stratix ii and stratix ii gx devices 32/36 mode, eight adjacent dqs/dq groups are combined and one pair of dqs/dqsn pins can drive al l the dq and parity pins in the combined groups. table 3?7 shows which dqs and dqsn pins are available in each mode and package in the stratix ii or stratix ii gx device family. 1 on the top and bottom side of the device, the dq and dqs pins must be configured as bidirectional ddr pins to enable the dqs phase-shift circuitry. the dqsn pins can be configured as input, output, or bidirectional pins. you can use the altdq and altdqs megafunctions to configure the dq and dqs/dqsn paths, respectively. however, altera highly recommends that you use the respective altera me mory controller ip tool bench for your external memory interfac e data paths. the data path is clear-text and free to use. you are responsible for your own timing analysis if you use your own data path. if you only want to use the dq and/or dqs pins as inputs, you need to set the output enable of the dq and/or dqs pins to ground. stratix ii or stratix ii gx side i/o banks (i/o banks 1, 2, 5, and 6) support all the memory interfaces supported in the top and bottom i/o banks. for optimal performance, use the altera memory contro ller ip tool bench to pick the data and strobe pins for these interfaces. since these i/o banks do not have any dedicated circuitry for memory interfacing, they can support ddr sdram at speeds up to 150 mhz and other ddr memories at speeds up to 200 mhz. you need to use the sstl-18 class i i/o standard when interfacing with ddr 2 sdram devices using pins in i/o bank 1, 2, 5, or 6. these i/o banks do not support the sstl-18 class ii and table 3?7. available dqs and dqsn pins in each mode and package note (1) mode package 484-pin fineline bga 484-pin hybrid fineline bga 672-pin fineline bga 780-pin fineline bga 1,020-pin fineline bga 1,508-pin fineline bga 4 7, 9, 11, 13 odd-numbered pins only all dqs and dqsn pins 8/9 7,11 3, 7, 11, 15 even-numbered pins only 16/18 n/a 5, 13 3, 7, 11, 15 32/36 n/a n/a 5, 13 note to ta b l e 3 ? 7 : (1) the numbers correspond to the dqs and dqsn pin numberin g in the stratix ii or strati x ii gx pin table. there are two sets of dqs/dq groups, one corr esponding with the top side of the device and one with the bottom side of the device.
3?20 altera corporation stratix ii device handbook, volume 2 january 2008 stratix ii and stratix ii gx ddr memory support overview 1.8-v hstl class ii i/o standards on output and bidirectional pins, but you can use sstl-18 class i or 1.8- v hstl class i i/o standards for memory interfaces. 1 the altera memory controller ip tool bench generates the optimal pin constraints that allow you to interface these memories at high frequency. table 3?8 shows the maximum clock rate supported for the ddr sdram interface in the stratix ii or st ratix ii gx device side i/o banks. clock pins you can use any of the ddr i/o registers to generate clocks to the memory device. for better performanc e, use the same i/o bank as the data and address/command pins. command and address pins you can use any of the user i/o pins in the top or bottom bank of the device for commands and addresses. for better performance, use the same i/o bank as the data pins. other pins (parity, dm, ecc and qvld pins) you can use any of the dq pins for the parity pins in stratix ii and stratix ii gx devices. the stratix ii or stratix ii gx device family has support for parity in the 8/9, 16/18, and 32/36 mode. there is one parity bit available per 8 bits of data pins. the data mask, dm, pins are only required when writing to ddr sdram, ddr2 sdram, and rldram ii devices. a low signal on the dm pins indicates that the write is valid. if the dm signal is high, the memory will mask the dq signals. you can use any of the i/o pins in the same bank as the dq pins (or th e rldram ii sio?s and qdrii sram?s d pins) for the dm signals. each gr oup of dqs and dq signals in ddr table 3?8. maximum clock rate for ddr and ddr2 sdram in stratix ii or stratix ii gx side i/o banks stratix ii or stratix ii gx device speed grade ddr sdram (mhz) ddr2 sdram (mhz) qdrii sram (mhz) rldram ii (mhz) -3 150 200 200 200 -4 133 167 167 175 -5 133 167 167 175
altera corporation 3?21 january 2008 stratix ii device handbook, volume 2 external memory interfaces in stratix ii and stratix ii gx devices and ddr2 sdram devices requires a dm pin. there is one dm pin per rldram ii device. the ddr i/o output registers, clocked by the ?90 shifted clock, creates the dm sign als, similar to dq output signals. 1 perform timing analysis to calc ulate your write-clock phase shift. some ddr sdram and ddr2 sdram devices support error correction coding (ecc), which is a method of detecting and automatically correcting errors in data transmissi on. in a 72-bit ddr sdram interface, there are eight ecc pins in addition to the 64 data pins. connect the ddr and ddr2 sdram ecc pins to a stratix ii or stratix ii gx device dqs/dq group. the memory controller needs extra logic to encode and decode the ecc data. qvld pins are used in rldram ii interfacing to indicate the read data availability. there is one qvld pin per rldram ii device. a high on qvld indicates that the memory is outputting the data requested. similar to dq inputs, th is signal is edge-aligned with qk/qk# signals and is sent half a clock cycle before data starts coming out of the memory. you need to connect qvld pins to the dqvld pin on the stratix ii or stratix ii gx device. the dqvld pin ca n be used as a regular user i/o pin if not used for qvld. because the quartus ii software does not differentiate dqvld pins from dq pins, you must ensure that your design uses the pin table?s recommended dqvld pin. dqs phase-shift circuitry the stratix ii or stratix ii gx phase- shift circuitry and the dqs logic block control the dqs and dqsn pins. each stratix ii or stratix ii gx device contains two phase-shifting ci rcuits. there is on e circuit for i/o banks 3 and 4, and another circuit for i/o banks 7 and 8. the phase- shifting circuit on the top of the de vice can control all the dqs and dqsn pins in the top i/o banks and the phas e-shifting circuit on the bottom of the device can control all the dqs and dqsn pins in the bottom i/o banks. figure 3?8 shows the dqs and dqsn pin connections to the dqs logic block and the dqs phase-shift circuitry.
3?22 altera corporation stratix ii device handbook, volume 2 january 2008 stratix ii and stratix ii gx ddr memory support overview figure 3?8. dqs and dqsn pins and the dqs phase-shift circuitry note (1) notes to figure 3?8 : (1) there are up to 18 pairs of dqs and dqsn pins availabl e on the top or the bottom of the stratix ii or stratix ii gx device, up to 8 on the left side of th e dqs phase-shift circuitry (i/o banks 3 and 8), and up to 10 on the right side (i/o bank 4 and 7). (2) clock pins clk[15..12]p feed the phase-shift circuitry on the top of the device and clock pins clk[7..4]p feed the phase-shift circuitry on the bottom of the device. you can also use a phase-locked loop (pll) clock output as a reference clock to the phase-shift circuitry. the refe rence clock can also be used in the logic array. (3) you can only use pll 5 to feed the dqs phase-shift circ uitry on the top of the device and pll 6 to feed the dqs phase-shift circuitry on the bottom of the device. figure 3?9 shows the connections between the dqs phase-shift circuitry and the dqs logic block. dqs pin dqsn pin dqsn pin dqs pin dqs pin dqsn pin dqs pin dqsn pin from pll 5 (3) clk[15..12]p (2) to ioe to ioe to ioe to ioe to ioe to ioe to ioe t t t t t t t to ioe dqs phase-shift circuitry t dqs logic blocks
altera corporation 3?23 january 2008 stratix ii device handbook, volume 2 external memory interfaces in stratix ii and stratix ii gx devices figure 3?9. dqs phase-shift circu itry and dqs logic block connections note (1) notes to figure 3?9 : (1) all features of the dqs phase-shift circuitry and the dqs logic block are accessible from the altdqs megafunction in the quartus ii software. you should, h owever, use altera?s memory controller ip tool bench to generate the data path for your memory interface. (2) dqs logic block is available on every dqs and dqsn pin. (3) there is one dqs phase-shift circuit on the top and bottom side of the device. (4) the input reference clock can come from clk[15..12]p or pll 5 for the dqs phase-shift circuitry on the top side of the device or from clk[7..4]p or pll 6 for the dqs phase-shift circui try on the bottom side of the device. (5) each individual dqs and dqsn pair can have indi vidual dqs delay settings to and from the logic array. (6) this register is one of the dqs ioe input registers. 6 6 phase offset control 6 phase offset settings from the logic array phase offset settings input reference clock (4) upndn clock enable dll 6 addnsub phase comparator delay chains up/down counter dq dq en en update enable circuitry 6 6 6 6 6 6 dqs delay settings to and from the logic array (5) dqs delay settings from the dqs phase-shift circuitry dqs or dqsn dqs delay chain bypass dqs logic block (2) dqs logic block (2) dqs logic block (2) dqs phase-shift circuitry (3) dqs or dqsn dqs or dqsn not postamble circuitry gated_dqs control dqs bus prn clrn q dff reset enablen a b v cc dqs' sclr (6)
3?24 altera corporation stratix ii device handbook, volume 2 january 2008 stratix ii and stratix ii gx ddr memory support overview the phase-shift circuitry is only used during read transactions where the dqs and dqsn pins are acting as inpu t clocks or strobes. the phase-shift circuitry can shift the incoming dqs signal by 0, 22.5, 30, 36, 45, 60, 67.5, 72, 90, 108, 120, or 144. the sh ifted dqs signal is then used as clocks at the dq ioe input registers. figure 3?3 shows an example where the dqs signal is shifted by 90. the dqs signals goes through the 90 shift delay set by the dqs phase-shift circuitry and the dqs lo gic block and some routing delay from the dqs pin to the dq ioe registers. the dq signals only goes through routing delay from the dq pin to the dq ioe registers and maintains the 90 relationship between the dqs and dq signals at the dq ioe registers since the software will automatically set delay chains to match the routing delay between the pins and the ioe registers for the dq and dqs input paths. all 18 dqs and dqsn pins on either the top or bottom of the device can have their input signal phase shifted by a different degree amount but all must be referenced at one particular frequency. for example you can have a 90 phase shift on dqs0t and have a 60 phase shift on dqs1t both referenced from a 200-mhz clock. n ot all phase-shift combinations are supported, however. the ph ase shifts on the same side of the device must all be a multiple of 22.5 (up to 90) , a multiple of 30 (up to 120), or a multiple of 36 (up to 144). in order to generate the correct phase shift with the dll used, you must provide a clock signal of the same fr equency as the dqs signal to the dqs phase-shift circuitry. any of the clk[15..12]p clock pins can feed the phase circuitry on the top of the device (i/o banks 3 and 4) or any of the clk[7..4]p clock pins can feed the phase circuitry on the bottom of the device (i/o banks 7 and 8). stratix i i and stratix ii gx devices can also use plls 5 or 6 as the reference cloc k to the dqs phase-shift circuitry on the top or bottom of the device, resp ectively. pll 5 is connected to the dqs phase-shift circuitry on the top side of the device and pll 6 is connected to the dqs phase-shift circ uitry on the bottom side of the device. both the top and bottom phase- shift circuits need unique clock pins or pll cloc k outputs for the reference clock. 1 when you have a pll dedicated only to generate the dll input reference clock, you must set the pll mode to ?no compensation? or the quartus ? ii software will change it automatically. because there are no other pll outputs used, the pll doesn?t need to compensate for any clock paths.
altera corporation 3?25 january 2008 stratix ii device handbook, volume 2 external memory interfaces in stratix ii and stratix ii gx devices dll the dqs phase-shift circuitry uses a delay-locked loop (dll) to dynamically measure the clock period needed by the dqs/dqsn pin (see figure 3?10 ). the dqs phase-shift circuitry then uses the clock period to generate the correct phase shift. the dll in the stratix ii or stratix ii gx dqs phase-shift circuitry can oper ate between 100 and 400 mhz. the phase-shift circuitry needs a maximum of 256 clock cycles to calculate the correct input clock period. data sent during these clock cycles may not be properly captured. 1 although the dll can run up to 400 mhz, other factors may prevent you from interfacing with a 400-mhz external memory device. 1 you can still use the dqs phase-shift circuitry for any memory interfaces that are less than 100 mhz. the dqs signal will be shifted by 2.5 ns and you can ad d more shift by using the phase offset module. even if the dqs sign al is not shifted exactly to the middle of the dq valid window, the ioe should still be able to capture the data in this low frequency application. there are four different frequency modes for the stratix ii or stratix ii gx dll. each frequency mode provides different phase shift, as shown in table 3?9 . in frequency mode 0, stratix ii devices use a 6-bit setting to implement the phase-shift delay. in frequency modes 1, 2, and 3, stratix ii devices only use a 5-bit setting to implement the phase-shift delay. the dll can be reset from either the logic array or a user i/o pin. this signal is not shown in figure 3?10 . each time the dll is reset, you must wait for 256 clock cycles before you can capture the data properly. table 3?9. stratix ii and strati x ii gs dll frequency modes frequency mode frequency range (mhz) available phase shift number of delay chains 0 100?175 30, 60, 90, 120 12 1 150?230 22.5, 45, 67.5, 90 16 2 200?310 30, 60, 90, 120 12 3 240?400 (c3 speed grade) 240?350 (c4 and c5 speed grades) 36, 72, 108, 144 10
3?26 altera corporation stratix ii device handbook, volume 2 january 2008 stratix ii and stratix ii gx ddr memory support overview 1 the input reference clock for the dqs phase-shift circuitry on the top side of the device can come from clk[15..12]p or pll 5. the input reference cl ock for the dqs phase-shift circuitry on the bottom side of the device can come from clk[7..4]p or pll 6. table 3?10 lists the maximum delay in th e fast timing model for the stratix ii dqs delay buffer. multiply th e number of delay buffers that you are using in the dqs logic block to ge t the maximum delay achievable in your system. for example, if you im plement a 90 phase shift at 200 mhz, you use three delay buffers in mode 2. the maximum achievable delay from the dqs block is th en 3 .416 ps = 1.248 ns. table 3?10. dqs delay buffer maximum delay in fast timing model frequency mode maximum delay per delay buffer (fast timing model) unit 0 0.833 ns 1, 2, 3 0.416 ns
altera corporation 3?27 january 2008 stratix ii device handbook, volume 2 external memory interfaces in stratix ii and stratix ii gx devices figure 3?10. simplified diagram of the dqs phase-shift circuitry note (1) notes to figure 3?10 : (1) all features of the dqs phase-shift circuitry are accessi ble from the altdqs megafunction in the quartus ii software. you should; however, use altera?s memory controller ip tool bench to generate the data path for your memory interface. (2) the input reference clock for the dqs phase-shift circ uitry on the top side of the device can come from clk[15..12]p or pll 5. the input reference clock for the dqs phase-shift circuitry on the bottom side of the device can come from clk[7..4]p or pll 6. (3) phase offset settings can only go to the dqs logic blocks. (4) dqs delay settings can go to the logic array and/or to the dqs logic block. the input reference clock goes into the dll to a chain of up to 16 delay elements. the phase comparator compar es the signal co ming out of the end of the delay element chain to th e input reference clock. the phase comparator then issues the upndn signal to the up/down counter. this signal increments or decrements a six-bit delay setting (dqs delay settings) that will increase or de crease the delay through the delay element chain to bring the input reference clock and the signals coming out of the delay elem ent chain in phase. the dqs delay settings contain the cont rol bits to shift the signal on the input dqs pin by the amount set in the altdqs megafunction. for the 0 shift, both the dll and the dqs logi c block are bypassed. since stratix ii and stratix ii gx dqs and dq pins are designed such that the pin to ioe delays are matched, the skew between the dq and dqs pin at the dq ioe registers is negligible when the 0 sh ift is implemented. you can feed the dqs delay settings to the dqs lo gic block and the logic array. 6 6 6 phase offset control 6 phase offset settings from the logic array phase offset settings (3) dqs delay settings (4) input reference clock (2) upndn clock enable dll 6 addnsub phase comparator delay chains up/down counter
3?28 altera corporation stratix ii device handbook, volume 2 january 2008 stratix ii and stratix ii gx ddr memory support overview phase offset control the dqs phase-shift circuitry also cont ains a phase offset control module that can add or subtract a phase offs et amount from the dqs delay setting (phase offset settings from the logic array in figure 3?10 ). you should use the phase offset control module for maki ng small shifts to the input signal and use the dqs phase-shift circuitry fo r larger signal shifts. for example, if you need the input signal to be shifted by 75, you can set the altdqs megafunction to generate a 72 phase shift with a phase offset of +3. you can either use a static phase of fset or a dynamic phase offset to implement the additional phase shift. the availabl e additional phase shift is implemented in 2s -complement between se ttings ?64 to +63 for frequency mode 0, and between settings ?32 to +31 for frequency modes 1, 2, and 3. however, the dqs dela y settings are at the maximum at setting 64 for frequency mode 0, an d at the maximum at setting 32 for frequency modes 1, 2, and 3. therefore, the actual physical offset setting range will be 64 or 32 subtracted by the dqs delay settings from the dll. for example, if the dll determines that to achieve 30 you will need a dqs delay setting of 28, you can subtract up to 28 phase offset settings and you can add up to 36 phase offset settings to achieve the optimal delay. 1 each phase offset setting transl ates to a certain delay, as specified in the dc & switching charact eristics of stratix iii devices chapter in volume 2 of the stratix iii device handbook . when using the static phase offset , you can specify the phase offset amount in the altdqs megafunction as a positive number for addition or a negative number for subtraction. you can also have a dynamic phase offset that is always added to, su btracted from, or both added to and subtracted from the dll phase shift. when you always add or subtract, you can dynamically input the phase offset amount into the dll_offset[5..0] port. when you want to both add and subtract dynamically, you control the addnsub signal in ad dition to the dll_offset[5..0] signals. dqs logic block each dqs and dqsn pin is connected to a separate dqs logic block (see figure 3?11 ). the logic block contains dqs delay chains and postamble circuitry.
altera corporation 3?29 january 2008 stratix ii device handbook, volume 2 external memory interfaces in stratix ii and stratix ii gx devices 1 the input reference clock for the dqs phase-shift circuitry on the top side of the device can come from clk[15..12]p or pll 5. the input reference cl ock for the dqs phase-shift circuitry on the bottom side of the device can come from clk[7..4]p or pll 6. figure 3?11. simplified diagra m of the dqs logic block note (1) notes to figure 3?11 : (1) all features of the dqs logic block are accessible from the altdqs megafunction in the quartus ii software. you should; however, use altera?s memory controller ip tool be nch to generate the data path for your memory interface. (2) the input reference clock for the dqs phase-shift circ uitry on the top side of the device can come from clk[15..12]p or pll 5. the input reference clock for the dqs ph ase-shift circuitry on the top side of the device can come from clk[7..4]p or pll 6. (3) this register is one of the dqs ioe input registers. dq dq en en update enable circuitry 6 6 6 6 6 6 dqs delay settings from the dqs phase- shift circuitry dqs or dqsn pin input reference clock (2) dqs delay chain bypass phase offset settings 6 6 not postamble circuitry gated_dqs control dqs bus prn clrn q dff reset enablen a b v cc dqs' sclr (3)
3?30 altera corporation stratix ii device handbook, volume 2 january 2008 stratix ii and stratix ii gx ddr memory support overview dqs delay chains the dqs delay chains consist of a set of variable delay elements to allow the input dqs and dqsn signals to be shifted by the amou nt given by the dqs phase-shift circuitry or the logic array. there are four delay elements in the dqs delay chain; the first de lay chain closest to the dqs pin can either be shifted by the dqs delay sett ings or by the sum of the dqs delay setting and the phase-offset setting. the number of delay chains used is transparent to the users because the altdqs megafunction automatically sets it. the dqs delay settings can come from the dqs phase-shift circuitry on the same side of the device as the target dqs logic block or from the logic array. when you apply a 0 shift in the altdqs megafunction, the dqs delay chains are bypassed. the delay elements in the dqs logic block mimic the delay elements in the dll. when the dll is not used to control the dqs delay chains, you can input your own 6- or 5-bit settings using the dqs_delayctrlin[5..0] signals available in the altdqs megafunction. these settings control 1, 2, 3, or all 4 dela y elements in the dqs delay chains. the amount of delay is equal to the sum of the delay element?s intrinsic delay and the prod uct of the number of delay steps and the value of the delay steps. both the dqs delay settings and the ph ase-offset settings pass through a latch before going into the dqs delay chains. the latches are controlled by the update enable circuitry to al low enough time for any changes in the dqs delay setting bits to arrive to all the delay elements. this allows them to be adjusted at the same time . the update enable circuitry enables the latch to allow enough time for the dqs delay settings to travel from the dqs phase-shift circuitry to all th e dqs logic blocks before the next change. it uses the input reference cl ock to generate the update enable output. the altdqs megafunction uses this circuit by default. see figure 3?12 for an example waveform of the update enable circuitry output. the shifted dqs signal then goes to the dqs bus to clock the ioe input registers of the dq pins. it can also go into the logic array for resynchronization purposes. the shifte d dqsn signal can only go to the active-low input register in the dq ioe and is only used for qdrii sram interfaces.
altera corporation 3?31 january 2008 stratix ii device handbook, volume 2 external memory interfaces in stratix ii and stratix ii gx devices figure 3?12. dqs update enable waveform dqs postamble circuitry for external memory interfaces that use a bidirectional read strobe like ddr and ddr2 sdram, the dqs signal is low before going to or coming from a high-impedance state. see figure 3?3 . the state where dqs is low, just after a high-impedance state, is called the preamble and the state where dqs is low, just before it re turns to a high-impedance state, is called the postamble. there are prea mble and postamble specifications for both read and write operations in ddr and ddr2 sdram. the dqs postamble circuitry ensures data is not lost when there is noise on the dqs line at the end of a read postambl e time. it is to be used with one of the dqs ioe input registers such that the dqs postamble control signal can ground the shifted dqs signal used to clock the dq input registers at the end of a read operation. this en sures that any glitches on the dqs input signals at the end of the read postamble time do not affect the dq ioe registers. f see an 327: interfacing ddr sd ram with stratix ii devices and an 328: interfacing ddr2 sdram with stratix ii devices for more details. ddr registers each ioe in a stratix ii or stratix ii gx device contains six registers and one latch. two registers and a latch ar e used for input, two registers are used for output, and two registers are used for output enable control. the second output enable register provides the write preamble for the dqs strobe in the ddr external memory interfaces. this ac tive low output enable register extends the high-impedance state of the pin by a half clock cycle to provide the external memory?s dqs write preamble time specification. figure 3?13 shows the six register s and the latch in the stratix ii or stratix ii gx ioe and figure 3?14 shows how the second oe register extends the dqs high-impedance state by half a clock cycle during a write operation. update enable circuitry output system clock dqs delay settings (updated every 8 cycles) dll counter update (every eight cycles) 6 bit dll counter update (every eight cycles)
3?32 altera corporation stratix ii device handbook, volume 2 january 2008 stratix ii and stratix ii gx ddr memory support overview figure 3?13. bidirectional ddr i/o path in stratix ii and stratix ii gx devices note (1) notes to figure 3?13 : (1) all control signals can be inverted at the ioe. the si gnal names used here match with quartus ii software naming convention. (2) the oe signal is active low, but the qu artus ii software implements this as act ive high and automatically adds an inverter before input to the a oe register during compilation. (3) the a oe register generates the enable signal for general-purpose ddr i/o applications. (4) this select line is to choose whether the oe signal should be delayed by half-a-clock cycle. (5) the b oe register generates the delayed enable signal for the write strobes or write cloc ks for memory interfaces. (6) the tristate enable is by default active low. you can, however, design it to be active high. the combinational control path for the tristate is not shown in this diagram. (7) you can also have combinational output to th e i/o pin; this path is not shown in the diagram. (8) on the top and bottom i/o banks, the cl ock to this register can be an inverted register a?s clock or a separate clock (inverted or non-inverted). on the side i/o banks, you can only use the inverted register a?s clock for this port. d q dff d q ena d q dff input re g ister b i input re g ister a i latch c dq dff dq dff 0 1 output re g ister a o output re g ister b o dq dff dq dff or2 tri i/o pin (7 ) oe re g ister b oe oe re g ister a oe lo g ic array dataout_l dataout_h outclock datain_h datain_l oe inclock ne g _re g _out i 0 (5) (4) (6) (3) combout 1 (2) latch tchla (8)
altera corporation 3?33 january 2008 stratix ii device handbook, volume 2 external memory interfaces in stratix ii and stratix ii gx devices figure 3?14. extending the oe disable by ha lf-a-clock cycle for a write transaction note (1) note to figure 3?14 : (1) the waveform reflects the so ftware simulation result. the oe signal is an active low on the device. however, the quartus ii software implements this signal as an active high and automatically adds an inverter before the a oe register d input. figures 3?15 and 3?16 summarize the ioe registers used for the dq and dqs signals. d0 d0 d2 d1 d1 d3 d2 d3 preamble postamble system clock (outclock for dqs) oe for dqs (from logic array) datain_h (from logic array) datain_l (from logic array) oe for dq (from logic array) write clock (outclock for dq, ? 90 phase shifted from system clock) dqs dq delay by half a clock cycle 90?
3?34 altera corporation stratix ii device handbook, volume 2 january 2008 stratix ii and stratix ii gx ddr memory support overview figure 3?15. dq configurat ion in stratix ii or stratix ii gx ioe note (1) notes to figure 3?15 : (1) you can use the altdq megafunction to generate the dq signals. you should, however, use altera?s memory controller ip tool bench to generate the data path for your memory interface. the signal names used here match with quartus ii software naming convention. (2) the oe signal is active low, but the qu artus ii software implements this as act ive high and automatically adds an inverter before the oe register a oe during compilation. (3) the outclock signal for ddr, ddr2 sdram, and qdrii sram inte rfaces has a 90 phase-shift relationship with the system clock. for 300-mhz rldram ii interfaces with ep2s60f1020c3, altera recommends a 75 phase-shift relationship. (4) the shifted dqs or dqsn signal can clock this regist er. only use the dqsn signal for qdrii sram interfaces. (5) the shifted dqs signal must be invert ed before going to the dq ioe. the inversion is automatic if you use the altdq megafunction to generate the dq signals. connect this port to the combout port in the altdqs megafunction. (6) on the top and bottom i/o banks, the cl ock to this register can be an inverted register a?s clock or a separate clock (inverted or non-inverted). on the side i/o banks, you can only use the inverted register a?s clock for this port. d q dff d q la tch ena d q dff input re g ister a i input re g ister b i latch c dq dff dq dff 0 1 dq dff tri dq pin oe re g ister a oe output re g ister a o output re g ister b o lo g ic array latch dataout_l dataout_h outclock (3) datain_h datain_l oe inclock (from dqs bus) ne g _re g _out i (5) (4) (2) (6)
altera corporation 3?35 january 2008 stratix ii device handbook, volume 2 external memory interfaces in stratix ii and stratix ii gx devices figure 3?16. dqs configur ation in stratix ii or stratix ii gx ioe note (1) notes to figure 3?16 : (1) you can use the altdqs megafunction to generate th e dqs signals. you should, however, use altera?s memory controller ip tool bench to generate the data path for your memory interface. the signal names used here match with quartus ii software naming convention. (2) the oe signal is active low, but the qu artus ii software implements this as act ive high and automatically adds an inverter before oe register a oe during compilation. in rldram ii and qdrii sram, the oe signal is always disabled. (3) the select line can be chosen in the altdqs megafunction. (4) the datain_l and datain_h pins are usually connected to ground and v cc , respectively. (5) dqs postamble circuitry and handling is not shown in this diagram. for more information, see an 327: interfacing ddr sdram with stratix ii devices and an 328: interfacing ddr2 sdram with stratix ii devices . (6) dqs logic blocks are only available with dqs and dqsn pins. (7) you must invert this signal before it reaches the dq ioe. this signal is automatically inverted if you use the altdq megafunction to generate the dq signals. connect this port to the inclock port in the altdq megafunction. dq dff dq dff 0 1 output re g ister b o output re g ister a o oe re g ister b oe oe re g ister a oe dq dff dq dff or2 tri dqs pin (5 ) lo g ic array system clock datain_l (4) datain_h (4) oe (3) combout (7) (2) 0 1
3?36 altera corporation stratix ii device handbook, volume 2 january 2008 stratix ii and stratix ii gx ddr memory support overview for interfaces to ddr sdram, ddr 2 sdram, and rldram ii, the stratix ii or stratix ii gx ddr ioe structure requires you to invert the incoming dqs signal to ensure proper data transfer. this is not required for qdrii sram interfaces if the cq signal is wired to the dqs pin and the cq# signal is wired to the dqsn pin. the altdq megafunction, by default, adds the inverter to the inclock port when it generates dq blocks. the megafunction also includes an option to remove the inverter for qdrii sram interfaces. as shown in figure 3?13 , the inclock signal?s rising edge clocks the a i register, inclock signal?s falling edge clocks the b i register, and latch c i is opened when inclock is 1. in a ddr memory read operation, the last data coincides with dqs being low. if you do not invert the dqs pin, you will not get this last data as the latch does not open until the next ri sing edge of the dqs signal. figure 3?17 shows waveforms of the circuit shown in figure 3?15 . the first set of waveforms in figure 3?17 shows the edge-aligned relationship between the dq and dqs signals at the stratix ii or stratix ii gx device pins. the second set of waveforms in figure 3?17 shows what happens if the shifted dq s signal is not inverted; the last data, d n , does not get latched into the logi c array as dqs goes to tristate after the read postamble time. the third set of waveforms in figure 3?17 shows a proper read operation with the dqs signal inverted after the 90 shift; the last data, d n , does get latched. in this case the outputs of register a i and latch c i , which correspond to dataout_h and dataout_l ports, are now switched because of the dqs inversion. register a i , register b i , and latch c i refer to the nomenclature in figure 3?15 .
altera corporation 3?37 january 2008 stratix ii device handbook, volume 2 external memory interfaces in stratix ii and stratix ii gx devices figure 3?17. dq captures with non- inverted and inverted shifted dqs dq at the pin dqs shifted by 90? output of register a 1 (dataout_h) output of latch c 1 (dataout_l) output of register b 1 dqs inverted and shifted by 90? output of register a 1 (dataout_h) output of latch c 1 (dataout_l) output of register b 1 dqs at the pin shifted dqs signal is not inverted shifted dqs signal is inverted dq & dqs signals d n ? 1 d n ? 2 d n ? 2 d n ? 2 d n ? 1 d n d n d n ? 3 d n ? 1 d n ? 1 d n
3?38 altera corporation stratix ii device handbook, volume 2 january 2008 enhancements in stratix ii and stratix ii gx devices pll when using the stratix ii and stratix ii gx top and bottom i/o banks (i/o banks 3, 4, 7, or 8) to interface with a ddr memory, at least one pll with two outputs is needed to generate the system clock and the write clock. the system clock generates the dqs write signals, commands, and addresses. the write clock is either shifted by ?90 or 90 from the system clock and is used to generate the dq signals during writes. for ddr and ddr2 sdram interfaces above 200 mhz, altera also recommends a second read pll to help ease resynchronization. when using the stratix ii and stratix ii g x side i/o banks 1, 2, 5, or 6 to interface with ddr sdram devices, two plls may be needed per i/o bank for best performance. since the side i/o banks do not have dedicated circuitry, one pll captur es data from the ddr sdram and another pll generates the write sign als, commands, and addresses to the ddr sdram device. stratix ii and stratix ii gx side i/o banks can support ddr sdram up to 150 mhz. enhancements in stratix ii and stratix ii gx devices stratix ii and stratix ii gx external memory interfaces support differs from stratix external memory interf aces support in the following ways: a pll output can now be used as the input reference clock to the dll. the shifted dqs signal can now go into the logic array. the dll in stratix ii and stratix ii gx devices has more phase-shift options than in stratix devices. it also has the option to add phase offset settings. stratix ii and stratix ii gx devices have dqs logic blocks with each dqs pin that helps with fine tuning the phase shift. the dqs delay settings can be routed from the dll into the logic array. you can also bypass the dll and send the dqs delay settings from the logic array to the dqs logic block. stratix ii and stratix ii gx devices support dqsn pins. the dqs/dq groups now support 4, 9, 18, and 36 bus modes. the dqs pins have been enhanced with the dqs postamble circuitry. conclusion stratix ii and stratix ii gx devices support sdr sdram, ddr sdram, ddr2 sdram, rldram ii, and qd rii sram external memories. stratix ii and stratix ii gx devices feature high-speed interfaces that transfer data between external me mory devices at up to 300 mhz/600 mbps. dqs phase-shift circuitry an d dqs logic blocks within the stratix ii and stratix ii gx devices allo w you to fine-tune the phase shifts for the input clocks or strobes to pr operly align clock edges as needed to capture data.
altera corporation 3?39 january 2008 stratix ii device handbook, volume 2 external memory interfaces in stratix ii and stratix ii gx devices referenced documents this chapter references the following documents: an 325: interfacing rldram ii with stratix ii & stratix gx devices an 326: interfacing qdrii & qdrii+ sr am with stratix i i, stratix, & stratix gx devices an 327: interfacing ddr sdra m with stratix ii devices an 328: interfacing ddr2 sd ram with stratix ii devices dc & switching characterist ics of stratix iii devices chapter in volume 2 of the stratix iii device handbook document revision history table 3?11 shows the revision history for this chapter. table 3?11. document revision history date and document version changes made summary of changes january 2008, v4.5 added the ?referenced documents? section. ? minor text edits. no change for the stratix ii gx device handbook only: formerly chapter 8. the chapter number changed due to the addition of the stratix ii gx dynamic reconfiguration chapter. no content change. ? may 2007, v4.4 updated the ?phase offset control? section. ? updated figure 3?2 .? updated ta b l e 3 ? 1 .? added table 3?4 and table 3?6 .? updated note (1) to figure 3?10 .? february 2007 v4.3 added the ?document revision history? section to this chapter. ? april 2006, v4.2 chapter updated as part of the stratix ii device handbook update. ? no change formerly chapter 7. chapter number change only due to chapter addition to section i in february 2006; no content change. ? december 2005 v4.1 chapter updated as part of the stratix ii device handbook update. ? october 2005 v4.0 added chapter to the stratix ii gx device handbook . ?
3?40 altera corporation stratix ii device handbook, volume 2 january 2008 document revision history
altera corporation section iii?1 preliminary section iii. i/o standards this section provides information on stratix ? ii single-ended, voltage- referenced, and differential i/o standards. this section contains the following chapters: chapter 4, selectable i/o standards in stratix ii and stratix ii gx devices chapter 5, high-speed differential i/o interfaces with dpa in stratix ii and stratix ii gx devices revision history refer to each chapter for its own specific revision history. for information on when each chapter was updated, refer to the chapter revision dates section, which appears in the full handbook.
section iii?2 altera corporation preliminary i/o standards stratix ii device handbook, volume 2
altera corporation 4?1 january 2008 4. selectable i/o standards in stratix ii and stratix ii gx devices introduction this chapter provides guidelines for using industry i/o standards in stratix ? ii and stratix ii gx devices, including: i/o features i/o standards external memory interfaces i/o banks design considerations stratix ii and stratix ii gx i/o features stratix ii and the stratix ii gx devices contain an abundance of adaptive logic modules (alms), embedded memory, high-bandwidth digital signal processing (dsp) blocks, and extensive routing resources, all of which can operate at very high core speed. stratix ii and stratix ii gx devices i /o structure is designed to ensure that these internal capabilities are fully utilized. there are numerous i/o features to assist in high-speed data transfer into and out of the device including: single-ended, non-voltage-referenc ed and voltage-referenced i/o standards high-speed differential i/o standards featuring serializer/deserializer (serdes), dynamic phase alignment (dpa), capable of 1 gigabit per second (gbps) performance for low-voltage differential signaling (lvds), hy pertransport technology, hstl, sstl, and lvpecl 1 hstl and sstl i/o standards are used only for pll clock inputs and outputs in diff erential mode. lvpecl is supported on clock input and outputs of the top and bottom i/o banks. double data rate (ddr) i/o pins programmable output drive streng th for voltage-referenced and non-voltage-referenced si ngle-ended i/o standards programmable bus-hold programmable pull-up resistor open-drain output on-chip series termination on-chip parallel termination sii52004-4.6
4?2 altera corporation stratix ii device handbook, volume 2 january 2008 stratix ii and stratix ii g x i/o standards support on-chip differential termination peripheral component interco nnect (pci) clamping diode hot socketing f for a detailed description of each i/o feature, refer to the stratix ii architecture chapter in volume 1 of the stratix ii device handbook or the stratix ii gx architecture chapter in volume 1 of the stratix ii gx device handbook. stratix ii and stratix ii gx i/o standards support stratix ii and stratix ii gx devices suppo rt a wide range of industry i/o standards. table 4?1 shows which i/o standards stratix ii devices support as well as typical applications. table 4?1. stratix ii and stratix ii gx i/ o standard applications (part 1 of 2) i/o standard application lvttl general purpose lvcmos general purpose 2.5 v general purpose 1.8 v general purpose 1.5 v general purpose 3.3-v pci pc and embedded system 3.3-v pci-x pc and embedded system sstl-2 class i ddr sdram sstl-2 class ii ddr sdram sstl-18 class i ddr2 sdram sstl-18 class ii ddr2 sdram 1.8-v hstl class i qdrii sram/rldram ii/sram 1.8-v hstl class ii qdrii sram/rldram ii/sram 1.5-v hstl class i qdrii sram/sram 1.5-v hstl class ii qdrii sram/sram 1.2-v hstl general purpose differential sstl-2 class i ddr sdram differential sstl-2 class ii ddr sdram differential sstl-18 class i ddr2 sdram differential sstl-18 class ii ddr2 sdram 1.8-v differential hstl class i clock interfaces 1.8-v differential hstl class ii clock interfaces 1.5-v differential hstl class i clock interfaces
altera corporation 4?3 january 2008 stratix ii device handbook, volume 2 selectable i/o standards in stratix ii and stratix ii gx devices single-ended i/o standards in non-voltage-referenced single-ended i/o standards, the voltage at the input must be above a set voltage to be considered ?on? (high, or logic value 1) or below another voltage to be considered ?off? (low, or logic value 0). voltages between the limits are undefined logically, and may fall into either a logic value 0 or 1. the non-voltage-referenced single-ended i/o standards supported by stratix ii and stratix ii gx devices are: low-voltage transistor-transistor logic (lvttl) low-voltage complementary metal-oxide semiconductor (lvcmos) 1.5 v 1.8 v 2.5 v 3.3-v pci 3.3-v pci-x voltage-referenced, single-ended i/o standards provide faster data rates. these standards use a constant reference voltage at the input levels. the incoming signals are compared with this constant voltage and the difference between the two defines ?on? and ?off? states. 1 stratix ii and stratix ii gx devices support stub series terminated logic (sstl) and high-speed transceiver logic (hstl) voltage-referenced i/o standards. lvttl the lvttl standard is formulated under eia/jedec standard, jesd8-b (revision of jesd8-a): interface standard for nominal 3-v/3.3-v supply digital integrated circuits. the standard defines dc interface parameters for di gital circuits operating from a 3.0- or 3.3-v power supply and driving or being driven by lvttl-compatible devices. th e 3.3-v lvttl standard is a 1.5-v differential hstl class ii clock interfaces lvds high-speed communications hypertransport? technology pcb interfaces differential lvpecl video graphics and clock distribution table 4?1. stratix ii and stratix ii gx i/ o standard applications (part 2 of 2) i/o standard application
4?4 altera corporation stratix ii device handbook, volume 2 january 2008 stratix ii and stratix ii g x i/o standards support general-purpose, single-ended standard used for 3.3-v applications. this i/o standard does not requir e input reference voltages (v ref ) or termination voltages (v tt ). 1 stratix ii and stratix ii gx devices support both input and output levels for 3.3-v lvttl operation. stratix ii stratix ii gx devices support a v ccio voltage level of 3.3 v ? 5% as specified as the narrow rang e for the voltage supply by the eia/jedec standard. lvcmos the lvcmos standard is formulated under eia/jedec standard, jesd8-b (revision of jesd8-a): interface standard for nominal 3-v/3.3-v supply digital integrated circuits. the standard defines dc interface parameters for di gital circuits operating from a 3.0- or 3.3-v power supply and driving or being driven by lvcmos-compatible devices. the 3.3-v lvcmos i/o standard is a general-purpose, single-ended stan dard used for 3.3-v applications. while lvcmos has its own output specification, it specifies the same input voltage requiremen ts as lvttl. these i/o standards do not require v ref or v tt . 1 stratix ii and stratix ii gx devices support both input and output levels for 3.3-v lvcmos operation. stratix ii and stratix ii gx devices support a v ccio voltage level of 3.3 v ? 5% as specified as the narrow ra nge for the voltage supply by the eia/jedec standard. 2.5 v the 2.5-v i/o standard is formul ated under eia/jedec standard, eia/jesd8-5: 2.5-v 0.2-v (norma l range), and 1.8-v ? 2.7-v (wide range) power supply voltage and interface standard for non-terminated digital integrated circuit. the standard defines the dc inte rface parameters for high-speed, low-voltage, non-terminated digital circuits driving or being driven by other 2.5-v devices. this standard is a general-purpose, single-ended standard used for 2.5-v applications. it does not require the use of a v ref or a v tt .
altera corporation 4?5 january 2008 stratix ii device handbook, volume 2 selectable i/o standards in stratix ii and stratix ii gx devices 1 stratix ii and stratix ii gx devices support both input and output levels for 2.5-v operation with v ccio voltage level support of 2.5 v 5%, which is narrower than defined in the normal range of the eia/jedec standard. 1. 8 v the 1.8-v i/o standard is formul ated under eia/jedec standard, eia/jesd8-7: 1.8-v 0.15-v (normal range), and 1.2-v ? 1.95-v (wide range) power supply voltage and interface standard for non-terminated digital integrated circuit. the standard defines the dc inte rface parameters for high-speed, low-voltage, non-terminated digital circuits driving or being driven by other 1.8-v devices. this standard is a general-purpose, single-ended standard used for 1.8-v applications. it does not require the use of a v ref or a v tt . 1 stratix ii and stratix ii gx devices support both input and output levels for 1.8-v operation with v ccio voltage level support of 1.8 v 5%, which is narrower than defined in the normal range of the eia/jedec standard. 1.5 v the 1.5-v i/o standard is formul ated under eia/jedec standard, jesd8-11: 1.5-v 0.1-v (normal range) and 0.9-v ? 1.6-v (wide range) power supply voltage and interface standard for non-terminated digital integrated circuit. the standard defines the dc inte rface parameters for high-speed, low-voltage, non-terminated digital circuits driving or being driven by other 1.5-v devices. this standard is a general-purpose, single-ended standard used for 1.5-v applications. it does not require the use of a v ref or a v tt . 1 stratix ii and stratix ii gx devices support both input and output levels for 1.5-v operation v ccio voltage level support of 1.5 v 5%, which is narrower th an defined in the normal range of the eia/jedec standard. 3.3-v pci the 3.3-v pci i/o standard is formulated under pci local bus specification revision 2.2 developed by the pci special interest group (sig).
4?6 altera corporation stratix ii device handbook, volume 2 january 2008 stratix ii and stratix ii g x i/o standards support the pci local bus specification is used for applications that interface to the pci local bus, which provides a processor-independent data path between highly integrated peripheral controller components, peripheral add-in boards, and processor/memory systems. the conventional pci specification revision 2.2 define s the pci hardware environment including the protocol, electrical, mechanical, and configuration specifications for the pci devices an d expansion boards. this standard requires 3.3-v v ccio. stratix ii and stratix ii gx devices are fully compliant with the 3.3-v pci local bus specification revision 2.2 and meet 64-bit/66-mhz operating frequency and timing requirements. 1 the 3.3-v pci standard does not require input reference voltages or board terminations. stratix ii and stratix ii gx devices support both input and output levels. 3.3-v pci-x the 3.3-v pci-x i/o standard is formulated under pci-x local bus specification revision 1.0a developed by the pci sig. the pci-x 1.0 standard is used for a pplications that interface to the pci local bus. the standard enables the design of systems and devices that operate at clock speeds up to 133 mhz, or 1 gbps for a 64-bit bus. the pci-x 1.0 protocol enhancements enab le devices to operate much more efficiently, providing more usable bandwidth at any clock frequency. by using the pci-x 1.0 standard, you can design devices to meet pci-x 1.0 requirements and operate as conven tional 33- and 66-mhz pci devices when installed in those systems. this standard requires 3.3-v v ccio . stratix ii and stratix ii gx devices are fully compliant with the 3.3-v pci-x specification revision 1.0a and meet the 133-mhz operating frequency and timing requirements. the 3.3-v pci-x standard does not require input reference voltages or board terminations. 1 stratix ii and stratix ii gx devices support both input and output levels operation. sstl-2 class i and sstl-2 class ii the 2.5-v sstl-2 standard is fo rmulated under jedec standard, jesd8-9a: stub series terminat ed logic for 2.5-v (sstl_2). the sstl-2 i/o standard is a 2.5-v memory bus standard used for applications such as high-speed ddr sdram interfaces. this standard defines the input and output specificat ions for devices that operate in the sstl-2 logic switching range of 0.0 to 2.5 v. this standard improves
altera corporation 4?7 january 2008 stratix ii device handbook, volume 2 selectable i/o standards in stratix ii and stratix ii gx devices operation in conditions where a bus must be isolated from large stubs. sstl-2 requires a 1.25-v v ref and a 1.25-v v tt to which the series and termination resistors are connected ( figures 4?1 and 4?2 ). 1 stratix ii and stratix ii gx devices support both input and output levels operation. figure 4?1. 2.5-v sstl class i termination figure 4?2. 2.5-v sstl class ii termination sstl-1 8 class i and sstl-1 8 class ii the 1.8-v sstl-18 standard is fo rmulated under jedec standard, jesd8-15: stub series terminat ed logic for 1.8-v (sstl_18). the sstl-18 i/o standard is a 1.8- v memory bus standard used for applications such as high-speed ddr 2 sdram interfaces. this standard is similar to sstl-2 and defines input and output specifications for devices that are designed to operate in the sstl-18 logic switching range 0.0 to 1.8 v. sstl-18 requires a 0.9-v v ref and a 0.9-v v tt to which the series and termination resistors are connected. there are no class definitions for the sstl-18 standard in the jedec specification. the specification of this i/o standard is based on an environment that consists of both series and parallel terminating resistors. altera provides solutions to two derived applications in jedec specification, and names them class i and class ii to be consistent with other sstl standards. figures 4?3 and 4?4 show sstl-18 class i and ii termination, respectively. ou tp u t bu ffer in p u t bu ffer v tt = 1.25 v 50 25 z = 50 v ref = 1.25 v output buffer input buffer v tt = 1.25 v 50 v tt = 1.25 v 50 25 z = 50 v ref = 1.25 v
4?8 altera corporation stratix ii device handbook, volume 2 january 2008 stratix ii and stratix ii g x i/o standards support 1 stratix ii and stratix ii gx devices support both input and output levels operation. figure 4?3. 1.8-v sstl class i termination figure 4?4. 1.8-v sstl class ii termination 1. 8 -v hstl class i and 1. 8 -v hstl class ii the hstl standard is a techno logy-independent i/o standard developed by jedec to provide voltage scalability. it is used for applications designed to operate in th e 0.0- to 1.8-v hstl logic switching range such as quad data rate (qdr) memory clock interfaces. although jedec specifies a maximum v ccio value of 1.6 v, there are various memory chip vendors with hstl standards that require a v ccio of 1.8 v. stratix ii and stratix ii gx devices support interfaces to chips with v ccio of 1.8 v for hstl. figures 4?5 and 4?6 show the nominal v ref and v tt required to track the higher value of v ccio . the value of v ref is selected to provide optimum noise margin in the system. 1 stratix ii and stratix ii gx devices support both input and output levels operation. output buffer input buffer v tt = 0.9 v 50 25 z = 50 v ref = 0.9 v output buffer input buffer v tt = 0.9 v 50 v tt = 0.9 v 50 25 z = 50 v ref = 0.9 v
altera corporation 4?9 january 2008 stratix ii device handbook, volume 2 selectable i/o standards in stratix ii and stratix ii gx devices figure 4?5. 1.8-v hstl class i termination figure 4?6. 1.8-v hstl class ii termination 1.5-v hstl class i and 1.5-v hstl class ii the 1.5-v hstl standard is for mulated under eia/jedec standard, eia/jesd8-6: a 1.5-v output buff er supply voltage based interface standard for digital integrated circuits. the 1.5-v hstl i/o standard is used for applications designed to operate in the 0.0- to 1.5-v hstl logic nomi nal switching range. this standard defines single-ended input and output specifications for all hstl-compliant digital integrated ci rcuits. the 1.5-v hstl i/o standard in stratix ii and stratix ii gx devices are compatible with the 1.8-v hstl i/o standard in apex? 20ke, ap ex 20kc, and in stratix ii and stratix ii gx devices themselves beca use the input and output voltage thresholds are compatible ( figures 4?7 and 4?8 ). 1 stratix ii and stratix ii gx devices support both input and output levels with v ref and v tt . output buffer input buffer v tt = 0.9 v 50 z = 50 v ref = 0.9 v output buffer input buffer v tt = 0.9 v 50 z = 50 v ref = 0.9 v v tt = 0.9 v 50
4?10 altera corporation stratix ii device handbook, volume 2 january 2008 stratix ii and stratix ii g x i/o standards support figure 4?7. 1.5-v hstl class i termination figure 4?8. 1.5-v hstl class ii termination 1.2-v hstl although there is no eia/jedec stan dard available for the 1.2-v hstl standard, altera supports it for applications that operate in the 0.0 to 1.2-v hstl logic nominal switching ra nge. 1.2-v hstl can be terminated through series or parallel on-chip termination (oct). figure 4?9 shows the termination scheme. figure 4?9. 1.2-v hstl termination differential i/o standards differential i/o standards are used to achieve even faster data rates with higher noise immunity. apart from lvds, lvpecl, and hypertransport technology, stratix ii and stratix ii gx devices also support differential versions of sstl and hstl standards. output buffer input buffer v tt = 0.75 v 50 z = 50 v ref = 0.75 v output buffer input buffer v tt = 0.75 v 50 v tt = 0.75 v 50 z = 50 v ref = 0.75 v ou tp u t bu ffer in p u t bu ffe r z = 50 v ref = 0.6 v oct
altera corporation 4?11 january 2008 stratix ii device handbook, volume 2 selectable i/o standards in stratix ii and stratix ii gx devices f for detailed information on differential i/o standards, refer to the high-speed differential i/ o interfaces with dpa in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii device handbook or high-speed differential i/ o interfaces with dpa in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook . differential sstl-2 class i and differential sstl-2 class ii the 2.5-v differential sstl-2 stan dard is formulated under jedec standard, jesd8-9a: stub series te rminated logic for 2.5-v (sstl_2). this i/o standard is a 2.5-v standa rd used for applications such as high-speed ddr sdram clock interfaces. this standard supports differential signals in systems using the sstl-2 standard and supplements the sstl-2 standard for differential clocks. stratix ii and stratix ii gx devices support b oth input and output levels. figures 4?10 and 4?11 shows details on differ ential sstl-2 termination. 1 stratix ii and stratix ii gx devices support differential sstl-2 i/o standards in pseudo-differential mode, which is implemented by using two sstl-2 single-ended buffers. the quartus ? ii software only supports pseudo-differential standards on the inclk , fbin and extclk ports of enhanced pll, as well as on dqs pins when dqs megafunction (altdq s, bidirectional data strobe) is used. two single-ended output buff ers are automatically programmed to have opposite polarity so as to implement a pseudo-differential output. a proper v ref voltage is required for the tw o single-ended input buffers to implement a pseudo-differential input. in this case, only the positive polarity input is used in the speed path while the nega tive input is not connected internally. in other word s, only the non-inverted pin is required to be specified in your design, while the quartus ii software automatically generates the inverted pin for you. although the quartus ii software do es not support pseudo-differential sstl-2 i/o standards on the left an d right i/o banks, you can implement these standards at these banks. you ne ed to create two pins in the designs and configure the pins with single-e nded sstl-2 standards. however, this is limited only to pins that su pport the differential pin-pair i/o function and is dependent on the si ngle-ended sstl-2 standards support at these banks.
4?12 altera corporation stratix ii device handbook, volume 2 january 2008 stratix ii and stratix ii g x i/o standards support figure 4?10. differential sstl-2 class i termination figure 4?11. differential sstl- 2 class ii termination differential sstl-1 8 class i and differential sstl-1 8 class ii the 1.8-v differential sstl-18 stan dard is formulated under jedec standard, jesd8-15: stub series te rminated logic for 1.8-v (sstl_18). the differential sstl- 18 i/o standard is a 1. 8-v standard used for applications such as high-speed ddr 2 sdram interfaces. this standard supports differential signals in syst ems using the sstl-18 standard and supplements the sstl-18 standard for differential clocks. 1 stratix ii and stratix ii gx devices support both input and output levels operation. differential transmitter differential receiver z 0 = 50 50 50 z 0 = 50 v tt = 1.25 v v tt = 1.25 v 25 25 differential transmitter differential receiver z 0 = 50 50 50 z 0 = 50 v tt = 1.25 v v tt = 1.25 v 50 50 v tt = 1.25 v v tt = 1.25 v 25 25
altera corporation 4?13 january 2008 stratix ii device handbook, volume 2 selectable i/o standards in stratix ii and stratix ii gx devices figures 4?12 and 4?13 shows details on differen tial sstl-18 termination. stratix ii and stratix ii gx devices support differential sstl-18 i/o standards in pseudo-differential mode, which is implemented by using two sstl-18 single-ended buffers. the quartus ii software only support s pseudo-differential standards on the inclk , fbin and extclk ports of enhanced pll, as well as on dqs pins when dqs megafunction (altdq s, bidirectional data strobe) is used. two single-ended output buff ers are automatically programmed to have opposite polarity so as to implement a pseudo-differential output. a proper v ref voltage is required for the tw o single-ended input buffers to implement a pseudo-differential input. in this case, only the positive polarity input is used in the speed path while the nega tive input is not connected internally. in other word s, only the non-inverted pin is required to be specified in your design, while the quartus ii software automatically generates the inverted pin for you. although the quartus ii software do es not support pseudo-differential sstl-18 i/o standards on the left and right i/o banks, you can implement these standards at these bank s. you need to create two pins in the designs and configure the pins wi th single-ended sstl-18 standards. however, this is limited only to pins that support the differential pin-pair i/o function and is dependent on the single-ended sstl-18 standards support at these banks. figure 4?12. differential sstl-18 class i termination differential transmitter differential receiver z 0 = 50 50 50 z 0 = 50 v tt = 0.9 v v tt = 0.9 v 25 25
4?14 altera corporation stratix ii device handbook, volume 2 january 2008 stratix ii and stratix ii g x i/o standards support figure 4?13. differential sstl- 18 class ii termination 1. 8 -v differential hstl class i and 1. 8 -v differential hstl class ii the 1.8-v differential hstl specification is the same as the 1.8-v single-ended hstl specification. it is used for applications designed to operate in the 0.0- to 1.8-v hstl logic switching range such as qdr memory clock interfaces. stratix ii and stratix ii gx devices support both input and output levels operation. figures 4?14 and 4?15 show details on 1.8-v differential hstl termination. stratix ii and stratix ii gx devices support 1.8-v differential hstl i/o standards in pseudo-differential mode, which is implemented by using two 1.8-v hstl sing le-ended buffers. the quartus ii software only support s pseudo-differential standards on the inclk , fbin and extclk ports of enhanced pll, as well as on dqs pins when dqs megafunction (altdq s, bidirectional data strobe) is used. two single-ended output buff ers are automatically programmed to have opposite polarity so as to implement a pseudo-differential output. a proper v ref voltage is required for the tw o single-ended input buffers to implement a pseudo-differential input. in this case, only the positive polarity input is used in the speed path while the nega tive input is not connected internally. in other word s, only the non-inverted pin is required to be specified in your design, while the quartus ii software automatically generates the inverted pin for you. although the quartus ii software does not support 1.8-v pseudo-differential hstl i/o standards on left/right i/o banks, you can implement these standards at these bank s. you need to create two pins in the designs and configure the pins with single-ended 1.8-v hstl standards. however, this is limited only to pins that support the differential pin-pair i/o function an d is dependent on the single-ended 1.8-v hstl standards support at these banks. differential transmitter differential receiver z 0 = 50 50 50 z 0 = 50 v tt = 0.9 v v tt = 0.9 v 50 50 v tt = 0.9 v v tt = 0.9 v 25 25
altera corporation 4?15 january 2008 stratix ii device handbook, volume 2 selectable i/o standards in stratix ii and stratix ii gx devices figure 4?14. 1.8-v differential hstl class i termination figure 4?15. 1.8-v differential hstl class ii termination 1.5-v differential hstl class i and 1.5-v differential hstl class ii the 1.5-v differential hstl standa rd is formulated under eia/jedec standard, eia/jesd8-6: a 1.5-v output buffer supply voltage based interface standard for digi tal integrated circuits. the 1.5-v differential hstl specification is the same as the 1.5-v single-ended hstl specification. it is used for applications designed to operate in the 0.0- to 1.5-v hstl logic switching range, such as qdr memory clock interfaces. stratix ii and stratix ii gx devices support both input and output levels operation. figures 4?16 and 4?17 show details on the 1.5-v differential hstl termination. stratix ii and stratix ii gx devices support 1.5-v differential hstl i/o standards in pseudo-differential mode, which is implemented by using two 1.5-v hstl sing le-ended buffers. differential transmitter differential receiver z 0 = 50 50 50 z 0 = 50 v tt = 0.9 v v tt = 0.9 v differential transmitter differential receiver z 0 = 50 50 50 z 0 = 50 v tt = 0.9 v v tt = 0.9 v 50 50 v tt = 0.9 v v tt = 0.9 v
4?16 altera corporation stratix ii device handbook, volume 2 january 2008 stratix ii and stratix ii g x i/o standards support the quartus ii software only support s pseudo-differential standards on the inclk , fbin and extclk ports of enhanced pll, as well as on dqs pins when dqs megafunction (altdq s, bidirectional data strobe) is used. two single-ended output buff ers are automatically programmed to have opposite polarity so as to implement a pseudo-differential output. a proper v ref voltage is required for the tw o single-ended input buffers to implement a pseudo-differential input. in this case, only the positive polarity input is used in the speed path while the nega tive input is not connected internally. in other word s, only the non-inverted pin is required to be specified in your design, while the quartus ii software automatically generates the inverted pin for you. although the quartus ii software does not support 1.5-v pseudo-differential hstl i/o standards on left/right i/o banks, you can implement these standards at these bank s. you need to create two pins in the designs and configure the pins with single-ended 1.5-v hstl standards. however, this is limited only to pins that support the differential pin-pair i/o function an d is dependent on the single-ended 1.8-v hstl standards support at these banks. figure 4?16. 1.5-v differential hstl class i termination differential transmitter differential receiver z 0 = 50 50 50 z 0 = 50 v tt = 0.75 v v tt = 0.75 v
altera corporation 4?17 january 2008 stratix ii device handbook, volume 2 selectable i/o standards in stratix ii and stratix ii gx devices figure 4?17. 1.5-v differential hstl class ii termination lvds the lvds standard is formulated under ansi/tia/eia standard, ansi/tia/eia-644: electrical ch aracteristics of low voltage differential signalin g interface circuits. the lvds i/o standard is a differen tial high-speed, low-voltage swing, low-power, general-purpose i/o interface standard. in stratix ii devices, the lvds i/o standard requires a 2.5-v v ccio level for the side i/o pins in banks 1, 2, 5, and 6. the to p and bottom banks have different v ccio requirements for the lvds i/o stan dard. the lvds clock i/o pins in banks 9 through 12 require a 3.3-v v ccio level. within these banks, the pll[5,6,11,12]_out[1,2] pins support output only lvds operations. the pll[5,6,11,12]_fb/out2 pins support lvds input or output operations but cannot be configured for bidirectional lvds operations. the lvds clock input pins in banks 4, 5, 7, and 8 use v ccint and have no dependency on the v ccio voltage level. this standard is used in applications requiring high-ba ndwidth data transfer, backplane drivers, and clock distribution . the ansi/tia/eia-644 standard specifies lvds transmitters and receivers capable of operating at recommended maximum data signalin g rates of 655 megabit per second (mbps). however, devices can operat e at slower speeds if needed, and there is a theoretical maximum of 1.923 gbps. stratix ii and stratix ii gx devices are capable of running at a ma ximum data rate of 1 gbps and still meet the ansi/tia /eia-644 standard. because of the low-voltage swing of the lvds i/o standard, the electromagnetic interfer ence (emi) effects are much smaller than complementary metal-oxide semiconductor (cmos), transistor-to-transistor logic (ttl), and positi ve (or psuedo) emitter coupled logic (pecl). this low emi makes lvds ideal for applications differential transmitter differential receiver z 0 = 50 50 50 z 0 = 50 v tt = 0.75 v v tt = 0.75 v 50 50 v tt = 0.75 v v tt = 0.75 v
4?18 altera corporation stratix ii device handbook, volume 2 january 2008 stratix ii and stratix ii g x i/o standards support with low emi requirements or nois e immunity requirements. the lvds standard does not require an input reference voltage. however, it does require a 100- ? termination resistor between the two signals at the input buffer. stratixii and stratixiigx devices provide an optional 100- ? differential lvds termination resi stor in the device using on-chip differential termination. stratix ii and stratix ii gx devices support both input and output levels operation. differential lvpecl the low-voltage positive (or pseudo) emitter coupled logic (lvpecl) standard is a differential interf ace standard requiring a 3.3-v v ccio . the standard is used in applications involving video graphics, telecommunications, data communicati ons, and clock distribution. the high-speed, low-voltage swing lvpecl i/o standard uses a positive power supply and is similar to lvds. however, lvpecl has a larger differential output voltage swing th an lvds. the lvpecl standard does not require an input reference voltage, but it does require a 100- ? termination resistor between the two signals at the input buffer. figures 4?18 and 4?19 show two alternate termination schemes for lvpecl. 1 stratix ii and stratix ii gx devices support both input and output levels operation. figure 4?18. lvpecl dc coupled termination figure 4?19. lvpecl ac coupled termination output buffer input buffer 100 z = 50 z = 50 output buffer input buffer 100 z = 50 z = 50 v ccio v ccio r2 r2 r1 r1 10 to 100 nf 10 to 100 nf
altera corporation 4?19 january 2008 stratix ii device handbook, volume 2 selectable i/o standards in stratix ii and stratix ii gx devices hypertransport technology the hypertransport standard is formulated by the hypertransport consortium. the hypertransport i/o standard is a differential high-speed, high-performance i/o interface stan dard requiring a 2.5- or 3.3-v v ccio . this standard is used in applications such as high-performance networking, telecommunications, embedded systems, consumer electronics, and internet connectivi ty devices. the hypertransport i/o standard is a point-to-point standard in which each hypertransport bus consists of two point-to-point unidirecti onal links. each link is 2 to 32 bits. the hypertransport standard does not require an input reference voltage. however, it does require a 100- ? termination resistor between the two signals at the input buffer. figure 4?20 shows hypertransport termination. stratix ii and stratix ii gx devices include an optional 100- ? differential hypertransport terminat ion resistor in the device using on-chip differential termination. 1 stratix ii and stratix ii gx devices support both input and output levels operation. figure 4?20. hypertransport termination stratix ii and stratix ii gx external memory interface the increasing demand for higher-per formance data processing systems often requires memory-intensive applications. stratix ii and stratix ii gx devices can interface with many types of external memory. f refer to the external memory interfaces in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii device handbook or the external memory interfaces in strati x ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook for more information on the external memory interface support in st ratix ii or stratix ii gx devices. output buffer input buffer 100 z = 50 z = 50
4?20 altera corporation stratix ii device handbook, volume 2 january 2008 stratix ii and stratix ii gx i/o banks stratix ii and stratix ii gx i/o banks stratix ii devices have eight gene ral i/o banks and four enhanced phase-locked loop (pll) exte rnal clock output banks ( figure 4?21 ) . i/o banks 1, 2, 5, and 6 are on the left or right sides of the device and i/o banks 3, 4, and 7 through 12 are at the top or bottom of the device. figure 4?21. strati x ii i/o banks notes (1) , (2) , (3) , (4) , (5) , (6) , (7) notes to figure 4?21 : (1) figure 4?21 is a top view of the silicon die that corresponds to a reverse view for flip-chip packages. it is a graphical representation only. refer to the pin list and quartus ii software for exact locations. (2) depending on the size of the device, differe nt device members have different numbers of v ref groups. (3) banks 9 through 12 are enhanced pll external cloc k output banks. these pll banks utilize the adjacent v ref group when voltage-referenced standards ar e implemented. for example, if an sstl input is implemented in pll bank 10, the voltage level at vrefb7 is the reference voltage level for the sstl input. (4) differential hstl and differential sstl standards are available for bidirectional operations on dqs pin and input-only operations on pll clock input pins; lvds, lvpecl, and hypertransport standards are available for input-only operations on pll clock input pins. refer to the ?differential i/o standards? on page 4?10 for more details. (5) quartus ii software does not support differential sstl an d differential hstl standard s at left/right i/o banks. refer to the ?differential i/o standards? on page 4?10 if you need to implement these standards at these i/o banks. (6) banks 11 and 12 are available only in ep2s60, ep2s90, ep2s130, and ep2s180 devices. (7) plls 7, 8, 9 10, 11, and 12 are available only in ep2s60, ep2s90, ep2s130, and ep2s180 devices. bank 3 bank 4 bank 11 bank 9 pll11 pll5 pll7 pll1 pll2 pll4 pll3 pll10 i/o banks 7, 8, 10 & 12 support all single-ended i/o standards and differential i/o standards except for hypertransport technology for both input and output operations. i/o banks 3, 4, 9 & 11 support all single-ended i/o standards and differential i/o standards except for hypertransport technology for both input and output operations. vref0b3 vref1b3 vref2b3 vref3b3 vref4b3 vref0b4 vref1b4 vref2b4 vref3b4 vref4b4 bank 8 bank 7 bank 12 bank 10 pll12 pll6 pll8 pll9 vref4b8 vref3b8 vref2b8 vref1b8 vref0b8 vref4b7 vref3b7 vref2b7 vref1b7 vref0b7 vref3b 2 vref2b2 vref1b2 vref0b2 bank 2 vref3b1 vref2b1 vref1b1 vref0b1 bank 1 vref1b 5 vref2b5 vref3b5 vref4b5 bank 5 vref1b6 vref2b6 vref3b6 vref4b6 bank 6 vref4b2 vref0b5 vref4b1 vref0b6 dqs4t dqs3t dqs2t dqs1t dqs0t dqs4b dqs3b dqs2b dqs1b dqs0b dqs8b dqs7b dqs6b dqs5b dqs8t dqs7t dqs6t dqs5t this i/o bank supports lvds and lvpecl standards for input clock operations. differential hstl and differential sstl standards are supported for both input and output operations. this i/o bank supports lvds and lvpecl standards for input clock operations. differential hstl and differential sstl standards are supported for both input and output operations. this i/o bank supports lvds and lvpecl standards for input clock operations. differential hstl and differential sstl standards are supported for both input and output operations. this i/o bank supports lvds and lvpecl standards for input clock operations. differential hstl and differential sstl standards are supported for both input and output operations. i/o banks 1, 2, 5 & 6 support lvttl, lvcmos, 2.5-v, 1.8-v, 1.5-v, sstl-2, sstl-18 class i, hstl-18 class i, hstl-15 class i, lvds, and hypertransport standards for input and output operations. hstl-18 class ii, hstl-15-class ii, sstl-18 class ii standards are only supported for input operations.
altera corporation 4?21 january 2008 stratix ii device handbook, volume 2 selectable i/o standards in stratix ii and stratix ii gx devices stratix ii gx devices have 6 general i/o banks and 4 enhanced phase-locked loop (pll) exte rnal clock output banks ( figure 4?22 ). i/o banks 9 through 12 are enhanced pll ex ternal clock output banks located on the top and bottom of the device. figure 4?22. stratix i i gx i/o banks notes (1) , (2) , (3) , (4) notes to figure 4?22 : (1) figure 4?22 is a top view of the silicon die which corresponds to a reverse view for flip-chip packages. it is a graphical representation only. (2) depending on size of the de vice, different device members have different number of v ref groups. refer to the pin list and the quartus ii software for exact locations. (3) banks 9 through 12 are enhanced pll external clock output banks. (4) horizontal i/o banks feature transceiver and dpa circuitry for high speed differential i/o standards. refer to the high-speed differential i/o interfaces with dpa in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook , or the stratix ii gx transceiver user guide (volume 1) of the stratix ii gx device handbook for more information on differential i/o standards. (5) quartus ii software does not support differential sstl an d differential hstl standard s at left/right i/o banks. refer to the ?differential i/o standards? on page 4?10 if you need to implement these standards at these i/o banks. (6) banks 11 and 12 are available only in ep2sgx60c/d/e, ep2sgx90e/f, and ep2sgx130g. (7) plls 7,8,11, and 12 are available only in ep2sgx60c/d/e, ep2sgxe/f, and ep2sgx130g. i/o b a nk s 3, 4, 9 & 11 s u pp o rt a ll s in g l e - e n ded i/o sta n dards f o r b o t h in p u t a n d ou tp u t o perat ion. all d i ffere n t i a l i/o sta n dards are s u pp o rted f o r b o t h in p u t a n d ou tp u t o perat ion at i/o ba nk s 9 & 1 0 . i/o b a nk s 7, 8, 1 0 a n d 12 s u pp o rt a ll s in g l e - e n ded i/o sta n dards f o r b o t h in p u t a n d ou tp u t o perat ion. all d i ffere n t i a l i/o sta n dards are s u pp o rted f o r b o t h in p u t a n d ou tp u t o perat ion s at i/o ba nk 1 0 a n d 12. i/o b a nk s 1, & 2, s u pp o rt lvttl, lv c mos, 2.5 -v, 1.9 -]v, 1.5 -v, sstl -2, sstl-18 c l ass i, lv d s, pse u d o- d i ffere n t i a l sstl -2, a n d pse u d o- d i ffere n t i a l sstl-18 c l ass i sta n dards f o r b o t h in p u t a n d ou tp u t o perat ion s . hstl, sstl-18 c l ass ii, pse u d o- d i ffere n t i a l hstl, a n d pse u d o- d i ffere n t i a l sstl-18 c l ass ii sta n dards are only s u pp o rted f o r in p u t o perat ion s . (4) dqsx8 dqsx8 dqsx8 dqsx8 dqsx8 pll11 vref0b3 vref1b3 vref2b3 vref3b3 vref4b3 vref0b4 vref1b4 vref2b4 vref3b4 vref4b4 vref4b8 vref3b8 vref2b8 vref1b8 vref0b8 vref4b7 vref3b7 vref2b7 vref1b7 vref0b7 dqsx8 dqsx8 dqsx8 dqsx8 dqsx8 dqsx8 dqsx8 dqsx8 dqsx8 bank 9 bank 11 vref0b2 vref1b2 vref2b2 pll1 pll2 bank 1 bank 2 bank 3 bank 4 bank 8 bank 7 pll7 pll8 pll12 pll5 thi s i/o ba nk s u pp o rts lv d s a n d lvpe c l sta n dards f o r in p u t c lo c k o perat ion s . d i ffere n t i a l hstl a n d d i ffere n t i a l sstl sta n dards are s u pp o rted f o r b o t h in p u t a n d ou tp u t o perat ion s . (3) thi s i/o ba nk s u pp o rts lv d s a n d lvpe c l sta n dards f o r in p u t c lo c k o perat ion. d i ffere n t i a l hstl a n d d i ffere n t i a l sstl sta n dards are s u pp o rted f o r b o t h in p u t a n d ou tp u t o perat ion s . (3) thi s i/o ba nk s u pp o rts lv d s a n d lvpe c l sta n dards f o r in p u t c lo c k o perat ion s . d i ffere n t i a l hstl a n d d i ffere n t i a l sstl sta n dards are s u pp o rted f o r b o t h in p u t a n d ou tp u t o perat ion s . (3) thi s i/o ba nk s u pp o rts lv d s a n d lvpe c l sta n dards f o r in p u t c lo c k o perat ion s . d i ffere n t i a l hstl a n d d i ffere n t i a l sstl sta n dards are s u pp o rted f o r b o t h in p u t a n d ou tp u t o perat ion s . (3) pll6 bank 12 bank 10 vref0b1 vref1b1 vref2b1 vref3b1 vref4b1 bank 15 bank 16 bank 14 bank 13 bank 17 dqsx8 dqsx8 dqsx8 dqsx8 vref4b2 vref3b2
4?22 altera corporation stratix ii device handbook, volume 2 january 2008 stratix ii and stratix ii gx i/o banks programmable i/o standards stratix ii and stratix ii gx device programmable i/o standards deliver high-speed and high-performance so lutions in many complex design systems. this section discusses the i/o standard support in the i/o banks of stratix ii and stratix ii gx devices. regular i/o pins most stratix ii and stratix ii gx devi ce pins are multi-function pins. these pins support regular inputs an d outputs as their primary function, and offer an optional func tion such as dqs, differential pin-pair, or pll external clock outputs. for example, you can configure a multi-function pin in the enhanced pll external cl ock output bank as a pll external clock output when it is not used as a regular i/o pin. 1 i/o pins that reside in pll ba nks 9 through 12 are powered by the vcc_pll < 5, 6, 11, or 12 > _out pins, respectively. the ep2s60f484, ep2s60f780, ep 2s90h484, ep2s90f780, and ep2s130f780 devices do not support plls 11 and 12. therefore, any i/o pins that reside in bank 11 are powered by the vccio3 pin, and any i/o pins that reside in bank 12 are powered by the vccio8 pin. table 4?2 shows the i/o standards support ed when a pin is used as a regular i/o pin in the i/o banks of stratix ii and stratix ii gx devices. table 4?2. stratix ii and stra tix ii gx regular i/o standar ds support (part 1 of 2) i/o standard general i/o bank enhanced pll external clock output bank (2) 123 45 (1) 6 (1) 789101112 lv t t l v v v v v v v v v v v v lv c m o s v v v v v v v v v v v v 2.5 v v v v v v v v v v v v v 1.8 v v v v v v v v v v v v v 1.5 v vvv vvvvvvv vv 3.3-v pci v v v v v v v v 3.3-v pci-x vv vvvvvv sstl-2 class i v v v v v v v v v v v v sstl-2 class ii vvv vvvvvvv vv
altera corporation 4?23 january 2008 stratix ii device handbook, volume 2 selectable i/o standards in stratix ii and stratix ii gx devices sstl-18 class i v v v v v v v v v v v v sstl-18 class ii (3) (3) vv (3) (3) v v v v v v 1.8-v hstl class i vv v v vv v v v v v v 1.8-v hstl class ii (3) (3) v v (3) (3) v v v v v v 1.5-v hstl class i vv v v vv v v v v v v 1.5-v hstl class ii (3) (3) v v (3) (3) v v v v v v 1.2-v hstl vv v differential sstl-2 class i (4) (4) (5) (5) (4) (4) (5) (5) differential sstl-2 class ii (4) (4) (5) (5) (4) (4) (5) (5) differential sstl-18 class i (4) (4) (5) (5) (4) (4) (5) (5) differential sstl-18 class ii (4) (4) (5) (5) (4) (4) (5) (5) 1.8-v differential hstl class i (4) (4) (5) (5) (4) (4) (5) (5) 1.8-v differential hstl class ii (4) (4) (5) (5) (4) (4) (5) (5) 1.5-v differential hstl class i (4) (4) (5) (5) (4) (4) (5) (5) 1.5-v differential hstl class ii (4) (4) (5) (5) (4) (4) (5) (5) lv d s v v (6) (6) v v (6) (6) vvvv hypertransport technology v v v v differential lvpecl (6) (6) (6) (6) vvvv notes to ta b l e 4 ? 2 : (1) this bank is not available in stratix ii gx devices. (2) a mixture of single-ended and differential i/o standard s is not allowed in enhanced pll external clock output bank. (3) this i/o standard is only supported for the input operation in this i/o bank. (4) although the quartus ii software does not support pseu do-differential sstl/hstl i/o standards on the left and right i/o banks, you can implement these standards at these banks. refer to the ?differential i/o standards? on page 4?10 for details. (5) this i/o standard is supported for bo th input and output operations for pins that support the dqs function. refer to the ?differential i/o standards? on page 4?10 for details. (6) this i/o standard is only supported for the input operation for pins that support pll inclk function in this i/o bank. table 4?2. stratix ii and stra tix ii gx regular i/o standar ds support (part 2 of 2) i/o standard general i/o bank enhanced pll external clock output bank (2) 123 45 (1) 6 (1) 789101112
4?24 altera corporation stratix ii device handbook, volume 2 january 2008 stratix ii and stratix ii gx i/o banks clock i/o pins the pll clock i/o pins co nsist of clock inputs ( inclk ), external feedback inputs ( fbin ), and external clock outputs ( extclk ). clock inputs are located at the left and right i/o banks (banks 1, 2, 5, and 6) to support fast plls, and at the top and bottom i/o banks (banks 3, 4, 7, and 8) to support enhanced plls. both exte rnal clock output s and external feedback inputs are located at enhanc ed pll external clock output banks (banks 9, 10, 11, and 12) to support enhanced plls. table 4?3 shows the pll clock i/o support in the i/o banks of stratix ii and stratix ii gx devices. table 4?3. i/o standards supported for strati x ii and stratix ii gx pll pins (part 1 of 2) i/o standard (2) enhanced pll (1) fast pll input output input inclk fbin extclk inclk lv t t l v v v v lv c m o s v v v v 2.5 v v v v v 1.8 v v v v v 1.5 v v v v v 3.3-v pci v v v 3.3-v pci-x v v v sstl-2 class i v v v v sstl-2 class ii v v v v sstl-18 class i v v v v sstl-18 class ii v v v v 1.8-v hstl class i v v v v 1.8-v hstl class ii v v v v 1.5-v hstl class i v v v v 1.5-v hstl class ii v v v v differential sstl-2 class i v v v differential sstl-2 class ii v v v differential sstl-18 class i v v v differential sstl-18 class ii v v v
altera corporation 4?25 january 2008 stratix ii device handbook, volume 2 selectable i/o standards in stratix ii and stratix ii gx devices f for more information, refer to the plls in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii device handbook or the plls in stratix ii & straix ii gx devices chapter in volume 2 of the stratix ii gx device handbook. voltage levels stratix ii device specify a range of allowed voltage levels for supported i/o standards. table 4?4 shows only typical values for input and output v ccio , v ref , as well as the board v tt . 1.8-v differential hstl class i v v v 1.8-v differential hstl class ii v v v 1.5-v differential hstl class i v v v 1.5-v differential hstl class ii v v v lv d s v v v v hypertransport technology v differential lvpecl vv v note to ta b l e 4 ? 3 : (1) the enhanced pll external clock output bank does not allow a mixture of both single-ended and differential i/o standards. (2) altera does not support 1.2-v hstl fo r pll input pins on column i/o pins. table 4?3. i/o standards supported for strati x ii and stratix ii gx pll pins (part 2 of 2) i/o standard (2) enhanced pll (1) fast pll input output input inclk fbin extclk inclk table 4?4. stratix ii and strati x ii gx i/o standards and voltage levels (part 1 of 3) note (1) i/o standard stratix ii and stratix ii gx v ccio (v) v ref (v) v tt (v) input operation o utput operation input termination top and bottom i/o banks left and right i/o banks (3) top and bottom i/o banks left and right i/o banks (3) lvttl 3.3/2.5 3.3/2.5 3.3 3.3 na na lvcmos 3.3/2.5 3.3/2.5 3.3 3.3 na na
4?26 altera corporation stratix ii device handbook, volume 2 january 2008 stratix ii and stratix ii gx i/o banks 2.5 v 3.3/2.5 3.3/2.5 2.5 2.5 na na 1.8 v 1.8/1.5 1.8/1.5 1.8 1.8 na na 1.5 v 1.8/1.5 1.8/1.5 1.5 1.5 na na 3.3-v pci 3.3 na 3.3 na na na 3.3-v pci-x 3.3 na 3.3 na na na sstl-2 class i 2.5 2.5 2.5 2.5 1.25 1.25 sstl-2 class ii 2.5 2.5 2.5 2.5 1.25 1.25 sstl-18 class i 1.8 1.8 1.8 1.8 0.90 0.90 sstl-18 class ii 1.8 1.8 1.8 na 0.90 0.90 1.8-v hstl class i 1.8 1.8 1.8 1.8 0.90 0.90 1.8-v hstl class ii 1.8 1.8 1.8 na 0.90 0.90 1.5-v hstl class i 1.5 1.5 1.5 1.5 0.75 0.75 1.5-v hstl class ii 1.5 1.5 1.5 na 0.75 0.75 1.2-v hstl (4) 1.2 na 1.2 na 0.6 na differential sstl-2 class i 2.5 2.5 2.5 2.5 1.25 1.25 differential sstl-2 class ii 2.5 2.5 2.5 2.5 1.25 1.25 differential sstl-18 class i 1.8 1.8 1.8 1.8 0.90 0.90 differential sstl-18 class ii 1.8 1.8 1.8 na 0.90 0.90 1.8-v differential hstl class i 1.8 1.8 1.8 na 0.90 0.90 1.8-v differential hstl class ii 1.8 1.8 1.8 na 0.90 0.90 1.5-v differential hstl class i 1.5 1.5 1.5 na 0.75 0.75 1.5-v differential hstl class ii 1.5 1.5 1.5 na 0.75 0.75 lv d s (2) 3.3/2.5/1.8/1.5 2.5 3.3 2.5 na na table 4?4. stratix ii and strati x ii gx i/o standards and voltage levels (part 2 of 3) note (1) i/o standard stratix ii and stratix ii gx v ccio (v) v ref (v) v tt (v) input operation o utput operation input termination top and bottom i/o banks left and right i/o banks (3) top and bottom i/o banks left and right i/o banks (3)
altera corporation 4?27 january 2008 stratix ii device handbook, volume 2 selectable i/o standards in stratix ii and stratix ii gx devices f refer to the dc & switching characteristics chapter in volume 1 of the stratix ii device handbook or the dc & switching characteristics chapter in volume 1 of the stratix ii gx device handbook for detailed electrical characteristics of each i/o standard. on-chip termination stratix ii and stratix ii gx devices feature on-chip termination to provide i/o impedance matching and termin ation capabilities. apart from maintaining signal integrity, this feature also minimizes the need for external resistor netw orks, thereby saving board space and reducing costs. stratix ii and stratix ii gx devices su pport on-chip series (r s ) and parallel (r t ) termination for single-ended i/o standards and on-chip differential termination (r d ) for differential i/o standards. this section discusses the on-chip series termination support. f for more information on differential on-chip termination, refer to the high-speed differential i/ o interfaces with dpa in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii device handbook or the high-speed differential i/o interfaces with dpa in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook. hypertransport technology na 2.5 na 2.5 na na differential lvpecl (2) 3.3/2.5/1.8/1.5 na 3.3 na na na notes to ta b l e 4 ? 4 : (1) any input pins with pci-cl amping diode will clamp the v ccio to 3.3 v. (2) lvds and lvpecl output operation in the top and bottom banks is only supported in pll banks 9-12. the v ccio level for differential output operatio n in the pll banks is 3.3 v. the v ccio level for output operation in the left and right i/o banks is 2.5 v. (3) the right i/o bank does not apply to the stratix ii gx. the right i/o bank on stra tix ii gx devices consists of transceivers. (4) 1.2-v hstl is only support ed in i/o banks 4,7, and 8. table 4?4. stratix ii and strati x ii gx i/o standards and voltage levels (part 3 of 3) note (1) i/o standard stratix ii and stratix ii gx v ccio (v) v ref (v) v tt (v) input operation o utput operation input termination top and bottom i/o banks left and right i/o banks (3) top and bottom i/o banks left and right i/o banks (3)
4?28 altera corporation stratix ii device handbook, volume 2 january 2008 on-chip termination the stratix ii and stratix ii gx devices supports i/o driver on-chip series (r s ) and parallel (r t ) termination through drive strength control for single-ended i/os. there are three ways to implement the r s and (r t ) in stratix ii and stratix ii gx devices: r s without calibration for both row i/os and column i/os r s with calibration only for column i/os r t with calibration only for column i/os on-chip series termina tion without calibration stratix ii and stratix ii gx devices support driver impedance matching to provide the i/o driver with controlled output impedance that closely matches the impedance of the transmis sion line. as a re sult, reflections can be significantly reduced. stratix ii and stratix ii gx devices support on-chip series termination for si ngle-ended i/o standards (see figure 4?23 ). the r s shown in figure 4?23 is the intrinsic impedance of transistors. the typical r s values are 25 ? and 50 ? . once matching impedance is selected, current drive strength is no longer selectable. 1 on-chip series termination withou t calibration is supported on output pins or on the output function of bidirectional pins. figure 4?23. stratix ii and stra tix ii gx on-chip series termination without calibration stratix ii driver series impedance receiving device v ccio r s r s z o gnd
altera corporation 4?29 january 2008 stratix ii device handbook, volume 2 selectable i/o standards in stratix ii and stratix ii gx devices table 4?5 shows the list of output standa rds that support on-chip series termination without calibration. to use on-chip termination for the sstl class i standard, users should select the 50- ? on-chip series terminatio n setting for replacing the external 25- ? r s (to match the 50- ? transmission line). for the sstl class ii standard, users should select the 25- ? on-chip series termination setting (to match the 50- ? transmission line and the near end 50- ? pull-up to v tt ). table 4?5. selectable i/o drivers with on-chip series termination without calibration i/o standard on-chip series termination setting row i/o column i/o unit 3.3-v lvttl 50 50 ? 25 25 ? 3.3-v lvcmos 50 50 ? 25 25 ? 2.5-v lvttl 50 50 ? 25 25 ? 2.5-v lvcmos 50 50 ? 25 25 ? 1.8-v lvttl 50 50 ? 25 ? 1.8-v lvcmos 50 50 ? 25 ? 1.5-v lvttl 50 50 ? 1.5-v lvcmos 50 50 ? sstl-2 class i 50 50 ? sstl-2 class ii 25 25 ? sstl-18 class i 50 50 ? sstl-18 class ii 25 ? 1.8-v hstl class i 50 50 ? 1.8-v hstl class ii 25 ? 1.5-v hstl class i 50 50 ? 1.2-v hstl (1) 50 ? note to ta b l e 4 ? 5 : (1) 1.2-v hstl is only support ed in i/o banks 4,7, and 8.
4?30 altera corporation stratix ii device handbook, volume 2 january 2008 on-chip termination f for more information on tolerance sp ecifications for on-chip termination without calibration, refer to the dc & switching characteristics chapter in volume 1 of the stratix ii device handbook or the dc & switching characteristics chapter in volume 1 of the stratix ii gx device handbook . on-chip series termin ation with calibration stratix ii and stratix ii gx devices su pport on-chip series termination with calibration in column i/os in top and bottom banks. every column i/o buffer consists of a gr oup of transistors in para llel. each transistor can be individually enabled or disabled. the on-chip series termination calibration circuit compares the total impedance of the transistor group to the external 25- ? or 50- ? resistors connected to the rup and rdn pins, and dynamically enables or disables th e transistors until they match (as shown in figure 4?24 ). the r s shown in figure 4?24 is the intrinsic impedance of transistors. calibrat ion happens at the end of device configuration. once the calibration ci rcuit finds the correct impedance, it powers down and stops changing th e characteristics of the drivers. 1 on-chip series termination with calibration is supported on output pins or on the output function of bidirectional pins. figure 4?24. stratix ii and st ratix ii gx on-chip seri es termination with calibration stratix ii driver series impedance receiving device v ccio r s r s z o gnd
altera corporation 4?31 january 2008 stratix ii device handbook, volume 2 selectable i/o standards in stratix ii and stratix ii gx devices table 4?6 shows the list of output standa rds that support on-chip series termination with calibration. on-chip parallel termin ation with calibration stratix ii and stratix ii gx devices su pport on-chip parallel termination with calibration in column i/os in top and bottom banks. every column i/o buffer consists of a gr oup of transistors in para llel. each transistor can be individually enabled or disabled. the on-chip parallel termination calibration circuit compares the total impedance of the transistor group to table 4?6. selectable i/o drivers with on-chip series termination with calibration i/o standard on-chip series termination setting (column i/o) unit 3.3-v lvttl 50 ? 25 ? 3.3-v lvcmos 50 ? 25 ? 2.5-v lvttl 50 ? 25 ? 2.5-v lvcmos 50 ? 25 ? 1.8-v lvttl 50 ? 25 ? 1.8-v lvcmos 50 ? 25 ? 1.5 lvttl 50 ? 1.5 lvcmos 50 ? sstl-2 class i 50 ? sstl-2 class ii 25 ? sstl-18 class i 50 ? sstl-18 class ii 25 ? 1.8-v hstl class i 50 ? 1.8-v hstl class ii 25 ? 1.5-v hstl class i 50 ? 1.2-v hstl (1) 50 ? note to ta b l e 4 ? 6 : (1) 1.2-v hstl is only support ed in i/o banks 4,7, and 8.
4?32 altera corporation stratix ii device handbook, volume 2 january 2008 on-chip termination the external 50- ? resistors connected to the rup and rdn pins and dynamically enables or disables th e transistors until they match. calibration happens at the end of th e device configuration. once the calibration circuit finds the correct impedance, it powers down and stops changing the characteristics of the drivers. there are two separate sets of calibration circuits in the stratix ii and stratix ii gx devices: one calibration circuit for top banks 3 and 4 one calibration circuit fo r bottom banks 7 and 8 calibration circuits rely on the external pull-up reference resistor (r up ) and pull-down reference resistor (r dn ) to achieve accurate on-chip series and parallel termination. there is one pair of rup and rdn pins in bank 4 for the calibration circuit for top i/o ba nks 3 and 4. similarly, there is one pair of rup and rdn pins in bank 7 for the calibration circuit for bottom i/o banks 7 and 8. two banks share the same calibration circuitry, so they must have the same v ccio voltage if both banks enable on-chip series or parallel termination with calibration. if banks 3 and 4 have different v ccio voltages, only bank 4 can enable on-c hip series or parallel termination with calibration because the rup and rdn pins are located in bank 4. bank 3 still can use on-chip series termination, but without calibration. the same rule applies to banks 7 and 8. table 4?7. selectable i/o drivers with on-chip parallel termination with calibration i/o standard on-chip parallel termination setting (column i/o) unit sstl-2 class i 50 ? sstl-2 class ii 50 ? sstl-18 class i 50 ? sstl-18 class ii 50 ? 1.8-v hstl class i 50 ? 1.8-v hstl class ii 50 ? 1.5-v hstl class i 50 ? 1.5-v hstl class ii 50 ? 1.2-v hstl (1) 50 ? note to ta b l e 4 ? 7 : (1) 1.2-v hstl is only support ed in i/o banks 4,7, and 8.
altera corporation 4?33 january 2008 stratix ii device handbook, volume 2 selectable i/o standards in stratix ii and stratix ii gx devices 1 on-chip parallel termination with calibration is only supported for input pins. pins configured as bidirectional do not support on-chip parallel termination. the rup and rdn pins are dual-purpose i/os , which means they can be used as regular i/os if the calibratio n circuit is not used. when used for calibration, the rup pin is connected to v ccio through an external 25- ? or 50- ? resistor for an on-chip se ries termination value of 25 ? or 50 ? , respectively. the rdn pin is connected to gnd through an external 25- ? or 50- ? resistor for an on-chip se ries termination value of 25 ? or 50 ? , respectively. for on-chip pa rallel termination, the rup pin is connected to v ccio through an external 50- ? resistor, and rdn is connected to gnd through an external 50- ? resistor. f for more information on tolerance sp ecifications for on-chip termination with calibration, refer to the dc & switching characteristics chapter in volume 1 of the stratix ii device handbook or the dc & switching characteristics chapter in volume 1 of the stratix ii gx device handbook . design considerations while stratix ii and stratix ii gx device s feature various i/o capabilities for high-performance and high-speed system designs, there are several other considerations that require attention to ensure the success of those designs. i/o termination i/o termination requirements for single-ended and differential i/o standards are discussed in this section. single-ended i/o standards although single-ended, non-voltage- referenced i/o standards do not require termination, impedance ma tching is necessary to reduce reflections and improv e signal integrity. voltage-referenced i/o standards require both an input reference voltage, v ref, and a termination voltage, v tt . the reference voltage of the receiving device tracks the terminatio n voltage of the transmitting device. each voltage-referenced i/o standard requires a unique termination setup. for example, a prop er resistive signal termination scheme is critical in sstl standards to produce a reliable ddr memory system with superior noise margin.
4?34 altera corporation stratix ii device handbook, volume 2 january 2008 design considerations stratix ii and stratix ii gx on-chip series and parallel termination provides the convenience of no exte rnal components. external pull-up resistors can be used to terminate the voltage-referenced i/o standards such as sstl-2 and hstl. 1 refer to the ?stratix ii and stratix ii gx i/o standards support? on page 4?2 for more information on the termination scheme of various single-ended i/o standards. differential i/o standards differential i/o standards typically require a termination resistor between the two signals at the receiver. the termination resistor must match the differential load impe dance of the bus. stratix ii and stratix ii gx devices provide an option al differential on-chip resistor when using lvds and hypertransport standards. i/o banks restrictions each i/o bank can simultaneously support multiple i/o standards. the following sections provide guidelines for mixing non-voltage-referenced and voltage-referenced i/o standards in stratix ii and stratix ii gx devices. non-voltage-referenced standards each stratix ii and stratix ii gx device i/o bank has its own v ccio pins and supports only one v ccio , either 1.5, 1.8, 2.5, or 3.3 v. an i/o bank can simultaneously support any number of input signals wi th different i/o standard assignments, as shown in table 4?8 . for output signals, a single i/o ba nk supports non-voltage-referenced output signals that are drivin g at the same voltage as v ccio . since an i/o bank can only have one v ccio value, it can only drive out that one value for non-voltage-referenced signals. for example, an i/o bank with a 2.5-v v ccio setting can support 2.5-v standard inputs and outputs and 3.3-v lvcmos inputs (not output or bidirectional pins). table 4?8. acceptable input levels for lvttl and lvcmos (part 1 of 2) bank v ccio (v) acceptable input levels (v) 3.3 2.5 1.8 1.5 3.3 vv (1) 2.5 v v
altera corporation 4?35 january 2008 stratix ii device handbook, volume 2 selectable i/o standards in stratix ii and stratix ii gx devices voltage-referenced standards to accommodate voltage-referenced i/o standards, each stratix ii or stratix ii gx device?s i/o bank supports multiple v ref pins feeding a common v ref bus. the number of available v ref pins increases as device density increases. if these pins are not used as v ref pins, they cannot be used as generic i/o pins. however, each bank can only have a single v ccio voltage level and a single v ref voltage level at a given time. an i/o bank featuring single-ended or differential standards can support voltage-referenced standards as long as all voltage-referenced standards use the same v ref setting. because of performance reasons, volt age-referenced input standards use their own v ccio level as the power source. for example, you can only place 1.5-v hstl input pins in an i/o bank with a 1.5-v v ccio . 1 refer to the ?stratix ii and stratix ii gx i/o banks? on page 4?20 for details on input v ccio for voltage-referenced standards. voltage-referenced bidirectional and output signals must be the same as the i/o bank?s v ccio voltage. for example, you can only place sstl-2 output pins in an i /o bank with a 2.5-v v ccio . 1 refer to the ?i/o placement guid elines? on page 4?36 for details on voltage-referenced i/o standards placement. 1.8 v (2) v (2) v v (1) 1.5 v (2) v (2) v v notes to ta b l e 4 ? 8 : (1) because the input signal does not drive to the rail, the input buffer does not completely shut off, and th e i/o current is slightly higher than the default value. (2) these input values overdrive the inpu t buffer, so the pin leakage current is slightly higher than the default value. to drive inputs higher than v ccio but less than 4.0 v, disable the pci clamping diode and select the allow lvttl and lvcmos input levels to overdrive input buffer option in the quartus ii software. table 4?8. acceptable input levels for lvttl and lvcmos (part 2 of 2) bank v ccio (v) acceptable input levels (v) 3.3 2.5 1.8 1.5
4?36 altera corporation stratix ii device handbook, volume 2 january 2008 design considerations mixing voltage-referenced and no n-voltage-referenced standards an i/o bank can support both non-voltage-referenced and voltage-referenced pins by applying each of the rule sets individually. for example, an i/o bank can support ss tl-18 inputs and 1.8-v inputs and outputs with a 1.8-v v ccio and a 0.9-v v ref . similarly, an i/o bank can support 1.5-v standards, 2.5-v (input s, but not outputs), and hstl i/o standards with a 1.5-v v ccio and 0.75-v v ref . i/o placement guidelines the i/o placement guidelines help to reduce noise issues that may be associated with a design such that stratix ii and stratix ii gx fpgas can maintain an acceptable noise level on the v ccio supply. because stratix ii and stratix ii gx devices require each bank to be powered separately for v ccio , these noise issues have no effect when crossing bank boundaries and, as such, these rules need not be applied. this section provides i/o placemen t guidelines for the programmable i/o standards supported by stratix ii and stratix ii gx devices and includes essential information for designing systems using their devices? selectable i/o capabilities. v ref pin placement restrictions there are at least two dedicated v ref pins per i/o bank to drive the v ref bus. larger stratix ii and stratix ii gx devices have more v ref pins per i/o bank. all v ref pins within one i/o bank are shorted together at device die level. there are limits to the number of pins that a v ref pin can support. for example, each output pin adds some noise to the v ref level and an excessive number of outputs make the level too unstable to be used for incoming signals. restrictions on the placement of si ngle-ended voltage-referenced i/o pads with respect to v ref pins help maintain an acceptable noise level on the v ccio supply and prevent output switching noise from shifting the v ref rail. input pins each v ref pin supports a maximum of 40 input pads.
altera corporation 4?37 january 2008 stratix ii device handbook, volume 2 selectable i/o standards in stratix ii and stratix ii gx devices output pins when a voltage-referenced input or bidirectional pad does not exist in a bank, the number of output pads that can be used in that bank depends on the total number of available pads in that same bank. however, when a voltage-referenced input exists, a de sign can use up to 20 output pads per v ref pin in a bank. bidirectional pins bidirectional pads must satisfy both input and output guidelines simultaneously. the general formulas for input and output rules are shown in table 4?9 . if the same output enable (oe) controls all the bidirectional pads (bidirectional pads in the same oe group are driving in and out at the same time) and there are no other outputs or voltage-referenced inputs in the bank, then the voltage-referenced input is never active at the same time as an output. ther efore, the output limitation rule does not apply. however, since th e bidirectional pads are linked to the same oe, the bidirectional pads wi ll all act as inputs at the same time. therefore, there is a limit of 40 input pads, as follows: + ? ? 40 per v ref pin if any of the bidirectional pads are controlled by different oe and there are no other outputs or voltage-referenced inputs in the bank, then one group of bidirectional pads can be used as inputs and another group is used as outputs. in such cases, the formula for the output rule is simplified, as follows: < total number of bidirectional pins > ? < total number of pins from smallest oe group > ? ? 20 per v ref pin table 4?9. bidirectional pin limitation formulas rules formulas input + ? ? 40 per v ref pin output + ? ? ? 20 per v ref pin
4?38 altera corporation stratix ii device handbook, volume 2 january 2008 design considerations consider a case where eight bidirectional pads are controlled by oe1, eight bidirectional pads are controlled by oe2, six bidirectional pads are controlled by oe3, and there are no other outputs or voltage-referenced inputs in the bank. while this totals 22 bidirectional pads, it is safely allowable because there would be a possible maximum of 16 outputs per v ref pin, assuming the worst case where oe1 and oe2 are active an d oe3 is inactive. this is useful for ddr sdram applications. when at least one additional volt age-referenced input and no other outputs exist in the same v ref group, the bidirectional pad limitation must simultaneously adhere to the in put and output limitations. the input rule becomes: < total number of bidirectional pins > + < total number of v ref input pins > ? ? 40 per v ref pin whereas the output rule is simplified as: < total number of bidirectional pins > ? ? 20 per v ref pin when at least one additi onal output exists but no voltage-referenced inputs exist, the output rule becomes: < total number of bidirectional pins > + < total number of output pins > ? < total number of pins from smallest oe group > ? ? 20 per v ref pin when additional voltage-referenced inputs and other outputs exist in the same v ref group, then the bidirect ional pad limitation must again simultaneously adhere to the input and output limitations. the input rule is: < total number of bidirectional pins > + < total number of v ref input pins > ? ? 40 per v ref pin whereas the output rule is given as: < total number of bidirectional pins > + < total number of output pins > ? < total number of pins from smallest oe group > ? ? 20 per v ref pin i/o pin placement with respect to high-speed differential i/o pins regardless of whether or not the serd es circuitry is utilized, there is a restriction on the placement of single -ended output pins with respect to high-speed differential i/o pins. as shown in figure 4?25 , all
altera corporation 4?39 january 2008 stratix ii device handbook, volume 2 selectable i/o standards in stratix ii and stratix ii gx devices single-ended outputs must be placed at least one lab row away from the differential i/o pins. there are no restrictions on the placement of single-ended input pins with respect to differential i/o pins. single-ended input pins may be pl aced within the same lab row as differential i/o pins. however, the si ngle-ended input?s ioe register is not available. the input must be implemented within the core logic. this single-ended output pin placement restriction only applies when using the lvds or hypertransport i /o standards in the left and right i/o banks. there are no restrictions for single-ended output pin placement with respect to differentia l clock pins in the top and bottom i/o banks. figure 4?25. single-ended output pin placem ent with respect to differential i/o pins dc guidelines power budgets are essential to ensure the reliability and functionality of a system application. you are often required to perform power dissipation analysis on each device in the system to come out with the total power dissipated in that system , which is composed of a static component and a dynamic component. the static power consumption of a de vice is the total dc current flowing from v ccio to ground. single-ended output pi n differential i/o pin single_ended input single-ended outputs not allowed row boundary
4?40 altera corporation stratix ii device handbook, volume 2 january 2008 design considerations for any ten consecutive pads in an i/o bank of stratix ii and stratix ii gx devices, altera recommends a maxi mum current of 250 ma, as shown in figure 4?26 , because the placement of v ccio /ground (gnd) bumps are regular, 10 i/o pins per pair of powe r pins. this limit is on the static power consumed by an i/o standard, as shown in table 4?10 . limiting static power is a way to improve reliability over the lifetime of the device. figure 4?26. dc current density restriction notes (1) , (2) notes to figure 4?26 : (1) the consecutive pads do not cross i/o banks. (2) v ref pins do not affect dc current calculation because there are no v ref pads. i/o pin sequence of an i/o bank any 10 consecutive output pins pin+9 pin pin 250ma i vcc gnd vcc
altera corporation 4?41 january 2008 stratix ii device handbook, volume 2 selectable i/o standards in stratix ii and stratix ii gx devices table 4?10 shows the i/o standard dc current specification. table 4?10. stratix ii and stratix ii gx i/o standar d dc current specification (part 1 of 2) note (1) i/o standard i pin (ma), top and bottom i/o banks i pin (ma), left and right i/o banks (2) lv t t l (3) (3) lv c m o s (3) (3) 2.5 v (3) (3) 1.8 v (3) (3) 1.5 v (3) (3) 3.3-v pci 1.5 na 3.3-v pci-x 1.5 na sstl-2 class i 12 (4) 12 (4) sstl-2 class ii 24 (4) 16 (4) sstl-18 class i 12 (4) 10 (4) sstl-18 class ii 20 (4) na 1.8-v hstl class i 12 (4) 12 1.8-v hstl class ii 20 (4) na 1.5-v hstl class i 12 (4) 8 1.5-v hstl class ii 20 (4) na differential sstl-2 class i 12 12 differential sstl-2 class ii 24 16 differential sstl-18 class i 12 10 differential sstl-18 class ii 20 na 1.8-v differential hstl class i 12 12 1.8-v differential hstl class ii 20 na 1.5-v differential hstl class i 12 8 1.5-v differential hstl class ii 20 na
4?42 altera corporation stratix ii device handbook, volume 2 january 2008 conclusion table 4?10 only shows the limit on the static power consumed by an i/o standard. the amount of power used at any moment could be much higher, and is based on the switching activities. conclusion stratix ii and stratix ii gx devices pr ovide i/o capabilities that allow you to work in compliance with cu rrent and emerging i/o standards and requirements. with the stratix ii or st ratix ii gx devices features, such as programmable driver strength, you ca n reduce board design interface costs and increase the development flexibility. references refer to the following references for more information: interface standard for nominal 3v/ 3.3-v supply digital integrated circuits, jesd8-b, electronic indu stries association, september 1999. 2.5-v +/- 0.2v (normal range) and 1.8-v to 2.7v (wide range) power supply voltage and interface standard for non-terminated digital integrated circuits, je sd8-5, electronic industries association, october 1995. 1.8-v +/- 0.15 v (normal range) and 1.2 v - 1.95 v (wide range) power supply voltage and interface standard for non-terminated digital integrated circuits, je sd8-7, electronic industries association, february 1997. 1.5-v +/- 0.1 v (normal range) and 0.9 v - 1.6 v (wide range) power supply voltage and interface standa rd for non-terminated digital integrated circuits, jesd8-11, elec tronic industries association, october 2000. notes to table 4?10 : (1) the current value obtained for differential hstl and diff erential sstl standards is per pin and not per differential pair, as opposed to the per-pair current va lue of lvds and hypertransport standards. (2) this does not apply to the right i/o banks of stratix ii gx devices. stratix ii gx devices have transceivers on the right i/o banks. (3) the dc power specification of each i/o standard depend s on the current sourcing and sinking capabilities of the i/o buffer programmed with that standard, as well as the load being driven. lvttl, lvcmos, 2.5-v, 1.8-v, and 1.5-v outputs are not included in the static power calculat ions because they normally do not have resistor loads in real applications. the voltage swing is rail-to-rail with capa citive load only. there is no dc current in the system. (4) this i pin value represents the dc current specification for the default current strength of the i/o standard. the i pin varies with programmable drive strength and is the same as the drive strength as set in quartus ii software. refer to the stratix ii architecture chapter in volume 1 of the stratix ii device handbook or the stratix ii gx architecture chapter in volume 1 of the stratix ii gx device handbook for a detailed description of the programmable drive strength feature of voltage-referenced i/o standards. table 4?10. stratix ii and stratix ii gx i/o standar d dc current specification (part 2 of 2) note (1) i/o standard i pin (ma), top and bottom i/o banks i pin (ma), left and right i/o banks (2)
altera corporation 4?43 january 2008 stratix ii device handbook, volume 2 selectable i/o standards in stratix ii and stratix ii gx devices pci local bus specification, revision 2.2, pci special interest group, december 1998. pci-x local bus specification, revision 1.0a, pci special interest group. stub series terminated logic for 2.5-v (sstl-2), jesd8-9a, electronic industries as sociation, december 2000. stub series terminated logic for 1.8 v (sstl-18), preliminary jc42.3, electronic industries association. high-speed transceiver logic (h stl)?a 1.5-v output buffer supply voltage based interface st andard for digital integrated circuits, eia/jesd8-6, electronic industries association, august 1995. electrical characterist ics of low voltage differential signaling (lvds) interface circuits, ansi/t ia/eia-644, american national standards institute/telecommunications industry/electronic industries association, october 1995. referenced documents this chapter references the following documents: dc & switching characteristics chapter in volume 1 of the stratix ii device handbook dc & switching characteristics chapter in volume 1 of the stratix ii gx device handbook external memory interfaces in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii device handbook external memory interfaces in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook high-speed differential i/o interfaces with dpa in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii device handbook high-speed differential i/o interfaces with dpa in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook plls in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii device handbook plls in stratix ii & straix ii gx devices chapter in volume 2 of the stratix ii gx device handbook stratix ii architecture chapter in volume 1 of the stratix ii device handbook stratix ii gx architecture chapter in volume 1 of the stratix ii gx device handbook stratix ii gx transceiver user guide (volume 1) of the stratix ii gx device handbook
4?44 altera corporation stratix ii device handbook, volume 2 january 2008 document revision history document revision history table 4?11 shows the revision history for this chapter. table 4?11. document revision history (part 1 of 2) date and document version changes made summary of changes january 2008 v4.6 updated figure 4?22 .? updated note 4 to table 4?2 .? added ?referenced documents? section. ? minor text edits. ? no change for the stratix ii gx device handbook only: formerly chapter 9. the chapter number changed due to the addition of the stratix ii gx dynamic reconfiguration chapter. no content change. ? may 2007 v4.5 added a note to the ?on-chip series termination with calibration? section. ? added a note to the ?on-chip series termination without calibration? section ? updated note to the ?stratix ii and stratix ii gx i/o features? section. ? updated the ?lvds? section. ? updated note to ?1.5 v? section ? updated note (1) for table 10?4 updated note (2) for table 10?3 ? updated table 10?2, column heading for columns 9 and 10. ? updated table 10?10. ? fixed typo in the ?stratix ii and stratix ii gx i/o features? section ? february 2007 v4.4 added the ?document revision history? section to this chapter. ? august 2006 v4.3 updated table 9?2, table 9?4, table 9?5, table 9?6, and table 9?7. ? april 2006 v4.2 chapter updated as part of the stratix ii device handbook update. ? no change formerly chapter 8. chapter number change only due to chapter addition to section i in february 2006; no content change. ?
altera corporation 4?45 january 2008 stratix ii device handbook, volume 2 selectable i/o standards in stratix ii and stratix ii gx devices december 2005 v4.1 chapter updated as part of the stratix ii device handbook update. ? october 2005 v4.0 added chapter to the stratix ii gx device handbook . ? table 4?11. document revision history (part 2 of 2) date and document version changes made summary of changes
4?46 altera corporation stratix ii device handbook, volume 2 january 2008 document revision history
altera corporation 5?1 january 2008 5. high-speed differential i/o interfaces with dpa in stratix ii and stratix ii gx devices introduction stratix ? ii and stratix ? ii gx device family offers up to 1-gbps differential i/o capabilities to support source-synchronous communication protocols such as hypertransport? technology, rapid i/o, xsbi, and spi. stratix ii and stratix ii gx devices have the following dedicated circuitry for high-speed differ ential i/o support: differential i/o buffer transmit serializer receive deserializer data realignment circuit dynamic phase aligner (dpa) synchronizer (fifo buffer) analog plls (fast plls) for high-speed differential interfaces, stratix ii and stratix ii gx devices can accommodate different differential i/o standards, including the following: lvds hypertransport technology hstl sstl lvpecl 1 hstl, sstl, and lvpecl i/o standards can be used only for pll clock inputs and outputs in differential mode. i/o banks stratix ii and stratix ii gx inputs and outputs are partitioned into banks located on the periphery of the die. the inputs and outputs that support lvds and hypertransport technology are located in row i/o banks, two on the left and two on the right side of the stratix ii device and two on the left side of the stratix ii gx devi ce. lvpecl, hstl, and sstl standards are supported on certain top and bottom banks of the die (banks 9 to 12) when used as differential clock in puts/outputs. differential hstl and sstl standards can be supported on ba nks 3, 4, 7, and 8 if the pins on these banks are used as dqs/dqsn pins. figures 5?1 and 5?2 show where the banks and the plls are located on the die. sii52005-2.2
5?2 altera corporation stratix ii device handbook, volume 2 january 2008 i/o banks figure 5?1. stratix ii i/o banks note (1) , (2) , (3) , (4) , (5) , (6) , and (7) notes to figure 5?1 : (1) figure 5?1 is a top view of the silicon die that corresponds to a reverse view for flip-chip packages. it is a graphical representation only. see the pin list and quartus ii software for exact locations. (2) depending on the size of the device, differe nt device members have different numbers of v ref groups. (3) banks 9 through 12 are enhanced pll external cloc k output banks. these pll banks utilize the adjacent v ref group when voltage-referenced standards ar e implemented. for example, if an sstl input is implemented in pll bank 10, the voltage level at vrefb7 is the reference voltage level for the sstl input. (4) differential hstl and differential sstl standards are available for bidirectional operations on dqs pin and input-only operations on pll clock input pins; lvds, lvpecl, and hypertransport standards are available for input-only operations on p ll clock input pins. see the selectable i/o standards in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii device handbook for more details. (5) quartus ii software does not support differential sstl and differential hstl standards at left/right i/o banks. see the selectable i/o standards in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii device handbook if you need to implement these standards at these i/o banks. (6) banks 11 and 12 are available only in ep2s60, ep2s90, ep2s130, and ep2s180 devices. (7) plls 7, 8, 9, 10, 11, and 12 are available only in ep2s60, ep2s90, ep2s130, and ep2s180 devices. bank 3 bank 4 bank 11 bank 9 pll11 pll5 pll7 pll1 pll2 pll4 pll3 pll10 i/o banks 7, 8, 10 & 12 support all single-ended i/o standards and differential i/o standards except for hypertransport technology for both input and output operations. i/o banks 3, 4, 9 & 11 support all single-ended i/o standards and differential i/o standards except for hypertransport technology for both input and output operations. vref0b3 vref1b3 vref2b3 vref3b3 vref4b3 vref0b4 vref1b4 vref2b4 vref3b4 vref4b4 bank 8 bank 7 bank 12 bank 10 pll12 pll6 pll8 pll9 vref4b8 vref3b8 vref2b8 vref1b8 vref0b8 vref4b7 vref3b7 vref2b7 vref1b7 vref0b7 vref3b 2 vref2b2 vref1b2 vref0b2 bank 2 vref3b1 vref2b1 vref1b1 vref0b1 bank 1 vref1b 5 vref2b5 vref3b5 vref4b5 bank 5 vref1b6 vref2b6 vref3b6 vref4b6 bank 6 vref4b2 vref0b5 vref4b1 vref0b6 dqs4t dqs3t dqs2t dqs1t dqs0t dqs4b dqs3b dqs2b dqs1b dqs0b dqs8b dqs7b dqs6b dqs5b dqs8t dqs7t dqs6t dqs5t this i/o bank supports lvds and lvpecl standards for input clock operations. differential hstl and differential sstl standards are supported for both input and output operations. this i/o bank supports lvds and lvpecl standards for input clock operations. differential hstl and differential sstl standards are supported for both input and output operations. this i/o bank supports lvds and lvpecl standards for input clock operations. differential hstl and differential sstl standards are supported for both input and output operations. this i/o bank supports lvds and lvpecl standards for input clock operations. differential hstl and differential sstl standards are supported for both input and output operations. i/o banks 1, 2, 5 & 6 support lvttl, lvcmos, 2.5-v, 1.8-v, 1.5-v, sstl-2, sstl-18 class i, hstl-18 class i, hstl-15 class i, lvds, and hypertransport standards for input and output operations. hstl-18 class ii, hstl-15-class ii, sstl-18 class ii standards are only supported for input operations.
altera corporation 5?3 january 2008 stratix ii device handbook, volume 2 high-speed differential i/o interfaces with dpa in stratix ii and stratix ii gx devices figure 5?2. stratix ii gx i/o banks note (1) , (2) , (3) , (4) , (5) , (6) , and (7) notes to figure 5?2 : (1) figure 5?2 is a top view of the silicon die wh ich corresponds to a reverse view for flip-chip packages. it is a graphical representation only. (2) depending on size of the de vice, different device members have different number of v ref groups. refer to the pin list and the quartus ii software for exact locations. (3) banks 9 through 12 are enhanced pll external clock output banks. (4) horizontal i/o banks feature transceiver and dpa ci rcuitry for high speed differential i/o standards. (5) quartus ii software does not support differential sstl an d differential hstl standard s at left/right i/o banks. refer to the ?differential pin placement guidelines? on page 5?21 if you need to implemen t these standards at these i/o banks. (6) banks 11 and 12 are available only in ep2sgx60c/d/e, ep2sgx90e/f, and ep2sgx130g. (7) plls 7, 8, 11, and 12 are available only in ep2sgx60c/d/e, ep2sgxe/f, and ep2sgx130g. i/o b a nk s 3, 4, 9, a n d 11 s u pp o rt a ll s in g l e - e n ded i/o sta n dards f o r b o t h in p u t a n d ou tp u t o perat ion s . all d i ffere n t i a l i/o sta n dards are s u pp o rted f o r b o t h in p u t a n d ou tp u t o perat ion s at i/o ba nk s 9 a n d 11. i/o ba nk s 7, 8, 1 0 a n d 12 s u pp o rt a ll s in g l e - e n ded i/o sta n dards f o r b o t h in p u t a n d ou tp u t o perat ion s . all d i ffere n t i a l i/o sta n dards are s u pp o rted f o r b o t h in p u t a n d ou tp u t o perat ion s at i/o ba nk s 1 0 a n d 12. i/o ba nk s 1 & 2 s u pp o rt lvttl, lv c mos, 2.5 v, 1.8 v, 1.5 v, sstl-2, sstl-18 c l ass i, lv d s, pse u d o- d i ffere n t i a l sstl-2 a n d pse u d o- d i ffere n t i a l sstl-18 c l ass i sta n dards f o r b o t h in p u t a n d ou tp u t o perat ion s . hstl, sstl-18 c l ass ii, pse u d o- d i ffere n t i a l hstl a n d pse u d o- d i ffere n t i a l sstl-18 c l ass ii sta n dards are only s u pp o rted f o r in p u t o perat ion s . (4) dqs 8 dqs 8 dqs 8 dqs 8 dqs 8 dqs 8 dqs 8 pll11 vref0b3 vref1b3 vref2b3 vref3b3 vref4b3 vref0b4 vref1b4 vref2b4 vref3b4 vref4b4 vref4b8 vref3b8 vref2b8 vref1b8 vref0b8 vref4b7 vref3b7 vref2b7 vref1b7 vref0b7 pll12 dqs 8 dqs 8 dqs 8 dqs 8 dqs 8 dqs 8 dqs 8dqs 8 dqs 8 bank 11 vref3b2 vref4b2 vref0b1 vref2b1 vref3b1 vref4b1 pll1 pll2 bank 1 bank 2 bank 3 bank 4 bank 12 bank 8 bank 7 pll7 pll8 pll6 pll5 bank 9 bank 10 vref1b1 vref0b2 vref1b2 vref2b2 dqs 8 dqs 8 thi s i/o ba nk s u pp o rts lv d s a n d lvpe c l sta n dards f o r in p u t c lo c k o perat ion s . d i ffere n t i a l hstl a n d d i ffere n t i a l sstl sta n dards are s u pp o rted f o r b o t h in p u t a n d ou tp u t o perat ion s . (3) thi s i/o ba nk s u pp o rts lv d s a n d lvpe c l sta n dards f o r in p u t c lo c k o perat ion. d i ffere n t i a l hstl a n d d i ffere n t i a l sstl sta n dards are s u pp o rted f o r b o t h in p u t a n d ou tp u t o perat ion s . (3) thi s i/o ba nk s u pp o rts lv d s a n d lvpe c l sta n dards f o r in p u t c lo c k o perat ion. d i ffere n t i a l hstl a n d d i ffere n t i a l sstl sta n dards are s u pp o rted f o r b o t h in p u t a n d ou tp u t o perat ion s . (3) thi s i/o ba nk s u pp o rts lv d s a n d lvpe c l sta n dards f o r in p u t c lo c k o perat ion. d i ffere n t i a l hstl a n d d i ffere n t i a l sstl sta n dards are s u pp o rted f o r b o t h in p u t a n d ou tp u t o perat ion s . (3) 13 14 17 16 15
5?4 altera corporation stratix ii device handbook, volume 2 january 2008 i/o banks table 5?1 lists the differential i/o standards supported by each bank. table 5?2 shows the total number of differential channels available in stratix ii devices. the available chan nels are divided evenly between the left and right banks of the die. non-dedicated clocks in the left and right banks can also be used as data re ceiver channels. the total number of receiver channels includes these fo ur non-dedicated clock channels. pin migration is available for different size devices in the same package. table 5?1. supported differential i/o types bank row i/o (banks 1, 2, 5 and 6) (2) column i/o (banks, 3, 4 and 7 through 12) type clock inputs clock outputs data or regular i/o pins clock inputs clock outputs data or regular i/o pins differential hstl vv (1) differential sstl vv (1) lvpecl vv lv d s vvvvv hypertransport technology vvv note to ta b l e 5 ? 1 : (1) used as both inputs and outputs on the dqs/dqsn pins. (2) banks 5 and 6 are not available in stratix ii gx devices. table 5?2. differential channels in stratix ii devices (part 1 of 2) notes (1) , (2) , and (3) device 484-pin fineline bga 484-pin hybrid fineline bga 672-pin fineline bga 780-pin fineline bga 1,020-pin fineline bga 1,508-pin fineline bga within the 1,508-pin fin ep2s15 38 transmitters 42 receivers 38 transmitters 42 receivers ep2s30 38 transmitters 42 receivers 58 transmitters 62 receivers ep2s60 38 transmitters 42 receivers 58 transmitters 62 receivers 84 transmitters 84 receivers ep2s90 38 transmitters 42 receivers 64 transmitters 68 receivers 90 transmitters 94 receivers 118 transmitters 118 receivers ep2s130 64 transmitters 68 receivers 88 transmitters 92 receivers 156 transmitters 156 receivers
altera corporation 5?5 january 2008 stratix ii device handbook, volume 2 high-speed differential i/o interfaces with dpa in stratix ii and stratix ii gx devices table 5?3 shows the total number of differential channels available in stratix ii gx devices. non-dedicated clocks in the left bank can also be used as data receiver channels. the total number of receiver channels includes these four non-dedicated clock channels. pin migration is available for different size devices in the same package. ep2s180 88 transmitters 92 receivers 156 transmitters 156 receivers notes to ta b l e 5 ? 2 : (1) pin count does not includ e dedicated pll input pins. (2) the total number of receiver channels includes the four non-dedicated clock channels that can optionally be used as data channels. (3) within the 1,508-pin fineline bga package, 92 receiver cha nnels and 92 transmitter channels are vertically migratable. table 5?2. differential channels in stratix ii devices (part 2 of 2) notes (1) , (2) , and (3) device 484-pin fineline bga 484-pin hybrid fineline bga 672-pin fineline bga 780-pin fineline bga 1,020-pin fineline bga 1,508-pin fineline bga within the 1,508-pin fin table 5?3. differential channels in stratix ii gx devices notes (1) , (2) , (3) device 780-pin fineline bga 1,152-pin fineline bga 1,508-pin fineline bga ep2sgx30 29 transmitters 31receivers ep2sgx60 29 transmitters 31 receivers 42 transmitters 42 receivers ep2sgx90 45 transmitters 47 receivers 59 transmitters 59 receivers ep2sgx130 71 transmitters 73 receivers notes to ta b l e 5 ? 3 : (1) pin count does not include dedicated pll input pins. (2) the total number of receiver channe ls includes the four non-dedicated clock channels that can optionally be used as data channels. (3) ep2sgx30cf780 devices with four transceiver channels are vertically migratable to ep2sgx60cf780 devices with four transceiver channels. ep2sgx30df780 devices with eight transceiver channels are vertically migratable to ep2sgx60df780 devices with eight transceiver channels. ep2sgx60ef1152 devices with 12 transceiver channels are vertically migratable to ep2sgx90ef1152 devices with 12 transceiver channels. ep2sgx90ff1508 devices with 16 transceiver channels are vertically migratable to ep2sgx130gf1508 devices with 20 transceiver channels.
5?6 altera corporation stratix ii device handbook, volume 2 january 2008 differential transmitter differential transmitter the stratix ii and stratix ii gx tran smitter has dedicated circuitry to provide support for lvds and hypert ransport signaling. the dedicated circuitry consists of a differential bu ffer, a serializer, and a shared fast pll. the differential buffer can drive out lvds or hypertransport signal levels that are statically set in the quartus ? ii software. the serializer takes data from a parallel bus up to 10 bits wide from the internal logic, clocks it into the load registers, and serializes it using the shift registers before sending the data to the differen tial buffer. the most significant bit (msb) is transmitted first. the load and shift registers are clocked by the diffioclk (a fast pll clock running at th e serial rate) and controlled by the load enable signal generated fr om the fast pll. the serialization factor can be statically set to ? 4, ???? ? 6, ? 7, ? 8, ???? or ? 10 using the quartus ii software. the load enable signal is automatically generated by the fast pll and is derived from the serialization factor setting. figure 5?3 is a block diagram of the stratix ii transmitter. figure 5?3. transmitter block diagram each stratix ii and stratix ii gx transmitter data channel can be configured to operate as a transmitter clock output. this flexibility allows the designer to place the output cloc k near the data outputs to simplify board layout and reduce clock-to-data skew. different applications often require specific clock to data alignments or specific data rate to clock rate factors. the transmitter can output a cl ock signal at the same rate as the data with a maximum frequency of 717 mhz. the output clock can also be divided by a factor of 2, 4, 8, or 10, depending on the serialization factor. the phase of the clock in relati on to the data can be set at 0 or 180 (edge or center aligned). the fast pll provides additional support for internal logic serializer fast pll diffioclk load_en 10 tx_ou t
altera corporation 5?7 january 2008 stratix ii device handbook, volume 2 high-speed differential i/o interfaces with dpa in stratix ii and stratix ii gx devices other phase shifts in 45 increments. th ese settings are made statically in the quartus ii megawizard ? software. figure 5?4 shows the transmitter in clock output mode. figure 5?4. transmitter in clock output mode the serializer can be bypassed to support ddr ( ? 2) and sdr ( ? 1) operations. the i/o element (ioe) contai ns two data output registers that each can operate in either ddr or sdr mode. the clock source for the registers in the ioe can come from any routing resource, from the fast pll, or from the enhanced pll. figure 5?5 shows the bypass path. figure 5?5. serializer bypass transmitter circuit diffioclk load_en parallel series internal lo g ic tx_outcloc k ioe serializer internal lo g ic ioe su pp o rts s d r, dd r, o r non-r eg i stered data p at h not used (connection exists) tx_out
5?8 altera corporation stratix ii device handbook, volume 2 january 2008 differential receiver differential receiver the receiver has dedicated circuitry to support high-speed lvds and hypertransport signaling, along with enhanced data reception. each receiver consists of a differential buffer, dynamic phase aligner (dpa), synchronization fifo buffer, data realignment circuit, deserializer, and a shared fast pll. the differential buff er receives lvds or hypertransport signal levels, which are statically set by the quartus ii software. the dpa block aligns the incoming data to on e of eight clock phases to maximize the receiver?s skew margin. the dpa circuit can be bypassed on a channel-by-channel basis if it is not needed. set the dpa bypass statically in the quartus ii megawizard plug-in manager or dynamically by using the optional rx_dpll_enable port. the synchronizer circuit is a 1-bit wi de by 6-bit deep fifo buffer that compensates for any phase differen ce between the dpa block and the deserializer. if necessary, the data re alignment circuit inserts a single bit of latency in the serial bit stream to align the word boundary. the deserializer includes shift registers and parallel load registers, and sends a maximum of 10 bits to the internal logi c. the data path in the receiver is clocked by either the diffioclk signal or the dpa recovered clock. the deserialization factor can be statically se t to 4, 5, 6, 7, 8, 9, or 10 by using the quartus ii software. the fast pll automatically generates the load enable signal, which is derived from the deserialization factor setting. figure 5?6 shows a block diagram of the receiver. figure 5?6. receiver block diagram dq 8 10 ? + data retimed_data dpa_clk ei g h t ph ase c lo c k s ded i cated r ece iv er in terface d pa by pass mul t i p l e x er up t o 1 g bps dpa fast pll diffioclk load_en rx_inclk synchronizer internal lo g ic re g ional or global clock data reali g nment circuitry
altera corporation 5?9 january 2008 stratix ii device handbook, volume 2 high-speed differential i/o interfaces with dpa in stratix ii and stratix ii gx devices the deserializer, like the serializer, can also be bypassed to support ddr ( ? 2) and sdr ( ? 1) operations. the dpa and data realignment circuit cannot be used when the deserializer is bypassed. the ioe contains two data input registers that can operate in ddr or sdr mode. the clock source for the registers in the ioe can come from any routing resource, from the fast pll, or from the enhanced pll. figure 5?7 shows the bypass path. figure 5?7. deserializer bypass receiver data realignment circuit the data realignment circuit aligns the word boundary of the incoming data by inserting bit latencies in to the serial stream. an optional rx_channel_data_align port controls the bit insertion of each receiver independently controlled from the internal logic. the data slips one bit for every pulse on the rx_channel_data_align port. the following are requirements for the rx_channel_data_align port: the minimum pulse width is one peri od of the parallel clock in the logic array. the minimum low time between pulses is one period of parallel clock. there is no maximum high or low time. valid data is available two parallel clock cycles after the rising edge of rx_channel_data_align . rx_in ioe deserializer dpa circuitry pld logic array i o e s upports s d r, dd r, or non- r egistered data p ath
5?10 altera corporation stratix ii device handbook, volume 2 january 2008 differential receiver figure 5?8 shows receiver output ( rx_out ) after one bit slip pulse with the deserialization factor set to 4. figure 5?8. data realignment timing the data realignment circuit can have up to 11 bit-times of insertion before a rollover occurs. the programma ble bit rollover point can be from 1 to 11 bit-times independent of the deserialization factor. an optional status port, rx_cda_max , is available to the fpga from each channel to indicate when the preset rollover point is reached. figure 5?9 illustrates a preset value of four bit-times before rollover occurs. the rx_cda_max signal pulses for one rx_outclk cycle to indicate that the rollover has occurred. figure 5?9. receiver data re-alignment rollover dynamic phase aligner the dpa block takes in high-speed serial data from the differential input buffer and selects one of eight phase clocks to sample the data. the dpa chooses a phase closest to the phase of the serial data. the maximum phase offset between the data and the phase-aligned clock is 1/8 ui, which is the maximum quantization error of the dpa. the eight phases rx_in rx_outclock rx_channel_data_ali g n rx_out inclk 3 3210 321x xx21 0321 2 1 0 3 2 1 0 3 2 1 0 rx_outclk rx_channel_data_align rx_cda_max inclk
altera corporation 5?11 january 2008 stratix ii device handbook, volume 2 high-speed differential i/o interfaces with dpa in stratix ii and stratix ii gx devices are equally divided, giving a 45-degree resolution. figure 5?10 shows the possible phase relationships between the dpa clocks and the incoming serial data. figure 5?10. dpa clock phase to data bit relationship each dpa block continuously monitors the phase of the incoming data stream and selects a new clock phase if needed. the selection of a new clock phase can be prevented by the optional rx_dpll_hold port, which is available for each channel. the dpa block requires a training patte rn and a training sequence of at least 256 repetitions of the training pattern. the training pattern is not fixed, so you can use any training patte rn with at least one transition on each channel. an optional output port, rx_dpa_locked , is available to the internal logic, to indicate when the dpa block has settled on the closest phase to the incoming data phase. the rx_dpa_locked de-asserts, depending on what is selected in the quartus ii megawizard plug-in, when either a new phase is selected, or when the dpa has moved two phases in the same direction. the data may still be valid even when the rx_dpa_locked is deasserted. use data checkers to validate the data when rx_dpa_locked is deasserted. an independent reset port, rx_reset , is available to reset the dpa circuitry. the dpa circuit must be retrained after reset. 45? 90? 135? 180? 225? 270? 315? 0.125t vco t vco 0? rx_in d0 d1 d2 d3 d4 dn
5?12 altera corporation stratix ii device handbook, volume 2 january 2008 differential i/o termination synchronizer the synchronizer is a 1-bit ? 6-bit deep fifo buffer that compensates for the phase difference between the recovered clock from the dpa circuit and the diffioclk that clocks the rest of th e logic in the receiver. the synchronizer can only compensate for phase differences, not frequency differences between the data and the receiver?s inclk . an optional port, rx_fifo_reset , is available to the internal logic to reset the synchronizer. the synchronizer is au tomatically reset when the dpa first locks to the incoming data. altera ? recommends using rx_fifo_reset to reset the synchronizer when the dpa signals a loss-of-lock condition beyond the initial locking condition. differential i/o termination stratix ii and stratix ii gx devices provide an on-chip 100- ?? differential termination option on each differential receiver channel for lvds and hypertransport standards. the on-chip termination eliminates the need to supply an external termination resistor, simplifying the board design and reducing reflections caused by stubs between the buffer and the termination resistor. you can enable on-chip termination in the quartus ii assignments editor. differential on-c hip termination is supported across the full range of supported differential data rates. f for more information, refer to the high-speed i/o specifications section of the dc & switching characteristic s chapter in volume 1 of the stratix ii device handbook or the high-speed i/o spec ifications section of the dc & switching characteristics chapter in volume 1 of the stratix ii gx device handbook . figure 5?11 illustrates on-chip termination. figure 5?11. on-chip diff erential termination on-chip differential termination is su pported on all row i/o pins and on clock pins clk[0, 2, 8, 10] . the clock pins clk[1, 3, 9, 11] , and fpll[7..10]clk , and the clocks in the top and bottom i/o banks ( clk[4..7, 12..15] ) do not support differential on-chip termination. lvds/ht transmitter stratix ii differential receiver with on-chip 100 termination r d z 0 = 50 z 0 = 50
altera corporation 5?13 january 2008 stratix ii device handbook, volume 2 high-speed differential i/o interfaces with dpa in stratix ii and stratix ii gx devices fast pll the high-speed differential i/o receiv er and transmitter channels use the fast pll to generate the parallel global clocks ( rx- or tx- clock) and high-speed clocks ( diffioclk ). figure 5?12 shows the locations of the fast plls. the fast pll vco operates at the clock frequency of the data rate. each fast pll offers a single se rial data rate support, but up to two separate serialization and/or deserial ization factors (from the c0 and c1 fast pll clock outputs) can be used. clock switchover and dynamic fast pll reconfiguration is available in high-speed differential i/o support mode. f for additional information on the fast pll, refer to the plls in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii handbook or the plls in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx handbook . figure 5?12 shows a block diagram of th e fast pll in high-speed differential i/o support mode. figure 5?12. fast pll block diagram notes to figure 5?12 : (1) stratix ii fast plls only support manual clock switchover. (2) the global or regional clock input can be driven by an output from another pll, a pi n-driven dedicated global or regional clock, or through a clock control block provided th e clock control block is fed by an output from another pll or pin-driven dedicated global or regional clock. (3) in high-speed differential i/o support mode, this high-s peed pll clock feeds the serdes. stratix ii devices only support one rate of data transfer per fast p ll in high-speed differential i/o support mode. (4) this signal is a high-speed differential i/o support serdes control signal. (5) if the design enables this 2 counter, the devi ce can use a vco frequency range of 150 to 520 mhz. char g e pump vco c1 8 8 4 4 8 clock input pfd c0 m loop filter ph ase f re qu e n c y detect o r v c o ph ase s e l ect ion s e l ectab l e at eac h pll ou tp u t po rt po st -s ca l e c oun ters global clocks diffioclk0 (3) loaden0 (4) diffioclk1 (3) loaden1 (4) re g ional clocks to dpa block global or re g ional clock (2) global or re g ional clock (2) c2 c3 n 4 clock (1) switchover circuitry sh aded po rt ion s o f t h e pll are r ec on f i g u rab l e k (5)
5?14 altera corporation stratix ii device handbook, volume 2 january 2008 clocking clocking the fast plls feed in to the different ial receiver and transmitter channels through the lvds/dpa clock network. the center fast plls can independently feed the banks above and below them. the corner plls can feed only the banks adjacent to them. figures 5?13 and 5?14 show the lvds and dpa clock networks of the stratix ii devices. figure 5?13. fast pll and lvds/dpa clock fo r ep2s15, ep2s30, and ep2s60 devices note (1) note to figure 5?13 : (1) figure 5?13 applies to ep2s60 devices in the 484 and 672 pin packages. 4 2 2 2 2 4 4 4 4 4 4 4 quadrant quadrant quadrant quadrant lvds clock fast pll 1 fast pll 2 dpa clock lvds clock dpa clock lvds clock fast pll 4 fast pll 3 dpa clock lvds clock dpa clock
altera corporation 5?15 january 2008 stratix ii device handbook, volume 2 high-speed differential i/o interfaces with dpa in stratix ii and stratix ii gx devices figure 5?14. fast pll and lvds/dpa clocks for ep2s60, ep2s90, ep2s130 and ep2s180 devices note (1) note to figure 5?14 : (1) figure 5?14 applies only to the ep2s60 in the 1020 stratix ii gx device. figures 5?15 and 5?16 show the fast pll and lvds/dpa clock of the stratix ii gx devices. figure 5?15. fast pll and lvds/dpa clock fo r ep2sgx30c/d and ep2sgx60c/d devices lvds clock dpa clock fast pll 1 fast pll 2 lvds clock dpa clock lvds clock dpa clock fast pll 4 fast pll 7 fast pll 10 fast pll 3 lvds clock dpa clock quadrant quadrant quadrant quadrant 4 4 2 4 4 4 4 2 2 2 2 2 fast pll 8 fast pll 9 2 2 4 2 2 4 4 4 quadrant quadrant quadrant quadrant lvds clock fast pll 1 fast pll 2 dpa clock lvds clock dpa clock no fast plls on ri g ht side of stratix ii gx devices
5?16 altera corporation stratix ii device handbook, volume 2 january 2008 clocking figure 5?16. fast pll and lvds/dpa clocks for ep2sgx60e, ep2sgx90 and ep2sgx130 devices source synchronous timing budget this section discusses the timing budget, waveforms, and specifications for source-synchronous signaling in stratix ii and stratix ii gx devices. lvds and hypertransport i/o standards enable high-speed data transmission. this high da ta transmission rate results in better overall system performance. to take advantage of fast system performance, it is important to understand how to anal yze timing for these high-speed signals. timing analysis for the differential block is different from traditional synchronous timi ng analysis techniques. rather than focusing on cloc k-to-output and setup times, source-synchronous timing analysis is based on the skew between the data and the clock signals. high-sp eed differential da ta transmission requires the use of timing paramete rs provided by ic vendors and is strongly influenced by board skew, cable skew, and clock jitter. this section defines the source-synchronous differential data orientation timing parameters, the timing budg et definitions for stratix ii and stratix ii gx devices, and how to us e these timing parameters to determine a design's maximum performance. quadrant quadrant quadrant quadrant no fast plls on ri g ht side of stratix ii gx devices lvds clock dpa clock fast pll 1 fast pll 2 lvds clock dpa clock fast pll 7 4 4 2 4 2 2 fast pll 8 2
altera corporation 5?17 january 2008 stratix ii device handbook, volume 2 high-speed differential i/o interfaces with dpa in stratix ii and stratix ii gx devices differential data orientation there is a set relationship between an external clock and the incoming data. for operation at 1 gbps and serdes factor of 10, the external clock is multiplied by 10, and phase-alignment can be set in the pll to coincide with the sampling window of each data bit. the data is sampled on the falling edge of the multiplied clock. figure 5?17 shows the data bit orientation of the ? 10 mode. figure 5?17. bit orientation in the quartus ii software differential i/o bit position data synchronization is necessary fo r successful data transmission at high frequencies. figure 5?18 shows the data bit or ientation for a channel operation. these figures are based on the following: serdes factor equals cl ock multiplication factor edge alignment is selected for phase alignment implemented in hard serdes for other serialization fa ctors use the quartus ii so ftware tools and find the bit position within the word. the bit positions after deserialization are listed in table 5?4 . figure 5?18 also shows a functional wa veform. timing waveforms may produce different results. altera recommends performing a timing simulation to predict actual device behavior. n-1 n-0 9 8 7 6 5 4 3 2 1 0 10 lvds bits msb lsb inclock/outclock data in high-frequency clock
5?18 altera corporation stratix ii device handbook, volume 2 january 2008 clocking figure 5?18. bit order for one channel of differential data previous cycle 76543 21 0 msb lsb tx_outclock tx_out xxxxxxxx xxxxxxxx current cycle next cycle transmitter channel operation (x 8 mode) xxxxxxxx rx_inclock rx_in 76543210 xxxxxxxxxxx xxxxx receiver channel operation (x 8 mode) rx_inclock rx_in rx_outclock rx_out [3..0] xx x x x x xx x xx x receiver channel operation (x4 mode) 3 210 x x x x x x x x x x x x 3210 rx_outclock rx_out [7..0] x x x x x x x x x x x x x x x x x x x x 7 6 5 4 3 2 1 0 x x x x
altera corporation 5?19 january 2008 stratix ii device handbook, volume 2 high-speed differential i/o interfaces with dpa in stratix ii and stratix ii gx devices table 5?4 shows the conventions for differential bit naming for 18 differential channels. the msb and lsb positions increase with the number of channels used in a system. receiver skew margin for non-dpa changes in system environment, su ch as temperature, media (cable, connector, or pcb) loading effect, the receiver's setup and hold times, and internal skew, reduce the sampling window for the receiver. the timing margin between the receiver?s clock input and the data input sampling window is called receiver skew margin (rskm). figure 5?19 shows the relationship between the rskm and the receiver?s sampling window. table 5?4. lvds bit naming receiver channel data number internal 8-bit parallel data msb position lsb position 170 2158 32316 43124 53932 64740 75548 86356 97164 10 79 72 11 87 80 12 95 88 13 103 96 14 111 104 15 119 112 16 127 120 17 135 128 18 143 136
5?20 altera corporation stratix ii device handbook, volume 2 january 2008 clocking tccs, rskm, and the sampling wind ow specifications are used for high-speed source-synchronous differential signals without dpa. when using dpa, these specifications are exchanged for the simpler single dpa jitter tolerance specification. for inst ance, the receiver skew is why each input with dpa selects a different phas e of the clock, th us removing the requirement for this margin. figure 5?19. differential high-speed timing diagram and timing budget for non-dpa rskm tui time unit interval (tui) rskm tccs internal clock fallin g ed g e t sw (min) bit n t sw (max) bit n rskm tccs t swbegin t swend samplin g window tccs 2 receiver input data transmitter output data internal clock synchronization external clock receiver input data internal clock external input clock timing budget timing diagram clock placement samplin g window (sw) rskm tccs
altera corporation 5?21 january 2008 stratix ii device handbook, volume 2 high-speed differential i/o interfaces with dpa in stratix ii and stratix ii gx devices differential pin placement guidelines in order to ensure proper high-s peed operation, differential pin placement guidelines have been es tablished. the quartus ii compiler automatically checks that these guidelines are followed and will issue an error message if these guidelines are not met. pll driving distance information is separated into guidel ines with and without dpa usage. high-speed differential i/o s and single-ended i/os when a differential channel or channe ls of side banks are used (with or without dpa), you must adhere to th e guidelines described in the following sections. single-ended i/os are allowed in the same bank as the lvds channels (with or without dpa) as long as the single-ended i/o standard uses the same v ccio as the lvds bank. single-ended inputs can be in the same lab row. outputs cannot be on the same lab row with lvds i/os. if input registers are used in the ioe, single-ended inputs cannot be in the same lab row as an lvds serdes block. lvds (non-serdes) i/os are allo wed in the same row as lvds serdes but the use of ioe registers are not allowed. single-ended outputs are limited to 120 ma drive strength on lvds banks (with or without dpa). lvttl equation for maximum number of i/os in an lvds bank: ? 120 ma = (number of lvttl outputs) (drive strength of each lvttl output) sstl-2 equation: ? 120 ma = (number of sstl-2 i/os ) (drive strength of each output) 2 lvttl and sstl-2 mix equation: ? 120 ma= (total drive strength of all lvttl outputs) + (total drive strength of all sstl2 outputs) 2 single-ended inputs can be in the same lab row as a differential channel using the serdes circuitry; however, ioe input registers are not available for the single-ended i/os placed in the same lab row as differential i/os. the same rule for input registers applies for non- serdes differential inputs placed within the same lab row as a serdes differential channel. the input register must be implemented within the core logic. the same rule for input registers applies for non-serdes differential inputs placed within the same lab row as a serdes differential channel.
5?22 altera corporation stratix ii device handbook, volume 2 january 2008 differential pin placement guidelines single-ended output pins must be at least one lab row away from differential output pins, as shown in figure 5?20 . figure 5?20. single-ended output pi n placement with respect to differential i/o pins dpa usage guidelines the stratix ii and stratix ii gx device have differential receivers and transmitters on the row banks of the device. each receiver has a dedicated dpa circuit to align the phase of the clock to the data phase of its associated channel. when a channel or channels of left or right banks are used in dpa mode, the guidelines listed below must be adhered to. fast pll/dpa channel driving distance each fast pll can drive up to 25 contiguous rows in dpa mode in a single bank (not including the re ference clock row). the unbonded serdes i/o rows are included in the 25 row calculation. these channels can be anywhere in the bank, their distance from the pll is not relevant, but the channels must be within 25 rows of each other. single-ended output pi n differential i/o pin single_ended input single-ended outputs not allowed row boundary
altera corporation 5?23 january 2008 stratix ii device handbook, volume 2 high-speed differential i/o interfaces with dpa in stratix ii and stratix ii gx devices unused channels can be within the 25 row span, but all used channels must be in dpa mode from the same fast pll. center fast plls can drive two i/o banks simultaneously, up to 50 channels (25 on the upper bank and 25 on the lower bank) as shown in figure 5?21 . if one center fast pll drives dpa channels in the upper and lower banks, the other center fast pll cannot be used for dpa. figure 5?21. driving capabilitie s of a center fast pll ref clk ref clk dpa dpa dpa dpa dpa dpa dpa dpa dpa dpa fast pll fast pll ref clk center pll used for dpa center pll used for dpa ref clk top channels driven by center pll bottom channels driven by center pll
5?24 altera corporation stratix ii device handbook, volume 2 january 2008 differential pin placement guidelines using corner and center fast plls if a differential bank is being dr iven by two fast plls, where the corner pll is driving one group and the center fast pll is driving another group, there must be at le ast 1 row of separation between the two groups of dpa channels (see figure 5?22 ). the two groups can operate at independent frequencies. not all the channels are bonded out of the die. each lab row is cons idered a channel, whether or not it has i/o support. no separation is necessary if a single fast pll is driving dpa channels as well as no n-dpa channels as long as the dpa channels are contiguous. figure 5?22. usage of corner and center fast plls driving dpa channels in a single bank ref clk ref clk diff i/o diff i/o diff i/o diff i/o diff i/o diff i/o diff i/o diff i/o diff i/o diff i/o fast pll fast pll ref clk center pll unused one unused channel for buffer corner pll used for dpa ref clk channels driven by center pll channels driven by corner pll
altera corporation 5?25 january 2008 stratix ii device handbook, volume 2 high-speed differential i/o interfaces with dpa in stratix ii and stratix ii gx devices using both center fast plls both center fast plls can be used for dpa as long as they drive dpa channels in their adjace nt quadrant only. see figure 5?23 . both center fast plls cannot be us ed for dpa if one of the fast plls drives the top and bottom banks, or if they are driving cross banks (e.g., the lower fast pll drives the top bank and the top fast pll drives the lower bank). figure 5?23. center fast pll usage when driving dpa channels ref clk ref clk dpa dpa dpa dpa dpa dpa dpa dpa dpa dpa fast pll fast pll ref clk center pll driving top bank center pll driving lower bank ref clk channels driven by the lower center pl l channels driven by the upper center pl l
5?26 altera corporation stratix ii device handbook, volume 2 january 2008 differential pin placement guidelines non-dpa differential i/o usage guidelines when a differential channel or channels of left or right banks are used in non-dpa mode, you must adhere to th e guidelines in the following sections. fast pll/differential i/o driving distance as shown in figure 5?24 , each fast pll can drive all the channels in the entire bank. figure 5?24. fast pll drivi ng capability when driving non-dpa differential channels fast pll diff i/o diff i/o fast pll ref clk diff i/o diff i/o diff i/o diff i/o ref clk diff i/o diff i/o diff i/o diff i/o diff i/o each pll can drive the entire bank ref clk ref clk center pll corner pll
altera corporation 5?27 january 2008 stratix ii device handbook, volume 2 high-speed differential i/o interfaces with dpa in stratix ii and stratix ii gx devices using corner and center fast plls the corner and center fast plls can be used as long as the channels driven by separate fast plls do no t have their transmitter or receiver channels interleaved. figure 5?25 shows illegal placement of differential channels when using corner and center fast plls. if one fast pll is driving transmitter channels only, and the other fast pll drives receiver channels only, the channels driven by those fast plls can overlap each other. center fast plls can be used for both transmitter and receiver channels. figure 5?25. illegal placement of interlaced duplex channels in an i/o bank board design considerations this section explains how to achiev e the optimal performance from the stratix ii and stratix ii gx high-sp eed i/o block and en sure first-time success in implementing a functional design with optimal signal quality. f for more information on board layout recommendations and i/o pin terminations, refer to an 224: high-speed board layout guidelines . fast pll diff i/o diff i/o fast pll ref clk diff i/o diff i/o diff i/o diff i/o ref clk diff i/o diff i/o diff i/o diff i/o diff i/o ref clk ref clk center pll corner pll interleaved duplex channel is not allowed duplex channel driven by center pll duplex channel driven by corner pll
5?28 altera corporation stratix ii device handbook, volume 2 january 2008 conclusion to achieve the best performance fr om the device, pay attention to the impedances of traces and connectors, differential routing, and termination techniques. f use this section together with the stratix ii device family data sheet in volume 1 of the stratix ii device handbook . the stratix ii and stratix ii gx high-s peed module generates signals that travel over the media at frequencies as high as one gbps. board designers should use the following guidelines: base board designs on controlled differential impedance. calculate and compare all parameters such as trace width, trac e thickness, and the distance between two differential traces. place external reference resistors as close to receiver input pins as possible. use surface mount components. avoid 90 or 45 corners. use high-performance connectors such as hmzd or vhdm connectors for backplane designs. two suppliers of high- performance connectors are teradyne corp ( www.teradyne.com ) and tyco international ltd. ( www.tyco.com ). design backplane and card traces so that trace impedance matches the connector?s or the termination?s impedance. keep an equal number of vias for both signal traces. create equal trace lengths to avoi d skew between signals. unequal trace lengths also result in misplaced crossing points and system margins when the tccs value increases. limit vias, because they caus e impedance discontinuities. use the common bypass capacitor va lues such as 0.001, 0.01, and 0.1 ? f to decouple the fast pll power and ground planes. you can also use 0.0047 ? f and 0.047 ? f. keep switching ttl signals away fr om differential signals to avoid possible noise coupling. do not route ttl clock signals to areas under or above the differential signals. route signals on adjacent laye rs orthogonally to each other. conclusion stratix ii and stratix ii gx high-speed differential inputs and outputs, with their dpa and data realignmen t circuitry, allo w users to build a robust multi-gigabit system. the dpa circuitry allows users to compensate for any timing skews resu lting from physical layouts. the data realignment circuitry allows th e devices to align the data packet between the transmitter and receiv er. together wi th the on-chip differential termination, stratix ii and stratix ii gx devices can be used as a single-chip solution for high-speed a pplications.
altera corporation 5?29 january 2008 stratix ii device handbook, volume 2 high-speed differential i/o interfaces with dpa in stratix ii and stratix ii gx devices referenced documents this chapter references the following documents: an 224: high-speed board layout guidelines dc & switching characteristic s chapter in volume 1 of the stratix ii device handbook dc & switching characteristics chapter in volume 1 of the stratix ii gx device handbook plls in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii handbook plls in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx handbook selectable i/o standards in st ratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii device handbook stratix ii device family data sheet in volume 1 of the stratix ii device handbook document revision history table 5?5 shows the revision history for this chapter. table 5?5. document revision history (part 1 of 2) date and document version changes made summary of changes january 2008, v2.2 updated figure 5?2 .? added ?referenced documents? section. ? minor text edits. ? added figure 5?9 .? updated ?receiver data realignment circuit? .? for the stratix ii gx device handbook only: formerly chapter 10. t he chapter number changed due to the addition of the stratix ii gx dynamic reconfiguration chapter. ? may 2007, v2.1 updated entire chapter to include stratix ii gx information. ? changed chapter part number. ? fixed two types in ?high-speed differential i/os and single-ended i/os? section ?
5?30 altera corporation stratix ii device handbook, volume 2 january 2008 document revision history february 2007 v2.0 this chapter changed from high-speed, source- synchronous differential i/o interfaces in stratix ii gx devices to ?high-speed differential i/o interfaces with dpa in stratix ii and stratix ii gx devices?. ? added the ?document revision history? section to this chapter. ? added ?and stratix ii gx? after each instance of ?stratix ii?. ? updated figures 10?4, 10?20, 10?22. ? updated note (4) of figure 10?2. ? updated table 10?1. ? updated the following sections: ?i/o banks? ?differential i/o termination? ?fast pll ? ?differential i/o bit position? ?dpa usage guidelines? ?fast pll/dpa channel driving distance? ? updated note (1) of tables 10?2 and 10?3. ? added note (5) to figure 10?11. ? added table 10?3. ? added figures 10?14, 10?15, 10?19. ? deleted old section called high-speed differential i/os and single-ended i/os and added a new ?high-speed differential i/os and single-ended i/os? section. ? deleted dpa and single-ended i/os section. ? updated title and added note (1) to figure 10?12. ? added note (1) to figure 10?13. ? april 2006, v1.2 updated all the megawizard plug-in manager figures to match the quartus ii software gui. updated ?dedicated source-synchronous circuitry? section, including table 10?3. ? february 2006, v1.1 updated chapter number from 9 to 10. updated figures 10?11 and 10?12. ? october 2005 v1.0 added chapter to the stratix ii gx device handbook . ? table 5?5. document revision history (part 2 of 2) date and document version changes made summary of changes
altera corporation section iv?1 preliminary section iv. digital signal processing (dsp) this section provides information for design and optimization of digital signal processing (dsp) functions an d arithmetic operations in the on- chip dsp blocks. this section contains the following chapter: chapter 6, dsp blocks in stratix ii and stratix ii gx devices revision history refer to each chapter for its own specific revision history. for information on when each chapter was updated, refer to the chapter revision dates section, which appears in the full handbook.
section iv?2 altera corporation preliminary digital signal processing (dsp) stratix ii device handbook, volume 2
altera corporation 6?1 january 2008 6. dsp blocks in stratix ii and stratix ii gx devices introduction stratix ? ii and stratix ii gx devices have dedicated digital signal processing (dsp) blocks optimized fo r dsp applications requiring high data throughput. these dsp blocks combined with the flexibility of programmable logic devices (plds), provide you with the ability to implement various high performanc e dsp functions easily. complex systems such as cdma2000, voice over internet protocol (voip), high- definition television (hdtv) requ ire high performance dsp blocks to process data. these system designs typically use dsp blocks as finite impulse response (fir) filters, comple x fir filters, fast fourier transform (fft) functions, discrete cosine transform (dct) functions, and correlators. stratix ii and stratix ii gx dsp bloc ks consist of a combination of dedicated blocks that perform mult iplication, addition, subtraction, accumulation, and summation operations. you can configure these blocks to implement arithmetic functions like multipliers, multiply-adders and multiply-accumulators which are necessary for most dsp functions. along with the dsp blocks, the trimatrix tm memory structures in stratix ii and stratix ii gx devices also support various soft multiplier implementations. the combination of soft multipliers and dedicated dsp blocks increases the number of multi pliers available in stratix ii and stratix ii gx devices and provides you with a wide variety of implementation options and flexibility when designing your systems. f see the stratix ii device family data sheet in volume 1 of the stratix ii device handbook or the stratix ii gx device family data sheet in volume 1 of the stratix ii gx device handbook for more information on stratix ii and stratix ii gx devices, respectively. dsp block overview each stratix ii and stratix ii gx device has two to four columns of dsp blocks that efficientl y implement multiplication, multiply-accumulate (mac) and multiply-add functions. figure 6?1 shows the arrangement of one of the dsp block columns with the surrounding labs. each dsp block can be configured to support: eight 9 9-bit multipliers four 18 18-bit multipliers one 36 36-bit multiplier sii52006-2.2
6?2 altera corporation stratix ii device handbook, volume 2 january 2008 dsp block overview figure 6?1. dsp blocks arranged in columns with adjacent labs the multipliers then feed an adder or accumulator block within the dsp block. stratix ii and stratix ii gx device multipliers support rounding and saturation on q1.15 input form ats. the dsp block also has input registers that can be configured to operate in a shift register chain for efficient implementation of functions like fir filters. the accumulator within the dsp block can be initialized to any value and supports rounding and saturation on q1.15 input formats to the multiplier. a single dsp block can be broken down to operate different configuration modes simultaneously. 1 for more information on q1.15 formatting, see ?saturation and rounding? on page 6?13 . dsp block column dsp block 4 lab rows
altera corporation 6?3 january 2008 stratix ii device handbook, volume 2 dsp blocks in stratix ii and stratix ii gx devices the number of dsp blocks per co lumn and the number of columns available increases with device density. table 6?1 shows the number of dsp blocks in each stratix ii device and the multipliers that you can implement. table 6?2 shows the number of dsp blocks in each stratix ii gx device and the multipliers that you can implement. table 6?1. number of dsp bloc ks in stratix ii devices note (1) device dsp blocks 9 9 multipliers 18 18 multipliers 36 36 multipliers ep2s15 12 96 48 12 ep2s30 16 128 64 16 ep2s60 36 288 144 36 ep2s90 48 384 192 48 ep2s130 63 504 252 63 ep2s180 96 768 384 96 note to ta b l e 6 ? 1 : (1) each device has either the number of 9 9-, 18 18-, or 36 36-bit multipliers shown. the total number of multipliers for each device is not the sum of all the multipliers. table 6?2. number of dsp blocks in stratix ii gx devices note (1) device dsp blocks 9 9 multipliers 18 18 multipliers 36 36 multipliers ep2sgx30c ep2sgx30d 16 128 64 16 ep2sgx60c ep2sgx60d ep2sgx60e 36 288 144 36 ep2sgx90e ep2sgx90f 48 384 192 48 ep2sgx130g 63 504 252 63 note to ta b l e 6 ? 2 : (1) each device has either the number of 9 9-, 18 18-, or 36 36-bit multipliers shown. the total number of multipliers for each device is not the sum of all the multipliers.
6?4 altera corporation stratix ii device handbook, volume 2 january 2008 dsp block overview in addition to the dsp block multiplie rs, you can use the stratix ii or stratix ii gx device?s trimatrix memory blocks for soft multipliers. the availability of soft multipliers in creases the number of multipliers available within the device. table 6?3 shows the total number of multipliers available in stratix ii devices using dsp blocks and soft multipliers. table 6?3. number of multipliers in stratix ii devices device dsp blocks (18 18) soft multipliers (16 16) (1) , (2) total multipliers (3) , (4) ep2s15 48 100 148 (3.08) ep2s30 64 189 253 (3.95) ep2s60 144 325 469 (3.26) ep2s90 192 509 701 (3.65) ep2s130 252 750 1,002 (3.98) ep2s130 384 962 1,346 (3.51) notes to ta b l e 6 ? 3 : (1) soft multipliers implemented in sum of multiplication mode. ram blocks are configured with 18-bit data widths and sum of coefficients up to 18-bits. (2) soft multipliers are only implemented in m4k and m512 trimatrix memory blocks, not m-ram blocks. (3) the number in parentheses represents the increase factor, which is the total number of multipliers with soft multipliers divided by the number of 18 18 multipliers supported by dsp blocks only. (4) the total number of multipliers may vary according to the multiplier mode used.
altera corporation 6?5 january 2008 stratix ii device handbook, volume 2 dsp blocks in stratix ii and stratix ii gx devices table 6?4 shows the total number of multipliers available in stratix ii gx devices using dsp blocks and soft multipliers. f refer to the stratix ii architectur e chapter in volume 1 of the stratix ii device handbook or the stratix ii gx architecture chapter in volume 1 of the stratix ii gx device handbook for more information on stratix ii or stratix ii gx trimatrix memory blocks. refer to an 306: implementing multipliers in fpga devices for more information on soft multipliers. table 6?4. number of multipliers in stratix ii gx devices device dsp blocks (18 18) soft multipliers (16 16) (1) , (2) total multipliers (3) , (4) ep2sgx30c ep2sgx30d 64 189 253 (3.95) ep2sgx60c ep2sgx60d ep2sgx60e 144 325 469 (3.26) ep2sgx90e ep2sgx90f 192 509 701 (3.65) ep2sgx130g 252 750 1,002 (3.98) notes to ta b l e 6 ? 4 : (1) soft multipliers implemented in sum of multiplication mode. ram blocks are configured with 18-bit data widths and sum of coefficients up to 18-bits. (2) soft multipliers are only implemented in m4k and m512 trimatrix memory blocks, not m-ram blocks. (3) the number in parentheses represents the increase factor, which is the total number of multipliers with soft multipliers divided by the number of 18 18 multipliers supported by dsp blocks only. (4) the total number of multipliers may vary according to the multiplier mode used.
6?6 altera corporation stratix ii device handbook, volume 2 january 2008 dsp block overview figure 6?2 shows the dsp block configured for 18 18 multiplier mode. figure 6?3 shows the 9 9 multiplier configuration of the dsp block. figure 6?2. dsp block in 18 18 mode adder/ subtractor/ accumulator 1 adder multiplier block prn clrn dq ena prn clrn dq ena prn clrn dq ena prn clrn dq ena prn clrn dq ena prn clrn dq ena prn clrn dq ena prn clrn dq ena prn clrn dq ena prn clrn dq ena prn clrn dq ena prn clrn dq ena summation block adder output block adder/ subtractor/ accumulator 2 q1.15 round/ saturate q1.15 round/ saturate q1.15 round/ saturate q1.15 round/ saturate to multitrack interconnect clrn dq ena from the row interface block optional serial shift register inputs from previous dsp block optional serial shift register outputs to next dsp block in the column optional input register stage with parallel input or shift register configuration optional pipline register stage summation stage for adding four multipliers together optional stage configurable as accumulator or dynamic adder/subtractor output selection multiplexer q1.15 round/ saturate q1.15 round/ saturate
altera corporation 6?7 january 2008 stratix ii device handbook, volume 2 dsp blocks in stratix ii and stratix ii gx devices figure 6?3. dsp block in 9 9 mode clrn dq ena clrn dq ena clrn dq ena adder/ subtractor/ 1a summation summation clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena adder/ subtractor/ 1b clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena adder/ subtractor/ 2a clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena adder/ subtractor/ 2b clrn dq ena clrn dq ena clrn dq ena output selection multiplexer to multitrack interconnect
6?8 altera corporation stratix ii device handbook, volume 2 january 2008 architecture architecture the dsp block consists of the following elements: a multiplier block an adder/subtractor/accumulator block a summation block input and output interfaces input and output registers multiplier block each multiplier block has the following elements: input registers a multiplier block a rounding and/or saturation stage for q1.15 input formats a pipeline output register
altera corporation 6?9 january 2008 stratix ii device handbook, volume 2 dsp blocks in stratix ii and stratix ii gx devices figure 6?4 shows the multiplier block architecture. figure 6?4. multiplier block architecture notes to figure 6?4 : (1) these signals are not registered or regist ered once to match the data path pipeline. (2) you can send these signals through either one or two pipeline registers. (3) the rounding and/or saturation is only supported in 18 18-bit signed multiplication for q1.15 inputs. input registers each multiplier operand can feed an input register or directly to the multiplier. the following dsp block signals control each input register within the dsp block: clock[3..0] ena[3..0] aclr[3..0] the input registers feed the multip lier and drive two dedicated shift output lines, shiftouta and shiftoutb . the dedicated shift outputs from one multiplier block directly f eed input registers of the adjacent multiplier below it within the same ds p block or the first multiplier in the next dsp block to form a shift register chain, as shown in figure 6?5 . the clrn dq ena data a data b shiftoutb shiftouta shiftina shiftinb aclr[3..0] clock[3..0] ena[3..0] signa (1) signb (1) clrn dq ena clrn dq ena sourcea sourceb q1.15 round/ saturate mult_saturate (1) mult_round (1) data out (2) multiplier block (3) dsp block pipeline register output register clrn dq ena mult_is_saturated
6?10 altera corporation stratix ii device handbook, volume 2 january 2008 architecture dedicated shift register chain spans a single column but longer shift register chains requiring multiple columns can be implemented using regular fpga routing resources. therefor e, this shift register chain can be of any length up to 768 registers in the largest member of the stratix ii or stratix ii gx device family. shift registers are useful in dsp functions like fir filters. when implementing 9 9 and 18 18 multip liers, you do not need external logic to create the shift register chai n because the input shift registers are internal to the dsp block. this impl ementation signific antly reduces the le resources required, avoids routing congestion, and results in predictable timing. stratix ii and stratix ii gx dsp blocks allow you to dynamically select whether a particular multiplier operan d is fed by regular data input or the dedicated shift register input using the sourcea and sourceb signals. a logic 1 value on the sourcea signal indicates that data a is fed by the dedicated scan-chain; a logic 0 value indicates that it is fed by regular data input. this feature allows the implementation of a dynamically loadable shift register where the shift register operates normally using the scan-chains and can also be loaded dynamically in parallel using the data input value.
altera corporation 6?11 january 2008 stratix ii device handbook, volume 2 dsp blocks in stratix ii and stratix ii gx devices figure 6?5. shift register chain note (1) note to figure 6?5 : (1) either data a or data b input can be set to a pa rallel input for constant co efficient multiplication. clrn dq ena data a data b a[n] b[n] clrn dq ena clrn dq ena shiftouta shiftoutb a[n ? 1] b[n ? 1] clrn dq ena clrn dq ena a[n ? 2] b[n ? 2] clrn dq ena clrn dq ena dsp block 0 dsp block 1 q1.15 round/ saturate q1.15 round/ saturate shiftouta shiftoutb shiftouta shiftoutb q1.15 round/ saturate clrn dq ena clrn dq ena
6?12 altera corporation stratix ii device handbook, volume 2 january 2008 architecture table 6?5 shows the summary of input register modes for the dsp block. multiplier stage the multiplier stage supports 9 9, 18 18, or 36 36 multipliers as well as other smaller multipliers in between these configurations. see ?operational modes? on page 6?21 for details. depending on the data width of the multiplier, a sing le dsp block can perform many multiplications in parallel. each multiplier operand can be a un ique signed or unsigned number. two signals, signa and signb , control the representation of each operand respectively. a logic 1 value on the signa signal indicates that data a is a signed number while a logic 0 value indicates an unsigned number. table 6?6 shows the sign of the multiplication result for the various operand sign repres entations. the result of the multiplication is signed if any one of the operands is a signed value. there is only one signa and one signb signal for each dsp block. therefore, all of the data a inputs feeding the same dsp block must have the same sign representati on. similarly, all of the data b inputs feeding the same dsp block must have the same si gn representation . the multiplier offers full precision regardless of the sign representation. 1 when the signa and signb signals are unus ed, the quartus ? ii software sets the multiplier to perform unsigned multiplication by default. table 6?5. input register modes register input mode 9 9 18 18 36 36 parallel input vvv shift register input vv table 6?6. multiplier sign representation data a (signa value) data b (signb value) result unsigned (logic 0) unsigned (logic 0) unsigned unsigned (logic 0) signed (logic 1) signed signed (logic 1) unsigned (logic 0) signed signed (logic 1) signed (logic 1) signed
altera corporation 6?13 january 2008 stratix ii device handbook, volume 2 dsp blocks in stratix ii and stratix ii gx devices saturation and rounding the dsp blocks have hardware suppo rt to perform optional saturation and rounding after each 18 18 mult iplier for q1.15 input formats. 1 designs must use 18 18 multip liers for the saturation and rounding options because the q1. 15 input format requires 16-bit input widths. 1 q1.15 input format multiplication requires signed multipliers. the most significant bit (msb) in the q1.15 input format represents the value?s sign bit. use signed multipliers to ensure the proper sign extension during multiplication. the q1.15 format uses 16 bits to re present each fixed point input. the msb is the sign bit, and the remain ing 15-bits are used to represent the value after the decimal place (or the fr actional value). this q1.15 value is equivalent to an integer number representation of the 16-bits divided by 2 15 , as shown in the following equations. all q1.15 numbers are between ?1 and 1. when performing multiplication, even though the q1.15 input only uses 16 of the 18 multiplier inputs, the enti re 18-bit input bus is transmitted to the multiplier. this is like a 1.17 inpu t, where the two least significant bits (lsbs) are always 0. the multiplier outp ut will be a 2.34 value (36 bits total) before performing any rounding or saturation. the two ms bs are sign bits. since the output only requires one sign bit, you can ignore one of the two msbs, resulting in a q1.34 value before rounding or saturation. when the design performs saturati on, the multiplier output gets saturated to 0x7fffffff in a 1.31 format. this uses bits [34..3] of the overall 36-bit multiplier output. the three lsbs are set to 0. the dsp block obtains the mult_is_saturated or accum_is_saturated overflow signal value from the lsb of the multiplier or accumulator output. ther efore, whenever saturation occurs, the lsb of the multiplier or ac cumulator output will send a 1 to the ?? 1 2 = 1 100 0000 0000 0000 = 0x4000 2 15 1 8 = 0 001 0000 0000 0000 = 0x1000 2 15
6?14 altera corporation stratix ii device handbook, volume 2 january 2008 architecture mult_is_saturated or accum_is_saturated overflow signal. at all other times, this overflow signal is 0 when saturation is enabled or reflects the value of the lsb of th e multiplier or accumulator output. when the design performs rounding , it adds 0x00008000 in 1.31 format to the multiplier output, and it only uses bits [34..15] of the overall 36-bit multiplier output. adding 0x00008000 in 1.31 format to the 36-bit multiplier result is equivalent to ad ding 0x0 0004 0000 in 2.34 format. the 16 lsbs are set to 0. figure 6?6 shows which bits are used when the design performs rounding and satura tion for the multiplication.
altera corporation 6?15 january 2008 stratix ii device handbook, volume 2 dsp blocks in stratix ii and stratix ii gx devices figure 6?6. rounding and saturation bits note to figure 6?6 : (1) both sign bits are the same. the design only uses one sign bit, and the other one is ignored. if the design performs a multiply_accumulate or multiply_add operation, the multiplier output is input to the adder/subtractor/accumula tor blocks as a 2.31 value, and the three lsbs are 0. 1 sign bit 2 lsbs 15 bits 2 sign bits (1) 3 lsbs 31 bits 1 sign bit 2 lsbs 15 bits 15 bits 19 lsbs are ignored 18 bits 2 sign bits (1) 3 lsbs 31 bits 2 sign bits (1) 2 sign bits (1) 3 lsbs 31 bits 18 18 36 111 1 1 100 0 00 0 00 0 00 00 00 00 00 00 00 00 000 0 0 01 0 00 00 00 00 00 00 0 0 00 00 00 00 00 00 0000 0 000 0 18 18 multiplication saturated output result rounded output result + =
6?16 altera corporation stratix ii device handbook, volume 2 january 2008 architecture pipeline registers the output from the multiplier can feed a pipeline register or this register can be bypassed. pipeline registers may be implemented for any multiplier size and increase the dsp block?s maximum performance, especially when using the subsequent dsp block adder stages. pipeline registers split up the long signal path between the adder/subtractor/accumulator bloc k and the adder /output block, creating two shorter paths. adder/output block the adder/output block ha s the following elements: an adder/subtractor/accumulator block a summation block an output select multiplexer output registers figure 6?7 shows the adder/output block architecture. the adder/output block can be configured as: an output interface an accumulator which ca n be optionally loaded a one-level adder a two-level adder with dynamic addition/subtraction control on the first-level adder the final stage of a 36-bit multiplier, 9 9 complex multiplier, or 18 18 complex multiplier the output select multiplexer sets the output configuration of the dsp block. the output registers can be us ed to register the output of the adder/output block. 1 the adder/output block cannot be used independently from the multiplier.
altera corporation 6?17 january 2008 stratix ii device handbook, volume 2 dsp blocks in stratix ii and stratix ii gx devices figure 6?7. adder/output block architecture note (1) notes to figure 6?7 : (1) the adder/output block is in 18 18 mode. in 9 9 mode, there are four adder/subtractor blocks and two summation blocks. (2) you can send these signals through a pipeline regi ster. the pipeline length can be set to 1 or 2. (3) q1.15 inputs are not available in 9 9 or 36 36 modes. adder/subtractor/accumulator block the adder/subtractor/accumulator block is the first level adder stage of the adder/output block. this block ca n be configured as an accumulator or as an adder/subtractor. adder/ subtractor/ accumulator 1 summation result a / accum_sload_upper_data result b result d addnsub1 (2) addnsub3 (2) signa (2) signb (2) accum_sload1 (2) accumulator feedback overflow0 adder/ output select multiplexer output registers subtractor/ accumulator 2 accumulator feedback overflow1 adder1_round (2) adder3_round (2) accum_sload0 (2) output register block q1.15 rounding q1.15 rounding result c / accum_sload_upper_data (3) (3)
6?18 altera corporation stratix ii device handbook, volume 2 january 2008 architecture accumulator when the adder/subtractor/accumu lator is configured as an accumulator, the output of the adder/output block feeds back to the accumulator as shown in figure 6?7 . the accumulator can be set up to perform addition only, subtraction only or the addnsub signal can be used to dynamically control the accu mulation direction. a logic 1 value on the addnsub signal indicates that the accumulator is performing addition while a logic 0 value indicates subtraction. each accumulator can be cleared by ei ther clearing the dsp block output register or by using the accum_sload signal. the accumulator clear using the accum_sload signal is independent from the resetting of the output registers so the accumulation can be cleared and a new one can begin without losing any clock cycles. the accum_sload signal controls a feedback multiplexer that specifie s that the output of the multiplier should be summed with a zero instea d of the accumulator feedback path. the accumulator can also be initiali zed/preloaded with a non-zero value using the accum_sload signal and the accum_sload_upper_data bus with one clock cycle latency. prel oading the accumulator is done by adding the result of the multiplie r with the value specified on the accum_sload_upper_data bus. as in the case of the accumulator clearing, the accum_sload signal specifies to the feedback multiplexer that the accum_sload_upper_data signal should feed the accumulator instead of the accu mulator feedback signal. the accum_sload_upper_data signal only loads the upper 36-bits of the accumulator. to load the entire accumulator, the value for the lower 16-bits must be sent through the mult iplier feeding that accumulator with the multiplier set to perform a multiplication by one. the overflow signal will go high on the positive edge of the clock when the accumulator detects an overflow or underflow. the overflow signal will stay high for only one clock cycl e after an overflow or underflow is detected even if the overflow or underflow condition is still present. a latch external to the dsp block has to be used to preserve the overflow signal indefinitely or until the latch is cleared. the dsp blocks support q1.15 input fo rmat saturation and rounding in each accumulator. the following signals are available that can control if saturation or rounding or both is performed to the output of the accumulator: accum_round accum_saturation accum_is_saturated output
altera corporation 6?19 january 2008 stratix ii device handbook, volume 2 dsp blocks in stratix ii and stratix ii gx devices each dsp block has two sets of accum_round and accum_saturation signals which control if rounding or saturation is performed on the accumulator output respectively (one set of signals for each accumulator). rounding and saturation of the accumulator output is only available when implementing an 16 16 multiplier-accumulator to conform to the bit widths required fo r q1.15 input format computation. a logic 1 value on the accum_round and accum_saturation signal indicates that rounding or saturation is performed while a logic 0 indicates that no rounding or saturati on is performed. a logic 1 value on the accum_is_saturated output signal tells you that saturation has occurred to the result of the accumulator. figure 6?10 shows the dsp block configured to perform multiplier- accumulator operations. adder/subtractor the addnsub1 or addnsub3 signals specify whether you are performing addition or subtraction. a logic 1 value on the addnsub1 or addnsub3 signals indicates that the adder/subtra ctor is performing addition while a logic 0 value indicates subtraction. these signals can be dynamically controlled using logic external to th e dsp block. if the first stage is configured as a subtractor, the output is a ? b and c ? d. the adder/subtractor block share the same signa and signb signals as the multiplier block. the signa and signb signals can be pipelined with a latency of one or two clock cycles or not. the dsp blocks support q1.15 input format rounding (not saturation) after each adder/subtractor. the addnsub1_round and addnsub3_round signals determine if roun ding is performed to the output of the adder/subtractor. the addnsub1_round signal controls the rounding of the top adder/subtractor and the addnsub3_round signal controls the rounding of the bottom adder/subtra ctor. rounding of the adder output is only available when implementing an 16 16 multiplier-adder to conform to the bit widths required fo r q1.15 input format computation. a logic 1 value on the addnsub_round signal indicates that rounding is performed while a logic 0 indicates that no rounding is performed. summation block the output of the adder/subtractor block feeds an optional summation block, which is an adder block that sums the outputs of both adder/subtractor bl ocks. the summation block is used when more than two multiplier results are summed. this is useful in applications such as fir filtering.
6?20 altera corporation stratix ii device handbook, volume 2 january 2008 architecture output select multiplexer the outputs of the different elemen ts of the adder/output block are routed through an output select multiplexer. depending on the operational mode of the dsp block, the output multiplexer selects whether the outputs of the dsp blocks comes from the outputs of the multiplier block, th e outputs of the adder/subt ractor/accumulator, or the output of the summation block. the output select multiplier configuration is set automatically by software, based on the dsp block operational mode you specify. output registers you can use the output registers to register the dsp block output. the following signals can control each output register within the dsp block: clock[3..0] ena[3..0] aclr[3..0] the output registers can be used in any dsp block operational mode. 1 the output registers form part of the accumulator in the multiply-accumulate mode. f refer to the stratix ii architecture chapter in volume 1 of the stratix ii device handbook or the stratix ii gx architecture chapter in volume 1 of the stratix ii gx device handbook for more information on the dsp block routing and interface.
altera corporation 6?21 january 2008 stratix ii device handbook, volume 2 dsp blocks in stratix ii and stratix ii gx devices operational modes the dsp block can be used in one of four basic operational modes, or a combination of two modes, depend ing on the application needs. table 6?7 shows the four basic operational modes and the number of multipliers that can be implemen ted within a single dsp block depending on the mode. the quartus ii software includes mega functions used to control the mode of operation of the multipliers. after you make the appropriate parameter settings using the megafunction?s megawizard ? plug-in manager, the quartus ii software automatical ly configures the dsp block. stratix ii and stratix ii gx dsp blocks can operate in different modes simultaneously. for example, a single dsp block can be broken down to operate a 9 9 multiplier as well as an 18 18 multiplier-adder where both multiplier's input a and input b have the same sign representations. this increases dsp block resource efficiency and allows you to implement more multipliers within a stratix ii or stratix ii gx device. the quartus ii software automatically places multipliers that can share the same dsp block resources within the same block. additionally, you can set up each stratix ii or stratix ii gx dsp block to dynamically switch between the following three modes: up to four 18-bit independent multipliers up to two 18-bit multiplier-accumulators one 36-bit multiplier table 6?7. dsp block operational modes mode number of multipliers 9 9 18 18 36 36 simple multiplier eight multipliers with eight product outputs four multipliers with four product outputs one multiplier multiply accumulate - two 52-bit multiply- accumulate blocks - two-multiplier adder four two-multiplier adder (two 9 9 complex multiply) two two-multiplier adder (one 18 18 complex multiply) - four-multiplier adder two four-multiplier adder one four-multiplier adder -
6?22 altera corporation stratix ii device handbook, volume 2 january 2008 operational modes each half of a stratix ii or stratix ii gx dsp block has separate mode control signals, which allows you to implement multiple 18-bit multipliers or multiplier-accumulators within the same dsp block and dynamically switch them independen tly (if they are in separate dsp block halves). if the design requires a 36-bit multiplier, you must switch the entire dsp block to accommodate th e it since the multiplier requires the entire dsp block. the smallest input bit width that supports dynamic mode switching is 18 bits. simple multiplier mode in simple multiplier mode, the dsp block performs individual multiplication operations for general-purpose multipliers and for applications such as computing eq ualizer coefficient updates which require many individual multiplication operations. 9- and 1 8 -bit multipliers each dsp block multiplier can be configured for 9- or 18-bit multiplication. a single dsp block can support up to eight individual 9 9 multipliers or up to four individual 18 18 multipliers. for operand widths up to 9-bits, a 9 9 multiplier will be implemented and for operand widths from 10- to 18-bits, an 18 18 multiplier will be implemented. figure 6?8 shows the dsp block in the simple multiplier operation mode.
altera corporation 6?23 january 2008 stratix ii device handbook, volume 2 dsp blocks in stratix ii and stratix ii gx devices figure 6?8. simple multiplier mode notes to figure 6?8 : (1) these signals are not registered or regist ered once to match the data path pipeline. (2) this signal has the same latency as the data path. (3) the rounding and saturation is only supported in 18- 18-bit signed multiplication for q1.15 inputs. the multiplier operands can accept sign ed integers, unsign ed integers or a combination of both. the signa and signb signals can be changed dynamically and can be registered in the dsp block. additionally, the multiplier inputs and result can be registered independently. the pipeline registers within the dsp block can be used to pipeline the multiplier result, increasing the perf ormance of the dsp block. 36-bit multiplier the 36-bit multiplier is also a simple multiplier mode but uses the entire dsp block, including the adder/ output block to implement the 36 36-bit multiplication operation. th e device inputs 18-bit sections of the 36-bit input into the four 18-bit multipliers. the adder/output block adds the partial produc ts obtained from the multipliers using the summation block. pipeline registers can be used between the multiplier stage and the summation block to sp eed up the multiplication. the 36 36-bit multiplier supports signed, unsigned as well as mixed sign multiplication. figure 6?9 shows the dsp block co nfigured to implement a 36-bit multiplier. clrn dq ena data a data b shiftoutb shiftouta shiftina shiftinb aclr[3..0] clock[3..0] ena[3..0] signa (1) signb (1) clrn dq ena clrn dq ena sourcea sourceb q1.15 round/ saturate mult_saturate (1) mult_round (1) output register data out mult_is_saturated (2) (3) clrn dq ena clrn dq ena multiplier block dsp block
6?24 altera corporation stratix ii device handbook, volume 2 january 2008 operational modes figure 6?9. 36-bit multiplier notes to figure 6?9 : (1) these signals are either not registered or registered once to match the pipeline. (2) these signals are either not registered, registered once , or registered twice to match the data path pipeline. clrn dq ena a[17..0] a[17..0] b[17..0] b[17..0] a[35..18] a[35..18] b[35..18] b[35..18] aclr clock ena signa (1) signb (1) clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena data out 36 36 multiplier adder signa ( 2 ) signb ( 2 ) 18 18 18 18 18 18 18 18
altera corporation 6?25 january 2008 stratix ii device handbook, volume 2 dsp blocks in stratix ii and stratix ii gx devices the 36-bit multiplier is useful for appl ications requiring more than 18-bit precision, for example, for mantissa multiplication of precision floating- point arithmetic applications. multiply accumulate mode in multiply accumulate mode, the output of the multiplier stage feeds the adder/output block which is configured as an accumulator or subtractor. figure 6?10 shows the dsp block configur ed to operate in multiply accumulate mode. figure 6?10. multiply accumulate mode notes to figure 6?10 : (1) the signa and signb signals are the same in the multipli er stage and the adder/output block. (2) these signals are not registered or regist ered once to match the data path pipeline. (3) you can send these signals through either one or two pipeline registers. (4) these signals match the latency of the data path. a single dsp block can implemen t up to two independent 18-bit multiplier accumula tors. the quartus ii soft ware implements smaller multiplier accumulators by tying the un used lower-order bits of the 18-bit multiplier to ground. the multiplier accumulator output ca n be up to 52-bits wide to account for a 36-bit multiplier result with 16-bi ts of accumulation. in this mode, the dsp block uses outp ut registers and the accum_sload and overflow clrn dq ena clrn dq ena data a data b data out overflow shiftoutb shiftouta shiftina shiftinb clrn dq ena clrn dq ena accumulator accum_sload (3) dq ena q1.15 round/ saturate accum_sload_upper_data (3) q1.15 round/ saturate mult_saturate (2) mult_round (2) accum_saturate (3) accum_round (3) addnsub (3) signa (1) , (3) signb (1) , (3) signa (1) , (2) signb (1) , (2) aclr[3..0] clock[3..0] ena[3..0] mult_is_saturated (4) accum_is_saturated (4) dq ena dq ena dq ena
6?26 altera corporation stratix ii device handbook, volume 2 january 2008 operational modes signals. the accum_sload signal can be used to clear the accumulator so that a new accumulation operation can begin without losing any clock cycles. this signal can be unregistered or registered once or twice. the accum_sload signal can also be used to preload the accumulator with a value specified on the accum_sload_upper_data signal with a one clock cycle penalty. the accum_sload_upper_data signal only loads the upper 36-bits (bits [51..16] of the accumulator). to load the entire accumulator, the value for the lower 16-bits (bits [15..0] ) must be sent through the multiplier feeding that ac cumulator with the multiplier set to perform a multiplication by one. bits [17..16] are overlapped by both the accum_sload_upper_data signal and the multiplier output. either one of these signals can be used to load bits [17..16] . the overflow signal indicates an overflow or underflow in the accumulator. this signal gets upda ted every clock cycle due to a new accumulation operation every cycle. to preserve the sign al, an external latch can be used. the addnsub signal can be used to specify if an accumulation or subtraction is performed dynamically. 1 the dsp block can implement just an accumulator (without multiplication) by specifying a multiply by one at the multiplier stage followed by an accumula tor to force the quartus ii software to implement the func tion within the dsp block. multiply add mode in multiply add mode, the output of the multiplier stage feeds the adder/output block which is configured as an adder or subtractor to sum or subtract the outputs of two or mo re multipliers. the dsp block can be configured to implement either a tw o-multiply add (where the outputs of two multipliers are added/subtracted together) or a four-multiply add function (where the outputs of four multipliers are added or subtracted together). 1 the adder block within the dsp bl ock can only be used if it follows multiplication operations. two-multiplier adder in the two-multiplier adder configuration, the dsp block can implement four 9-bit or smaller multiplier adde rs or two 18-bit multiplier adders. the adders can be configured to take the sum of both multiplier outputs or the difference of both multiplier ou tputs. you have the option to vary the summation/subtraction operation dynamically. these multiply add functions are useful for applications such as ffts and complex fir filters. figure 6?11 shows the dsp block configured in the two-multiplier adder mode.
altera corporation 6?27 january 2008 stratix ii device handbook, volume 2 dsp blocks in stratix ii and stratix ii gx devices figure 6?11. two-multiplier adder mode notes to figure 6?11 : (1) these signals are not registered or regist ered once to match the data path pipeline. (2) you can send these signals through a pipeline regi ster. the pipeline length can be set to 1 or 2. (3) these signals match the latency of the data path. complex multiply the dsp block can be configured to implement complex multipliers using the two-multiplier adder mode. a si ngle dsp block can implement one 18 18-bit complex multiplier or two 9 9-bit complex multipliers. a complex multiplicatio n can be written as: ( a + j b ) ( c + j d ) = (( a c ) ? ( b d )) + j (( a d ) + ( b c )) to implement this complex multiplication within the dsp block, the real part (( a c ) ? ( b d )) is implemented using two multipliers feeding one subtractor block while the imaginary part (( a d ) + ( b c )) is implemented using another two multipliers feedin g an adder block, for data up to 18-bits. figure 6?12 shows an 18-bit complex multiplication. for data widths up to 9-bits, a dsp block can perform two separate complex adder/ subtractor/ accumulator 1 prn clrn dq ena q1.15 round/ saturate data a 1 data b 1 shiftinb shiftina clrn dq ena clrn dq ena shiftouta shiftoutb clrn dq ena data out 1 aclr[3..0] clock[3..0] ena[3..0] signa (1) signb (1) mult_saturate (1) mult_round (1) signa (2) signb (2) addnsub_round (2) addnsub1 (2) mult1_is_saturated (3) mult0_is_saturated (3) q1.15 rounding prn clrn dq ena q1.15 round/ saturate data a 2 data b 2 dq ena clrn dq ena dq ena dq ena dq ena dq ena
6?28 altera corporation stratix ii device handbook, volume 2 january 2008 operational modes multiplication operations using eight 9-bit multipliers feeding four adder/subtractor/accumulator bloc ks. resources external to the dsp block must be used to route the correct real and imaginary input components to the appropriate multipli er inputs to perform the correct computation for the comple x multiplication operation. figure 6?12. complex multiplier us ing two-multiplier adder mode four-multiplier adder in the four-multiplier adder configur ation, the dsp block can implement one 18 18 or two individual 9 9 multiplier adders. these modes are useful for implementing one-dimensional and two-dimensional filtering applications. the four-multiplier adder is performed in two addition stages. the outputs of two of the four multipliers are initially summed in the two first-stage adder/ subtractor/accumulator blocks. the results of these two adder/subtractor/accumulator blocks are then summed in the final stage summation block to prod uce the final four-multiplier adder result. figure 6?13 shows the dsp block configur ed in the four-multiplier adder mode. subtractor 36 36 18 18 18 37 a 18 (real part) adder 36 36 18 18 37 (imaginary part) 18 18 18 dsp block (a c) ? (b d) (a d) + (b c) 18 18 18 b d a d b c c
altera corporation 6?29 january 2008 stratix ii device handbook, volume 2 dsp blocks in stratix ii and stratix ii gx devices figure 6?13. four-multiplier adder mode notes to figure 6?13 : (1) these signals are not registered or regist ered once to match the data path pipeline. (2) you should send these signals through the pipeline register to match the latency of the data path. (3) these signals match the latency of the data path. (4) the rounding and saturation is only supported in 18- 18-bit signed multiplication for q1.15 inputs. signa (2) signb (2) addnsub1/3_round (2) addnsub3 (2) addnsub1 (2) adder adder/ subtractor/ accumulator 1 prn clrn dq ena q1.15 round/ saturate data a 1 data b 1 shiftinb shiftina clrn dq ena clrn dq ena aclr[3..0] clock[3..0] ena[3..0] signa (1) signb (1) mult_saturate (1) mult_round (1) mult1_is_saturated (3) mult0_is_saturated (3) q1.15 rounding prn clrn dq ena prn clrn dq ena shiftouta shiftoutb data a 2 data b 2 dq ena clrn dq ena adder/ subtractor/ accumulator 1 data a 1 data b 1 clrn dq ena clrn dq ena clrn dq ena data out 1 mult1_is_saturated (3) mult0_is_saturated (3) q1.15 rounding data a 2 data b 2 dq ena clrn dq ena prn clrn dq ena q1.15 round/ saturate prn clrn dq ena prn clrn dq ena q1.15 round/ saturate prn clrn dq ena prn clrn dq ena prn clrn dq ena prn clrn dq ena prn clrn dq ena q1.15 round/ saturate prn clrn dq ena (4) (4) (4) (4) (4) (4)
6?30 altera corporation stratix ii device handbook, volume 2 january 2008 operational modes fir filter the four-multiplier adder mode can be used to implement fir filter and complex fir filter applications. to do this, the dsp block is set up in a four-multiplier adder mode with one se t of input registers configured as shift registers using the dedicated shift register chain. the set of input registers configured as shift registers will contain the input data while the inputs configured as regular inputs will hold the filter coefficients. figure 6?14 shows the dsp block configured in the four-multiplier adder mode using input shift registers.
altera corporation 6?31 january 2008 stratix ii device handbook, volume 2 dsp blocks in stratix ii and stratix ii gx devices figure 6?14. fir filter implemented usi ng the four-multiplier adder m ode with input shift registers data a coefficient 0 clrn dq ena clrn dq ena clrn dq ena a[ n ] coefficient 0 (to adder) coefficient 1 clrn dq ena clrn dq ena clrn dq ena a[ n ? 1] coefficient 1 (to adder) coefficient 2 clrn dq ena clrn dq ena clrn dq ena a[ n ? 2] coefficient 2 (to adder) 18 18 18 18
6?32 altera corporation stratix ii device handbook, volume 2 january 2008 software support the built-in input shift register chai n within the dsp block eliminates the need for shift registers externally to the dsp block in logic elements (les). this architecture feature simplifies the filter design and improves the filter performance because all the filter circuitry is localized within the dsp block. 1 input shift registers for the 36-bi t simple multiplier mode have to be implemented using external registers to the dsp block. a single dsp block can implement a fo ur tap 18-bit fir filter. for filters larger than four taps, the dsp blocks can be cascaded with additional adder stages implemented using les. software support altera provides two distinct method s for implementing various modes of the dsp block in your design: instan tiation and inferenc e. both methods use the following three quartus ii megafunctions: lpm_mult altmult_add altmult_accum you can instantiate the megafunction s in the quartus ii software to use the dsp block. alternatively, with in ference, you can create a hdl design an synthesize it using a third-party synthesis tool like leonardospectrum or synplify or quartus ii native sy nthesis that infers the appropriate megafunction by recognizing multipliers, multiplier adders, and multiplier accumula tors. using either method, the quartus ii software maps the functionality to the ds p blocks during compilation. f see quartus ii on-line help for inst ructions on using the megafunctions and the megawizard plug-in manager. f for more information, see the synthesis section in design and synthesis (volume 1) of the quartus ii development software handbook . conclusion the stratix ii and stratix ii gx de vice dsp blocks are optimized to support dsp applications requiring high data throughput such as fir filters, fft functions and encoders. th ese dsp blocks are flexible and can be configured to implement one of several operational modes to suit a particular application. the built-in shift register chain, adder/subtractor/accumulator block and the su mmation block minimizes the amount of external logic requir ed to implement these functions, resulting in efficient resource utilization and improved performance and data throughput fo r dsp applications. the quartus ii
altera corporation 6?33 january 2008 stratix ii device handbook, volume 2 dsp blocks in stratix ii and stratix ii gx devices software, together with the leonardospectrum ? and synplify software provide a complete and easy-to-us e flow for implementing these multiplier functions in the dsp blocks. referenced documents this chapter references the following documents: an 306: implementing mult ipliers in fpga devices design and synthesis (volume 1) of the quartus ii development software handbook stratix ii architectur e chapter in volume 1 of the stratix ii device handbook stratix ii gx architecture chapter in volume 1 of the stratix ii gx device handbook stratix ii device family data sheet in volume 1 of the stratix ii device handbook stratix ii gx device family data sheet in volume 1 of the stratix ii gx device handbook document revision history table 6?8 shows the revision history for this chapter. table 6?8. document revision history date and document version changes made summary of changes january 2008 v2.2 added the ?referenced documents? section. ? minor text edits. ? no change for the stratix ii gx device handbook only: formerly chapter 11. the chapter number changed due to the addition of the stratix ii gx dynamic reconfiguration chapter. no content change. ? february 2007 v2.1 added the ?document revision history? section to this chapter. ? no change formerly chapter 10. chapter number change only due to chapter addition to section i in february 2006; no content change. ? october 2005 v2.0 added chapter to the stratix ii gx device handbook . ?
6?34 altera corporation stratix ii device handbook, volume 2 january 2008 document revision history
altera corporation section v?1 preliminary section v. configuration& remote system upgrades this section provides configuration information for all of the supported configuration schemes for stratix ? ii devices. these configuration schemes use either a microprocessor, configuration device, or download cable. there is detailed information on how to design with altera enhanced configuration devices which includes information on how to manage multiple configuration files and access the on-chip flash memory space. the last chapter shows designers how to perform remote and local upgrades for their designs. this section contains the following chapters: chapter 7, configuring strati xii and stratixiigx devices chapter 8, remote system upgrades with stratix ii and stratix ii gx devices chapter 9, ieee 1149.1 (jtag) boun dary-scan testing for stratix ii and stratix ii gx devices revision history refer to each chapter for its own specific revision history. for information on when each chapter was updated, refer to the chapter revision dates section, which appears in the full handbook.
section v?2 altera corporation preliminary configuration& remote system upgrades stratix ii device handbook, volume 2
altera corporation 7?1 january 2008 7. configuring stratix ii and stratix ii gx devices introduction stratix ? ii and stratix ii gx devices use sram cells to store configuration data. because sram memory is vola tile, configuration data must be downloaded to stratix ii and stratix i i gx devices each time the device powers up. stratix ii and stratix ii gx devices can be configured using one of five configuration schemes: the fast passive parallel (fpp), active serial (as), passive serial (ps), passive parallel asynchronous (ppa), and joint test action group (jtag) conf iguration schemes. all configuration schemes use either an external controller (for example, a max ? ii device or microprocessor) or a configuration device. configuration devices the altera enhanced configuratio n devices (epc16, epc8, and epc4) support a single-device configuration solution for high-density devices and can be used in the fpp and ps configuration schemes. they are isp-capable through its jtag interf ace. the enhanced configuration devices are divided into two major blocks, the controller and the flash memory. f for information on enhanced conf iguration devices, refer to the enhanced configuration devices (epc4, epc8 & epc16) data sheet in volume 2 of the configuration handbook . the altera serial configuration de vices (epcs64, ep cs16, and epcs4) support a single-device configuration solution for stratix ii and stratix ii gx devices and are used in the as configuration scheme. serial configuration devices offer a low cost, low pin count configuration solution. f for information on serial configuration devices, refer to the serial configuration devices (epcs1, epcs 4, epcs16, epcs64, and epcs128) data sheet chapter in volume 2 of the configuration handbook . the epc2 configuration devices provide configuration support for the ps configuration scheme. the epc2 device is isp-capable through its jtag interface. the epc2 device can be cascaded to hold large configuration files. f for more information on epc2 configuration devices, refer to the configuration devices for sram -based lut devices data sheet chapter in volume 2 of the configuration handbook . sii52007-4.5
7?2 altera corporation stratix ii device handbook, volume 2 january 2008 introduction the configuration scheme is selected by driving the stratix ii or stratix ii gx device msel pins either high or low as shown in table 7?1 . the msel pins are powered by the v ccio power supply of the bank they reside in. the msel[3..0] pins have 9-k ? internal pull-down resistors that are always active. during power-on reset (por) and during reconfiguration, the msel pins have to be at lvttl v il and v ih levels to be considered a logic low and logic high. 1 to avoid any problems with detecting an incorrect configuration scheme, hard-wire the msel[] pins to v ccpd and gnd, without any pull-up or pull-down re sistors. do not drive the msel[] pins by a microprocessor or another device. table 7?1. stratix ii and st ratix ii gx configuration schemes (part 1 of 2) configuration scheme msel3 msel2 msel1 msel0 fast passive parallel (fpp) 0000 passive parallel asynchronous (ppa) 0001 passive serial (ps) 0010 remote system upgrade fpp (1) 0100 remote system upgrade ppa (1) 0101 remote system upgrade ps (1) 0110 fast as (40 mhz) (2) 1000 remote system upgrade fast as (40 mhz) (2) 1001 fpp with decompression and/or design security feature enabled (3) 1011 remote system upgrade fpp with decompression and/or design security feature enabled (1) , (3) 1100 as (20 mhz) (2) 1101 remote system upgrade as (20 mhz) (2) 1110 jtag-based configuration (5) (4) (4) (4) (4)
altera corporation 7?3 january 2008 stratix ii device handbook, volume 2 configuring stratix ii and stratix ii gx devices stratix ii and stratix ii gx devices offer design security, decompression, and remote system upgrade features. design security using configuration bitstream encryption is available in stratix ii and stratix ii gx devices, which protects your designs. stratix ii and stratix ii gx devices can receive a compressed configuration bi t stream and decompress this data in real-time, reducing storage requ irements and configuration time. you can make real-time system upgrades from remote locations of your stratix ii and stratix ii gx designs with the remote system upgrade feature. table 7?2 and table 7?3 show the uncompressed configuration file sizes for stratix ii and stratix ii gx devices, respectively. notes to ta b l e 7 ? 1 : (1) these schemes require that you drive the runlu pin to specify either remote update or local update. for more information about remote system upgrades in stratix ii devices, refer to the remote system upgrades with stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii device handbook or the remote system upgrades with stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook . (2) only the epcs16 and epcs64 devices support up to a 40 mhz dclk . other epcs devices support up to a 20 mhz dclk . refer to the serial configuration devices (epcs1, epcs4, epcs16, epcs64, and epcs128) data sheet for more information. (3) these modes are only supported when using a max ii device or a microprocessor with flash memory for configuration. in these modes, the host system must output a dclk that is 4 the data rate. (4) do not leave the msel pins floating. connect them to v ccpd or ground. these pins support the non-jtag configuration scheme used in production. if only jtag configuration is used, you should connect the msel pins to ground. (5) jtag-based configuration takes precedence ov er other configuration schemes, which means msel pin settings are ignored. table 7?1. stratix ii and st ratix ii gx configuration schemes (part 2 of 2) configuration scheme msel3 msel2 msel1 msel0 table 7?2. stratix ii uncompressed .rbf sizes notes (1) , (2) device data size (bits) data size (mbytes) ep2s15 4,721,544 0.590 ep2s30 9,640,672 1.205 ep2s60 16,951,824 2.119 ep2s90 25,699,104 3.212 ep2s130 37,325,760 4.666 ep2s180 49,814,760 6.227 notes to ta b l e 7 ? 2 : (1) these values are final. (2) .rbf : raw binary file.
7?4 altera corporation stratix ii device handbook, volume 2 january 2008 configuration features use the data in table 7?2 to estimate the file size before design compilation. different configuration file formats, such as a hexidecimal ( .hex ) or tabular text file ( .ttf ) format, will have different file sizes. however, for any specific version of the quartus ? ii software, any design targeted for the same device will have the same uncompressed configuration file size. if you are using compression, the file size can vary after each compilation because the compression ratio is dependent on the design. this chapter explains the stratix ii and stratix ii gx device configuration features and describes how to co nfigure stratix ii and stratix ii gx devices using the supported configuration schemes. this chapter provides configuration pin descriptions and the stratix ii and stratix ii gx device configuration file fo rmats. in this chapter, the generic term device(s) includes all stratix ii and stratix ii gx devices. f for more information on setting device configuration options or creating configuration files, refer to software settings in volume 2 of the configuration handbook . configuration features stratix ii and stratix ii gx devices offer configuration data decompression to reduce configuration f ile storage, design security using data encryption to protect your design s, and remote system upgrades to allow for remotely updating your stratix ii and stratix ii gx designs. table 7?4 summarizes which configuration features can be used in each configuration scheme. table 7?3. stratix ii gx uncompressed .rbf sizes note (1) device data size (bits) data size (mbytes) ep2sgx30c ep2sgx30d 9,640,672 1.205 ep2sgx60c ep2sgx60d ep2sgx60e 16,951,824 2.119 ep2sgx90e ep2sgx90f 25,699,104 3.212 ep2sgx130g 37,325,760 4.666 note to ta b l e 7 ? 3 : (1) .rbf : raw binary file.
altera corporation 7?5 january 2008 stratix ii device handbook, volume 2 configuring stratix ii and stratix ii gx devices configuration data decompression stratix ii and stratix ii gx devices support configuration data decompression, which saves configur ation memory space and time. this feature allows you to store comp ressed configuration data in configuration devices or other memory and transmit this compressed bit stream to stratix ii and stratix ii gx devices. during configuration, stratix ii and stratix ii gx devices automatically recognize the compressed file format and decompress es the bit stream in real time and programs its sram cells. 1 data indicates that compression typically reduces configuration bit stream size by 35 to 55 % . stratix ii and stratix ii gx devices support decompression in the fpp (when using a max ii device/micro processor + flas h), as, and ps configuration schemes. decompression is not supported in the ppa configuration scheme nor in jtag-based configuration. table 7?4. stratix ii and stratix i i gx configuration features configuration scheme configuration method desi gn security decompression remote system upgrade fpp max ii device or a microprocessor with flash memory v (1) v (1) v enhanced configuration device v (2) v as serial configuration device vvv (3) ps max ii device or a microprocessor with flash memory vvv enhanced configuration device v v v download cable vv ppa max ii device or a microprocessor with flash memory v jtag max ii device or a microprocessor with flash memory notes to ta b l e 7 ? 4 : (1) in these modes, the host system must send a dclk that is 4 the data rate. (2) the enhanced configuration device decompression feature is available, while the stratix ii and stratix ii gx decompression feature is not available. (3) only remote update mode is supported when using the as configuration scheme. local update mode is not supported.
7?6 altera corporation stratix ii device handbook, volume 2 january 2008 configuration features 1 when using fpp mode, the inte lligent host must provide a dclk that is 4 the data rate. therefore, the configuration data must be valid for four dclk cycles. the decompression feature supported by stratix ii and stratix ii gx devices is different from the decompression feature in enhanced configuration devices (epc16, epc8, and epc4 devices), although they both use the same compression al gorithm. the data decompression feature in the enhanced configurat ion devices allows them to store compressed data and decompress the bi tstream before transmitting it to the target devices. when using stratix ii and stratix ii gx devices in fpp mode with enhanced configuration devices, the decompression feature is available only in the enhanced config uration device, not the stratix ii or stratix ii gx device. in ps mode, use the stratix ii or stratix ii gx decompression feature because sending compressed configuration data reduces configuration time. do not use both the stratix i i or stratix ii gx device and the enhanced configuration device decompression features simultaneously. the compression algorithm is not intended to be recursive and could expand the configuration file in stead of compressing it further. when you enable compression, th e quartus ii software generates configuration files with compressed configuration data. this compressed file reduces the storage requirements in the configuration device or flash memory, and decreases the time need ed to transmit the bitstream to the stratix ii or stratix ii gx device. the time required by a stratix ii or stratix ii gx device to decompress a configuration file is less than the time needed to transmit the co nfiguration data to the device. there are two ways to enable compression for stratix ii and stratix ii gx bitstreams: before design compilation (in the compiler settings menu) and after design compilation (in the convert programming files window). to enable compression in the project?s compiler settings, select device under the assignments menu to bring up the settings window. after selecting your stratix ii or stratix ii gx device, open the device & pin options window, and in the general settings tab enable the check box for generate compressed bitstreams (as shown in figure 7?1 ).
altera corporation 7?7 january 2008 stratix ii device handbook, volume 2 configuring stratix ii and stratix ii gx devices figure 7?1. enabling compression for stratix ii and stratix ii gx bitstreams in compiler settings compression can also be enabled when creating programming files from the convert programming files window. 1. click convert programming files (file menu). 2. select the programming file type (pof, sram hexout, rbf, or ttf). 3. for pof output files, select a configuration device. 4. in the input files to convert box, select sof data . 5. select add file and add a stratix ii or stratix ii gx device sof(s).
7?8 altera corporation stratix ii device handbook, volume 2 january 2008 configuration features 6. select the name of the file you added to the sof data area and click properties . 7. check the compression check box. when multiple stratix ii or strati x ii gx devices are cascaded, you can selectively enable the compression feat ure for each device in the chain if you are using a serial configuration scheme. figure 7?2 depicts a chain of two stratix ii or stratix ii gx devices. the first stratix ii or stratix ii gx device has compression enabled and therefore receives a compressed bit stream from the configuration de vice. the second stratix ii or stratix ii gx device has the compression feature disabled and receives uncompressed data. in a multi-device fpp configuration chain all stratix ii or stratix ii gx devices in the chain must either enable of disable the decompression feature. you can not selectively enable the compression feature for each device in the chain because of the data and dclk relationship. figure 7?2. compressed and uncompressed configuration data in the same configuration file you can generate programming files for this setup from the convert programming files window (file menu) in the quartus ii software. design security using config uration bitstream encryption stratix ii and stratix ii gx devices are th e industry?s first devices with the ability to decrypt a configuratio n bitstream using the advanced encryption standard (aes) algorith m?the most advanced encryption algorithm available today. when usin g the design security feature, a nce gnd nceo de c ompression controller stratix ii or stratix ii gx fpga nce nceo n.c. s er i a l c on f i g u rat ion data c om pressed u n c om pressed c on f i g u rat ion data c on f i g u rat ion data serial or enhanced confi g uration device stratix ii or stratix ii gx fpga
altera corporation 7?9 january 2008 stratix ii device handbook, volume 2 configuring stratix ii and stratix ii gx devices 128-bit security key is stored in the stratix ii or stratix ii gx device. in order to successfully configure a strati x ii or stratix ii gx device that has the design security feature enabled, it must be configured with a configuration file that wa s encrypted using the same 128-bit security key. the security key can be stored in non- volatile memory inside the stratix ii or stratix ii gx device. this non-volatile memory does not require any external devices, such as a battery back-up, for storage. 1 when using a serial configuration scheme such as passive serial (ps) or active serial (as), config uration time is the same whether or not the design security feature is enabled. if the fast passive parallel (fpp) scheme is used with the design security or decompression feature, a 4 dclk is required. this results in a slower configuration time when compared to the configuration time of an fpga that has neither the design security, nor decompression feature enabled. for more information about this feature, contact al tera applications group. remote system upgrade stratix ii and stratix ii gx devices feature remote and local update. f for more information about this feature, refer to the remote system upgrades with stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii device handbook or the remote system upgrades with stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook power-on reset circuit the por circuit keeps the entire syst em in reset until the power supply voltage levels have stabilized on power-up. upon power-up, the device does not release nstatus until v ccint , v ccpd , and v ccio of banks 3, 4, 7, and 8 are above the device?s por trip point. on power down, v ccint is monitored for brown-out conditions. the passive serial (ps) mode ( msel[3,2,1,0] = 0010 ) and the fast passive parallel (fpp) mode ( msel[3,2,1,0] = 0000 ) always set bank 3 to use the lower por trip point consistent with 1.8- and 1.5-v signaling, regardless of the vccsel setting. for all other configuration modes, vccsel selects the por trip-point level. refer to the section ?vccsel pin? on page 7?10 for more details. in stratix ii devices, a pin-selectable option porsel is provided that allows you to select between a typi cal por time setting of 12 ms or 100 ms. in both cases, you can extend the por time by using an external component to assert the nstatus pin low.
7?10 altera corporation stratix ii device handbook, volume 2 january 2008 configuration features v ccpd pins stratix ii and stratix ii gx devices also offer a new power supply, v ccpd , which must be connected to 3.3-v in order to power the 3.3-v/2.5-v buffer available on the configurat ion input pins and jtag pins. v ccpd applies to all the jtag input pins ( tck , tms , tdi , and trst ) and the configuration pins when vccsel is connected to ground. refer to table 7?5 for information on the pins affected by vccsel . 1 v ccpd must ramp-up from 0-v to 3.3-v within 100 ms. if v ccpd is not ramped up within this sp ecified time, your stratix ii or stratix ii gx device will not configure successfully. if your system does not allow for a v ccpd ramp-up time of 100 ms or less, you must hold nconfig low until all power supplies are stable. vccsel pin the vccsel pin selects the type of input buffer used on configuration input pins and it selects the por trip point voltage level for v ccio bank 3 powered by vccio3 pins. 1 for more information, refer to table 7?24 on page 7?105 . the configuration input pins and the pll_ena pin ( table 7?5 ) have a dual buffer design. these pins have a 3.3-v/2.5-v input buffer and a 1.8-v/1.5-v input buffer. the vccsel input pin selects which input buffer is used during configuratio n. the 3.3-v/2.5-v input buffer is powered by v ccpd , while the 1.8-v/1.5-v input buffer is powered by v ccio . after configuration, the dual-p urpose configuration pins are powered by the v ccio pins of the bank in which they reside. table 7?5 shows the pins affected by vccsel .
altera corporation 7?11 january 2008 stratix ii device handbook, volume 2 configuring stratix ii and stratix ii gx devices vccsel is sampled during power-up. therefore, the vccsel setting cannot change on the fly or during a reconfiguration. the vccsel input buffer is powered by v ccint and has an internal 5-k ?? pull-down resistor that is always active. 1 vccsel must be hardwired to v ccpd or gnd. a logic high selects the 1.8-v/1.5-v input buffer, and a logic low selects the 3.3-v/2.5-v input buffer. vccsel should be set to comply with the logic levels driven out of the configuration device or max ii device or a microprocessor with flash memory. vccsel also sets the por trip point for i/ o bank 3 to ensure that this i/o bank has powered up to the appropriate voltage levels before configuration begins. for pa ssive serial (ps) mode ( msel[3..0] = 0010 ) and for fast passive parallel (fpp) mode ( msel[3..0] = 0000 ) the por circuitry selects the trip point associ ated with 1.5-v/1.8-v signaling. for all other configuration modes defined by msel[3..0] settings (other table 7?5. pins affected by the voltage level at vccsel pin vccsel = low (connected to gnd) vccsel = high (connected to v ccpd ) nstatus (when used as an input) 3.3/2.5-v input buffer is selected. input buffer is powered by v ccpd . 1.8/1.5-v input buffer is selected. input buffer is powered by v ccio of the i/o bank. these input buffers are 3.3 v tolerant. nconfig conf_done (when used as an input) data[7..0] nce dclk (when used as an input) cs nws nrs ncs clkusr dev_oe dev_clrn runlu pll_ena
7?12 altera corporation stratix ii device handbook, volume 2 january 2008 configuration features than 00x0 (msel[1] = x , ?don't care?), vccsel=gnd selects the higher i/o bank 3 por trip point for 2.5-v/3.3-v signaling and vccsel=vccpd selects the lower i/o bank 3 por trip point associated with 1.5-v/1.8-v signaling. for all configuration modes with msel[3..0] not equal to 00x0 (msel[1] = x , ?don't care?), if vccio of configuration bank 3 is powered by 1.8-v or 1.5-v and vccsel = gnd , the voltage supplied to this i/o bank(s) may never reach the por trip point, which prevents the device from beginning configuration. if the vccio of i/o bank 3 is powered by 1.5- or 1.8-v and the configuration signals used require 3.3- or 2.5-v signaling, you should set vccsel to vccpd to enable the 1.8-/1.5-v inpu t buffers for configuration. the 1.8-v/1.5-v input buffers are 3.3-v tolerant. 1 the fast passive parallel (fpp) and passive serial (ps) modes always enable bank 3 to use the por trip point to be consistent with 1.8- and 1.5-v signal ing, regardless of the vccsel setting. table 7?6 shows how you should set vccsel depending on the configuration mode, the voltage level on vccio3 pins that power bank 3, and the supported config uration input voltages. table 7?6. supported v ccsel setting based on mode, vccio3, and input configuration voltage configuration mode v ccio (bank 3) supported configuration input voltages v ccsel all modes 3.3-v/2.5-v 3.3-v/2.5-v gnd all modes 1.8-v/1.5-v 3.3-v/2.5-v v ccpd (1) all modes 1.8-v/1.5-v 1.8-v/1.5-v v ccpd ? 3.3-v/2.5-v 1.8-v/1.5-v not supported note to ta b l e 7 ? 6 : (1) the vccsel pin can also be connected to gnd for ps ( msel[3..0]=0010 ) and fpp ( msel[3..0]=0000 ) modes.
altera corporation 7?13 january 2008 stratix ii device handbook, volume 2 configuring stratix ii and stratix ii gx devices table 7?7 shows the configuration mode support for banks 4, 7, and 8. output configuration pins you must verify that the configurat ion output pins for your chosen configuration modes meet the v ih of the configuration device. refer to table 7?22 on page 7?94 for a consolidated list of configuration output pins. the v ih of 3.3 v or 2.5 v configuration devices will not be met when the v ccio of the output configuration pins are 1.8 v or 1.5 v. level shifters will be required to meet the input high level voltage threshold v ih . note that as mode is only applicable for 3.3-v configurations. if i/o bank 3 is less than 3.3 v, level shifte rs are required on the output pins ( dclk , ncso , asdo ) from the stratix ii or stratix ii gx device back to the epcs device. table 7?7. stratix ii conf iguration mode support for banks 4, 7 and 8 configuration mode configuration voltage/v ccio support for banks 4, 7, and 8 3.3/3.3 1.8/1.8 3.3/1.8 vccsel = gnd vccsel = vccpd vccsel = gnd fast passive parallel y y y passive parallel asynchronous y y y passive serial y y y remote system upgrade fpp y y y remote system upgrade ppa y y y remote system upgrade ps y y y fast as (40 mhz) y y y remote system upgrade fast as (40 mhz) y y y fpp with decompression and/or design security yyy remote system upgrade fpp with decompression and/or design security feature enabled yyy as (20 mhz) y y y remote system upgrade as (20 mhz) y y y
7?14 altera corporation stratix ii device handbook, volume 2 january 2008 fast passive parallel configuration the key is to ensure the vccio voltage of bank 3 is high enough to trip the vccio3 por trip point on power-up. also, to make sure the configuration device meets the v ih for the configuration input pins based on the selected input buffer. fast passive parallel configuration fast passive parallel (fpp) configuration in stratix ii and stratix ii gx devices is designed to meet the co ntinuously increasing demand for faster configuration times. stratix ii and stratix ii gx devices are designed with the capability of rece iving byte-wide configuration data per clock cycle. table 7?8 shows the msel pin settings when using the ffp configuration scheme. fpp configuration of stratix ii and st ratix ii gx devices can be performed using an intelligent host, such as a max ii device, a microprocessor, or an altera enhanced co nfiguration device. table 7?8. stratix ii and strati x ii gx msel pin settings for fpp configuration schemes notes (1) , (2) , and (3) configuration scheme m sel3 msel2 msel1 msel0 fpp when not using remote system upgrade or decompression and/or design security feature 0000 fpp when using remote system upgrade (4) 0100 fpp with decompression and/or design security feature enabled (5) 1011 fpp when using remote system upgrade and decompression and/or design security feature (4) , (5) 1100 notes to ta b l e 7 ? 8 : (1) you must verify the configuration output pins for your chosen configura iton modes meet the v ih of the configuration device. refer to table 7?22 for a consolidated list of configuration output pins. (2) the v ih of 3.3-v or 2.5-v configuration devices will not be met when the vccio of the output configuration pins is 1.8-v or 1.5-v. level shifters will be required to meet the input high level voltage threshold v ih . (3) the vccsel signal does not control tdo or nceo . during configuration, these pins drive out voltage levels corresponding to the vccio supply voltage that powers the i/o bank containing the pin. for more information about multi-volt support, incl uding information about using tdo and nceo in multi-volt systems, refer to the stratix ii gx architecture chapter in volume 1 of the stratix ii gx device handbook . (4) these schemes require that you drive the runlu pin to specify either remote update or local update. for more information about remote system upgrad e in stratix ii devices, refer to the remote system upgrades with stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii device handbook or the remote system upgrades with stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook . (5) these modes are only supported when using a max ii device or a microprocessor with flash memory for configuration. in these modes, the host system must output a dclk that is 4 the data rate.
altera corporation 7?15 january 2008 stratix ii device handbook, volume 2 configuring stratix ii and stratix ii gx devices fpp configuration using a max ii device as an external host fpp configuration using compression and an external host provides the fastest method to configure stratix ii and stratix ii gx devices. in the fpp configuration scheme, a max ii device can be used as an intelligent host that controls the transfer of configur ation data from a storage device, such as flash memory, to the target st ratix ii or stratix ii gx device. configuration data can be stored in rbf, hex, or ttf format. when using the max ii devices as an intellig ent host, a design that controls the configuration process, such as fetchi ng the data from flash memory and sending it to the device, must be stored in the max ii device. 1 if you are using the stratix ii or stratix ii gx decompression and/or design security feature, th e external host must be able to send a dclk frequency that is 4 the data rate. the 4 dclk signal does not require an addi tional pin and is sent on the dclk pin. the maximum dclk frequency is 100 mhz, which results in a maximum data rate of 200 mbps. if you are not using the stratix ii or stratix ii gx decompression or design se curity features, the data rate is 8 the dclk frequency. figure 7?3 shows the configuration interface connections between the stratix ii or stratix ii gx device and a max ii device for single device configuration. figure 7?3. single device fpp confi guration using an external host note to figure 7?3 : (1) the pull-up resistor sho uld be connected to a supply that provides an acceptable input signal for the device. v cc should be high enough to meet the v ih specification of the i/o on the device and the external host. external host (max ii device or microprocessor) conf_done nstatus nce data[7..0] nconfig stratix ii device memory addr data[7..0] gnd msel[3..0] v cc (1) v cc (1) gnd dclk nceo n.c. 10 k 10 k
7?16 altera corporation stratix ii device handbook, volume 2 january 2008 fast passive parallel configuration upon power-up, the stratix ii and stratix ii gx devices go through a power-on reset (por). the por delay is dependent on the porsel pin setting; when porsel is driven low, the por time is approximately 100 ms, if porsel is driven high, the por ti me is approximately 12 ms. during por, the device resets, holds nstatus low, and tri-states all user i/o pins. once the device successfully exits por, all user i/o pins continue to be tri-stated. if nio_pullup is driven low during power-up and configuration, the user i/o pins and dual-purpose i/o pins have weak pull-up resistors, which are on (after por) before and during configuration. if nio_pullup is driven high, the weak pull-up resistors are disabled. 1 you can hold nconfig low in order to stop device configuration. f the value of the weak pull-up resistors on the i/o pins that are on before and during configuration can be found in the dc & switching characteristics chapter in volume 1 of the stratix ii device handbook or the dc & switching characteristics chapter in volume 1 of the stratix ii gx device handbook . the configuration cycle consists of three stages: reset, configuration and initialization. while nconfig or nstatus are low, the device is in the reset stage. to initiate configuration, the max ii device must drive the nconfig pin from low-to-high. 1 v ccint , v ccio , and v ccpd of the banks where the configuration and jtag pins reside need to be fully powered to the appropriate voltage levels in order to begin the configuration process. when nconfig goes high, the device comes out of reset and releases the open-drain nstatus pin, which is then pulled high by an external 10-k ? pull-up resistor. once nstatus is released, the device is ready to receive configuration data and the configuration stage begins. when nstatus is pulled high, the max ii device places the configuration data one byte at a time on the data[7..0] pins. 1 stratix ii and stratix ii gx devices receive configuration data on the data[7..0] pins and the clock is received on the dclk pin. data is latched into the device on the rising edge of dclk . if you are using the stratix ii or stra tix ii gx decompression and/or design security feature, configuration data is latched on the rising edge of every fourth dclk cycle. after the configuration data is latched in, it is processed during the following three dclk cycles.
altera corporation 7?17 january 2008 stratix ii device handbook, volume 2 configuring stratix ii and stratix ii gx devices data is continuously clocked into the target device until conf_done goes high. the conf_done pin goes high one byte early in parallel configuration (fpp and ppa) modes. the last byte is required for serial configuration (as and ps) modes. after the device has received the next to last byte of the configuration data successfully, it releases the open-drain conf_done pin, which is pulled hi gh by an external 10-k ? pull-up resistor. a low- to-high transition on conf_done indicates configuration is complete and initialization of the device can begin. the conf_done pin must have an external 10-k ? pull-up resistor in order for the device to initialize. in stratix ii and stratix ii gx devices, the initialization clock source is either the internal oscillator (t ypically 10 mhz) or the optional clkusr pin. by default, the internal oscillator is the clock source for initialization. if the internal oscillator is used, the stratix ii or stratix ii gx device provides itself with enough clock cycles for proper initialization. therefore, if the internal oscillator is the initialization clock source, sending the entire configuration file to the device is sufficient to configure and initialize the device. driving dclk to the device after configuration is complete does not affect device operation. you can also synchronize initialization of multiple devices or to delay initialization with the clkusr option. the enable user-supplied start-up clock ( clkusr ) option can be turned on in the quartus ii software from the general tab of the device & pin options dialog box. supplying a clock on clkusr does not affect the configuration process. the conf_done pin goes high one byte early in parallel configuration (fpp and ppa) modes. the last byte is required for serial configuration (as and ps) modes. after the conf_done pin transitions high, clkusr is enabled after the time specified as t cd2cu . after this time peri od elapses, stratix ii and stratix ii gx devices require 299 cl ock cycles to initialize properly and enter user mode. stratix ii and stratix ii gx devices support a clkusr f max of 100 mhz. an optional init_done pin is available, which signals the end of initialization and the start of user-m ode with a low-to-high transition. this enable init_done output option is available in the quartus ii software from the general tab of the device & pin options dialog box. if the init_done pin is used, it is high because of an external 10-k ? pull-up resistor when nconfig is low and during the beginning of configuration. once the option bit to enable init_done is programmed into the device (during the first frame of configuration data), the init_done pin goes low. when initialization is complete, the init_done pin is released and pulled high. the max ii device must be able to detect this low-to-high tran sition, which signals the device has
7?18 altera corporation stratix ii device handbook, volume 2 january 2008 fast passive parallel configuration entered user mode. when initialization is complete, the device enters user mode. in user-mode, the user i/o pi ns no longer have weak pull-up resistors and function as assigned in your design. to ensure dclk and data[7..0] are not left floating at the end of configuration, the max ii device must drive them either high or low, whichever is convenient on your board. the data[7..0] pins are available as user i/o pins after conf iguration. when you select the fpp scheme in the quartus ii software, as a default, these i/o pins are tri-stated in user mode. to change this default option in the quartus ii software, select the pins tab of the device & pin options dialog box. the configuration clock ( dclk ) speed must be below the specified frequency to ensure correct configuration. no maximum dclk period exists, which means you can pause configuration by halting dclk for an indefinite amount of time. 1 if you are using the stratix ii or stratix ii gx decompression and/or design security feature and need to stop dclk , it can only be stopped three clock cycles after the last data byte was latched into the stratix ii or stratix ii gx device. by stopping dclk , the configuration circuit allows enough clock cycles to process the last byte of latched configuration data. when the clock restarts, the max ii device must provide data on the data[7..0] pins prior to sending the first dclk rising edge. if an error occurs during configuration, the device drives its nstatus pin low, resetting itself internally. the low signal on the nstatus pin also alerts the max ii device that there is an error. if the auto-restart configuration after error option (available in the quartus ii software from the general tab of the device & pin options (dialog box) is turned on, the device releases nstatus after a reset time-out period (maximum of 100 s). after nstatus is released and pull ed high by a pull-up resistor, the max ii device can try to reconfigure the target device without needing to pulse nconfig low. if this option is turned off, the max ii device must generate a low-to- high transition (with a low pulse of at least 2 s) on nconfig to restart the configuration process. the max ii device can also monitor the conf_done and init_done pins to ensure successful configuration. the conf_done pin must be monitored by the max ii device to detect errors and determine when programming completes. if all configuration data is sent, but the conf_done or init_done signals have not gone high, the max ii device will reconfigure the target device.
altera corporation 7?19 january 2008 stratix ii device handbook, volume 2 configuring stratix ii and stratix ii gx devices 1 if the optional clkusr pin is used and nconfig is pulled low to restart configuration during device initialization, you need to ensure clkusr continues toggling during the time nstatus is low (maximum of 100 s). when the device is in user-mode, initiating a reconfiguration is done by transitioning the nconfig pin low-to-high. the nconfig pin should be low for at least 2 s. when nconfig is pulled low, the device also pulls nstatus and conf_done low and all i/o pins are tri-stated. once nconfig returns to a logic high level and nstatus is released by the device, reconfiguration begins. figure 7?4 shows how to configure multiple devices using a max ii device. this circuit is similar to the fpp configuration circuit for a single device, except the stratix ii or st ratix ii gx devices are cascaded for multi-device configuration. figure 7?4. multi-device fpp confi guration using an external host note to figure 7?4 : (1) the pull-up resistor should be connected to a supply that provides an acceptable input signal for all devices in the chain. v cc should be high enough to meet the v ih specification of the i/o standard on the device and the external host. in multi-device fpp configuration, the first device?s nce pin is connected to gnd while its nceo pin is connected to nce of the next device in the chain. the last device?s nce input comes from the previous device, while its nceo pin is left floating. after the fi rst device completes configuration in a multi-device configuration chain, its nceo pin drives low to activate the second device?s nce pin, which prompts the second device to begin configuration. the second device in the chain begins co nfiguration within one clock cycle; therefore, the transfer of data destinations is transparent to the max ii device. all other configuration pins ( nconfig , nstatus , dclk , data[7..0] , and conf_done ) are connected to every device in conf_done nstatus nce data[7..0] nconfig stratix ii device 1 memory addr data[7..0] gnd v cc (1) v cc (1) dclk nceo conf_done nstatus nce data[7..0] nconfig stratix ii device 2 dclk nceo n.c. 10 k 10 k external host (max ii device or microprocessor) msel[3..0] gnd msel[3..0] gnd
7?20 altera corporation stratix ii device handbook, volume 2 january 2008 fast passive parallel configuration the chain. the configuration signal s may require buffering to ensure signal integrity and prevent clock skew problems. ensure that the dclk and data lines are buffered for every fourth device. because all device conf_done pins are tied together, all devices initialize and enter user mode at the same time. all nstatus and conf_done pins are tied together and if any device detects an error, configuration stops for the entire chain and the entire chain must be reconfigured. for example, if the first device flags an error on nstatus , it resets the chain by pulling its nstatus pin low. this behavior is similar to a single device detecting an error. if the auto-restart config uration after error option is turned on, the devices release their nstatus pins after a reset time-out period (maximum of 100 s). after all nstatus pins are released and pulled high, the max ii device can try to reconfigure the chain without pulsing nconfig low. if this option is turned off, the max ii device must generate a low-to-high transition (wit h a low pulse of at least 2 s) on nconfig to restart the configuration process. in a multi-device fpp configuration chain, all stratix ii or stratix ii gx devices in the chain must either enable or disable the decompression and/or design security feature. you can not selectively enable the decompression and/or design security feature for each device in the chain because of the data and dclk relationship. if the chain contains devices that do not support design security, you should use a serial configuration scheme. if a system has multiple devices that contain the same configuration data, tie all device nce inputs to gnd, and leave nceo pins floating. all other configuration pins ( nconfig , nstatus , dclk , data[7..0] , and conf_done ) are connected to every device in the chain. configuration signals may require buffering to ensure signal integrity and prevent clock skew problems. ensure that the dclk and data lines are buffered for every fourth device. devices must be the same density and package. all devices start and complete conf iguration at the same time. figure 7?5 shows multi-device fpp configuration when both stratix ii or stratix ii gx devices are receiving the same configuration data.
altera corporation 7?21 january 2008 stratix ii device handbook, volume 2 configuring stratix ii and stratix ii gx devices figure 7?5. multiple-device fpp configuration using an ex ternal host when both devices receive the same data notes to figure 7?5 : (1) the pull-up resistor should be connected to a supply that provides an acceptable input signal for all devices in the chain. v cc should be high enough to meet the v ih specification of the i/o on th e device and the external host. (2) the nceo pins of both stratix ii or stratix ii gx devices are left unconnected when configuring the same configuration data into multiple devices. you can use a single configuration chain to configure stratix ii or stratix ii gx devices with other altera devices that support fpp configuration, such as stratix devices. to ensure that all devices in the chain complete configuration at the same time or that an error flagged by one device initiates reconfiguration in all devices, tie all of the device conf_done and nstatus pins together. f for more information on configuring multiple altera devices in the same configuration chain, refer to configuring mixed altera fpga chains in volume 2 of the configuration handbook. fpp configuration timing figure 7?6 shows the timing waveform fo r fpp configuration when using a max ii device as an external ho st. this waveform shows the timing when the decompression and the design security feature are not enabled. conf_done nstatus nce data[7..0] nconfig stratix ii device memory addr data[7..0] gnd v cc (1) v cc (1) dclk nceo n.c. (2) conf_done nstatus nce data[7..0] nconfig stratix ii device gnd dclk nceo n.c. (2) 10 k 10 k external host (max ii device or microprocessor) msel[3..0] gnd msel[3..0] gnd
7?22 altera corporation stratix ii device handbook, volume 2 january 2008 fast passive parallel configuration figure 7?6. fpp configuration timing waveform notes (1) , (2) notes to figure 7?6 : (1) this timing waveform should be used when the de compression and design security feature are not used. (2) the beginning of this waveform shows the device in user-mode. in user-mode, nconfig , nstatus , and conf_done are at logic high levels. when nconfig is pulled low, a reconfiguration cycle begins. (3) upon power-up, the stratix ii or stratix ii gx device holds nstatus low for the time of the por delay. (4) upon power-up, before and during configuration, conf_done is low. (5) dclk should not be left floating after co nfiguration. it should be driven high or low, whichever is more convenient. (6) d ata[7..0] are available as user i/o pins after configuration and the state of these pins depends on the dual-purpose pin settings. table 7?9 defines the timing parameters for stratix ii and stratix ii gx devices for fpp configuration when the decompression and the design security features are not enabled. nconfig nstatus (3) conf_done (4) dclk data[7..0] user i/o init_done byte 0 byte 1 byte 2 byte 3 byte n t cd2um t cf2st1 t cf2cd t cfg t ch t cl t dh t dsu t cf2ck t status t clk t cf2st0 t st2ck hi g h-z user mode (5) (5) user mode table 7?9. fpp timing parameters for stratix ii and stratix ii gx devices (part 1 of 2) notes (1) , (2) symbol parameter min max units t cf2cd nconfig low to conf_done low 800 ns t cf2st0 nconfig low to nstatus low 800 ns t cfg nconfig low pulse width 2 s t status nstatus low pulse width 10 100 (3) s t cf2st1 nconfig high to nstatus high 100 (3) s t cf2ck nconfig high to first rising edge on dclk 100 s t st2ck nstatus high to first rising edge of dclk 2 s
altera corporation 7?23 january 2008 stratix ii device handbook, volume 2 configuring stratix ii and stratix ii gx devices t dsu data setup time before rising edge on dclk 5 ns t dh data hold time after rising edge on dclk 0 ns t ch dclk high time 4 ns t cl dclk low time 4 ns t clk dclk period 10 ns f max dclk frequency 100 mhz t r input rise time 40 ns t f input fall time 40 ns t cd2um conf_done high to user mode (4) 20 100 s t cd2cu conf_done high to clkusr enabled 4 ? maximum dclk period t cd2umc conf_done high to user mode with clkusr option on t cd2cu ? (299 ? clkusr period) notes to ta b l e 7 ? 9 : (1) this information is preliminary. (2) these timing parameters should be used when the decompression and de sign security feature are not used. (3) this value is obtainable if users do not delay configuration by extending the nconfig or nstatus low pulse width. (4) the minimum and maximum numbers apply on ly if the internal oscillator is chos en as the clock source for starting up the device. table 7?9. fpp timing parameters for stratix ii and stratix ii gx devices (part 2 of 2) notes (1) , (2) symbol parameter min max units
7?24 altera corporation stratix ii device handbook, volume 2 january 2008 fast passive parallel configuration figure 7?7 shows the timing waveform fo r fpp configuration when using a max ii device as an external ho st. this waveform shows the timing when the decompression and/or the design security feature are enabled. figure 7?7. fpp configuration timing waveform wi th decompression or design security feature enabled notes (1) , (2) notes to figure 7?7 : (1) this timing waveform should be used when the deco mpression and/or design security feature are used. (2) the beginning of this waveform shows the device in user-mode. in user-mode, nconfig , nstatus and conf_done are at logic high levels. when nconfig is pulled low, a reconfiguration cycle begins. (3) upon power-up, the stratix ii or stratix ii gx device holds nstatus low for the time of the por delay. (4) upon power-up, before and during configuration, conf_done is low. (5) dclk should not be left floating after co nfiguration. it should be driven high or low, whichever is more convenient. (6) data[7..0] are available as user i/o pins after configuration and the state of these pins depends on the dual-purpose pin settings. (7) if needed, dclk can be paused by holding it low. when dclk restarts, the external host must provide data on the data[7..0] pins prior to sending the first dclk rising edge. nconfig nstatus conf_done dclk data[7..0] user i/o init_done t cd2um t cf2st1 t cf2cd t cfg t cf2ck t t cf2st0 t st2ck hi g h-z user mode (3) (4) 12341234 1 byte 0 byte 1 byte 2 4 t dsu t dh status t dh t c h t c l t c lk byte n (6) (6) (5) (5) user mode
altera corporation 7?25 january 2008 stratix ii device handbook, volume 2 configuring stratix ii and stratix ii gx devices table 7?10 defines the timing parameters for stratix ii and stratix ii gx devices for fpp configuration when the decompression and/or the design security feature are enabled. f device configuration options and how to create configuration files are discussed further in the software settings chapter in the configuration handbook. table 7?10. fpp timing parameters for stratix ii and st ratix ii gx devices with decompression or design security feature enabled note (1) symbol parameter min max units t cf2cd nconfig low to conf_done low 800 ns t cf2st0 nconfig low to nstatus low 800 ns t cfg nconfig low pulse width 2 s t status nstatus low pulse width 10 100 (2) s t cf2st1 nconfig high to nstatus high 100 (2) s t cf2ck nconfig high to first rising edge on dclk 100 s t st2ck nstatus high to first rising edge of dclk 2 s t dsu data setup time before rising edge on dclk 5 ns t dh data hold time after rising edge on dclk 30 ns t ch dclk high time 4 ns t cl dclk low time 4 ns t clk dclk period 10 ns f max dclk frequency 100 mhz t data data rate 200 mbps t r input rise time 40 ns t f input fall time 40 ns t cd2um conf_done high to user mode (3) 20 100 s t cd2cu conf_done high to clkusr enabled 4 ? maximum dclk period t cd2umc conf_done high to user mode with clkusr option on t cd2cu + (299 ? clkusr period) notes to table 7?10 : (1) these timing parameters should be used when the decompression and design security feature are used. (2) this value is obtainable if users do not delay configuration by extending the nconfig or nstatus low pulse width. (3) the minimum and maximum numbers apply on ly if the internal oscillator is chos en as the clock source for starting up the device.
7?26 altera corporation stratix ii device handbook, volume 2 january 2008 fast passive parallel configuration fpp configuration using a microprocessor in the fpp configuration scheme, a microprocessor can control the transfer of configuration data from a storage device, such as flash memory, to the target stratix ii or stratix ii gx device. 1 all information in ?fpp configuration using a max ii device as an external host? on page 7?15 is also applicable when using a microprocessor as an external host. refer to that section for all configuration and timing information. fpp configuration using an enhanced configuration device in the fpp configuration scheme, an enhanced configurat ion device sends a byte of configuration data every dclk cycle to the stratix ii or stratix ii gx device. configuration data is stored in the configuration device. 1 when configuring your stratix ii or stratix ii gx device using fpp mode and an enhanced conf iguration device, the enhanced configuration device decompress ion feature is available while the stratix ii and stratix ii gx decompression and design security features are not. figure 7?8 shows the configuration interface connections between a stratix ii or stratix ii gx device and the enhanced configuration device for single device configuration. 1 the figures in this chapter only show the configuration-related pins and the configuration pin connections between the configuration device and the device. f for more information on the enhanc ed configuration device and flash interface pins, such as pgm[2..0] , exclk , porsel , a[20..0] , and dq[15..0] , refer to the enhanced configuration devices (epc4, epc8 & epc16) data sheet in volume 2 of the configuration handbook.
altera corporation 7?27 january 2008 stratix ii device handbook, volume 2 configuring stratix ii and stratix ii gx devices figure 7?8. single device fpp configur ation using an enhanced configuration device notes to figure 7?8 : (1) the pull-up resistor sh ould be connected to the same supply voltage as the configuration device. (2) the ninit_conf pin is available on enhanced configuration devices and has an internal pull-up resistor that is always active. this means an external pull-up resistor should not be used on the ninit_conf - nconfig line. the ninit_conf pin does not need to be connected if its functionality is not used. if ninit_conf is not used, nconfig must be pulled to v cc either directly or through a resistor. (3) the enhanced conf iguration devices? oe and ncs pins have internal programmable pull-up resistors. if intern al pull-up resistors are used, external pull-up resistors should not be used on th ese pins. the internal pull-up resistors are used by default in the quartus ii soft ware. to turn off the internal pull-up resistors, check the disable ncs and oe pull-ups on configuration device option when generating programming files. f the value of the internal pull-up resi stors on the enhanced configuration devices can be found in the enhanced configuration devices (epc4, epc8 & epc16) data sheet in volume 2 of the configuration handbook. when using enhanced configuratio n devices, you can connect the device?s nconfig pin to ninit_conf pin of the enhanced configuration device, which allows the init_conf jtag instruction to initiate device configuration. the ninit_conf pin does not need to be connected if its functionality is not used. if ninit_conf is not used, nconfig must be pulled to v cc either directly or through a resistor. an internal pull-up resistor on the ninit_conf pin is always active in the enhanced configuration devices, which means an external pull-up resistor should not be used if nconfig is tied to ninit_conf . upon power-up, the stratix ii or stratix ii gx device goes through a por. the por delay is dependent on the porsel pin setting; when porsel is driven low, the por time is approximately 100 ms, if porsel is driven high, the por time is approximately 12 ms. during por, the device will reset, hold nstatus low, and tri-state all user i/o pins. the stratix ii device enhanced confi g uration device dclk data[7..0] oe ncs ninit_conf (2) dclk data[7..0] nstatus conf_done nconfig v cc v cc gnd gnd (1) (1) nce (3) (3) nceo n.c. msel[3..0] 10 k 10 k (3) (3)
7?28 altera corporation stratix ii device handbook, volume 2 january 2008 fast passive parallel configuration configuration device also goes through a por delay to allow the power supply to stabilize. the por time for enhanced configuration devices can be set to either 100 ms or 2 ms, depending on its porsel pin setting. if the porsel pin is connected to gnd, the por delay is 100 ms. if the porsel pin is connected to v cc , the por delay is 2 ms. during this time, the configuration device drives its oe pin low. this low signal delays configuration because the oe pin is connected to the target device?s nstatus pin. 1 when selecting a por time, you need to ensure that the device completes power-up before the enhanced configuration device exits por. altera recommends that you use a 12-ms por time for the stratix ii or stratix ii g x device, and use a 100-ms por time for the enhanced configuration device. when both devices complete por, they release their open-drain oe or nstatus pin, which is then pulled high by a pull-up resistor. once the device successfully exits por, all user i/o pins continue to be tri-stated. if nio_pullup is driven low during power-up and configuration, the user i/o pins and dual-purpose i/o pins will have weak pull-up resistors, which are on (after por) before and during configuration. if nio_pullup is driven high, the weak pull-up resistors are disabled. f the value of the weak pull-up resistors on the i/o pins that are on before and during configuration can be found in the stratix ii device handbook or the stratix ii gx device handbook . when the power supplies have reached the appropriate operating voltages, the target device senses the low-to-high transition on nconfig and initiates the configuration cycle. the configuration cycle consists of three stages: reset, configuration and initialization. while nconfig or nstatus are low, the device is in reset. the beginning of configuration can be delayed by holding the nconfig or nstatus pin low. 1 v ccint , v ccio and v ccpd of the banks where the configuration and jtag pins reside need to be fully powered to the appropriate voltage levels in order to begin the configuration process. when nconfig goes high, the device comes out of reset and releases the nstatus pin, which is pulled high by a pull-up resistor. enhanced configuration devices have an optional internal pull-up resistor on the oe pin. this option is available in the quartus ii software from the general tab of the device & pin options dialog box. if this internal pull-up resistor is not used, an external 10-k ? pull-up resistor on the oe-nstatus line is required. once nstatus is released, the device is ready to receive configuration data and the configuration stage begins.
altera corporation 7?29 january 2008 stratix ii device handbook, volume 2 configuring stratix ii and stratix ii gx devices when nstatus is pulled high, the configuration device?s oe pin also goes high and the configuration device clocks data out to the device using the stratix ii or stratix ii gx device?s internal oscillator. the stratix ii and stratix ii gx devices receive configuration data on the data[7..0] pins and the clock is received on the dclk pin. a byte of data is latched into the device on each rising edge of dclk . after the device has received all configuration data successfully, it releases the open-drain conf_done pin which is pulled high by a pull-up resistor. because conf_done is tied to the configuration device?s ncs pin, the configuration device is disabled when conf_done goes high. enhanced configuration devices have an optional internal pull-up resistor on the ncs pin. this option is available in the quartus ii software from the general tab of the device & pin options dialog box. if this internal pull-up resistor is not used, an external 10-k ? pull-up resistor on the ncs - conf_done line is required. a low to high transition on conf_done indicates configuration is comp lete and initialization of the device can begin. in stratix ii and stratix ii gx devices, the initialization clock source is either the internal oscillator (t ypically 10 mhz) or the optional clkusr pin. by default, the internal oscillator is the clock source for initialization. if the internal oscillator is used, the stratix ii or stratix ii gx device provides itself with enough clock cycl es for proper initialization. you also have the flexibility to synchronize initialization of multiple devices or to delay initialization with the clkusr option. the enable user-supplied start-up clock ( clkusr ) option can be turned on in the quartus ii software from the general tab of the device & pin options dialog box. supplying a clock on clkusr will not affect the configuration process. after all configuration data has been accepted and conf_done goes high, clkusr will be enabled after the time specified as t cd2cu . after this time period elapses, stratix ii and strati x ii gx devices require 299 clock cycles to initialize properly and enter user mode. stratix ii and stratix ii gx devices support a clkusr f max of 100 mhz. an optional init_done pin is available, which signals the end of initialization and the start of user-m ode with a low-to-high transition. the enable init_done output option is available in the quartus ii software from the general tab of the device & pin options dialog box. if the init_done pin is used, it will be hi gh due to an external 10-k ? pull-up resistor when nconfig is low and during the beginning of configuration. once the option bit to enable init_done is programmed into the device (during the first frame of configuration data), the init_done pin will go low. when initialization is complete, the init_done pin will be released and pulled high. in user-mode, the user
7?30 altera corporation stratix ii device handbook, volume 2 january 2008 fast passive parallel configuration i/o pins will no longer have weak pu ll-up resistors and will function as assigned in your design. the enhanced configuration device will drive dclk low and data[7..0] high at the end of configuration. if an error occurs during configuration, the device drives its nstatus pin low, resetting itself internally. since the nstatus pin is tied to oe , the configuration device will also be reset. if the auto-restart configuration after error option (available in the quartus ii software from the general tab of the device & pin options dialog box) is turned on, the device will automatically initiate reconfiguration if an error occurs. the stratix ii or stratix ii gx device releases its nstatus pin after a reset time-out period (maximum of 100 s). when the nstatus pin is released and pulled high by a pull-up resistor, the configuration device reconfigures the chain. if this option is turned off, th e external system must monitor nstatus for errors and then pulse nconfig low for at least 2 s to restart configuration. the external system can pulse nconfig if nconfig is under system control rather than tied to v cc . in addition, if the configuration device sends all of its data and then detects that conf_done has not gone high, it re cognizes that the device has not configured successfully. enha nced configuration devices wait for 64 dclk cycles after the last configuration bit was sent for conf_done to reach a high state. in this case, the configuration device pulls its oe pin low, which in turn drives the target device?s nstatus pin low. if the auto-restart configuration after error option is set in the software, the target device resets and then releases its nstatus pin after a reset time-out period (maximum of 100 s). when nstatus returns to a logic high level, the configuration device will try to reconfigure the device. when conf_done is sensed low after configuration, the configuration device recognizes that the target device has not configured successfully. therefore, your system should not pull conf_done low to delay initialization. instead, you should use the clkusr option to synchronize the initialization of multiple devices that are not in the same configuration chain. devices in th e same configuration chain will initialize together if their conf_done pins are tied together. 1 if the optional clkusr pin is used and nconfig is pulled low to restart configuration during device initialization, ensure clkusr continues toggling during the time nstatus is low (maximum of 100 s). when the device is in user-mode, a reconfiguration can be initiated by pulling the nconfig pin low. the nconfig pin should be low for at least 2s. when nconfig is pulled low, the device also pulls nstatus and conf_done low and all i/o pins are tri-stated. because conf_done is
altera corporation 7?31 january 2008 stratix ii device handbook, volume 2 configuring stratix ii and stratix ii gx devices pulled low, this activates the configuration device because it sees its ncs pin drive low. once nconfig returns to a logic high level and nstatus is released by the device, reconfiguration begins. figure 7?9 shows how to configure multiple stratix ii or stratix ii gx devices with an enhanced configuration device. this circuit is similar to the configuration device circuit for a single device, except the stratix ii or stratix ii gx devices are cascaded for multi-device configuration. figure 7?9. multi-device fpp configuration using an enhanc ed configuration device notes to figure 7?9 : (1) the pull-up resistor should be connected to the same supply volt age as the configuration device. (2) the ninit_conf pin is available on enhanced configuration devi ces and has an internal pull-up resistor that is always active. this means an external p ull-up resistor should not be used on the ninit_conf - nconfig line. the ninit_conf pin does not need to be connected if its functionality is not used. if ninit_conf is not used, nconfig must be pulled to v cc either directly or through a resistor. (3) the enhanced conf iguration devices? oe and ncs pins have internal programmable pull-up resistors. if internal pull-up resistors are used, external pull-up resistors should not be used on these pins. th e internal pull-up resistors are used by default in the quartus ii software. to turn off the internal pull -up resistors, check the disable ncs and oe pull-up resistors on configuration device option when generating programming files. 1 enhanced configuration devices cannot be cascaded. when performing multi-device configuration, you must generate the configuration device?s pof from ea ch project?s sof. you can combine multiple sofs using the convert programming files window in the quartus ii software. f for more information on how to create configuration files for multi-device configuration chains, refer to software settings in volume 2 of the configuration handbook . ncs data[7..0] oe ninit_conf (2) gnd gnd gnd 10 k dclk v cc (1) (3) 10 k v cc (1) (3) enhanced confi g uration device conf_done data[7..0] nstatus nconfig dclk msel[3..0] nce nceo stratix ii device 1 conf_done data[7..0] nstatus nconfig dclk msel[3..0] nce n.c. nceo stratix ii device 2 (3) (3)
7?32 altera corporation stratix ii device handbook, volume 2 january 2008 fast passive parallel configuration in multi-device fpp configuration, the first device?s nce pin is connected to gnd while its nceo pin is connected to nce of the next device in the chain. the last device?s nce input comes from the previous device, while its nceo pin is left floating. after the fi rst device completes configuration in a multi-device configuration chain, its nceo pin drives low to activate the second device?s nce pin, which prompts the second device to begin configuration. all other configuration pins ( nconfig , nstatus , dclk , data[7..0] , and conf_done ) are connected to every device in the chain. pay special attention to the co nfiguration signals because they may require buffering to ensure signal integrity and prevent clock skew problems. ensure that the dclk and data lines are buffered for every fourth device. when configuring multiple devices, co nfiguration does not begin until all devices release their oe or nstatus pins. similarly, since all device conf_done pins are tied together, all devices initialize and enter user mode at the same time. since all nstatus and conf_done pins are tied together, if any device detects an error, configuration stops for the entire chain and the entire chain must be reconfigured. for example, if the first device flags an error on nstatus , it resets the chain by pulling its nstatus pin low. this low signal drives the oe pin low on the enhanced configuration device and drives nstatus low on all devices, which causes them to enter a reset state. this behavior is similar to a single device detecting an error. if the auto-restart config uration after error option is turned on, the devices will automatically initiate reconfiguration if an error occurs. the devices will release their nstatus pins after a reset time-out period (maximum of 100 s). when all the nstatus pins are released and pulled high, the configuration device trie s to reconfigure the chain. if the auto-restart configuration after error option is turned off, the external system must monitor nstatus for errors and then pulse nconfig low for at least 2 s to restart configurat ion. the external system can pulse nconfig if nconfig is under system control rather than tied to v cc . your system may have multiple devices that contain the same configuration data. to support this configuration scheme, all device nce inputs are tied to gnd, while nceo pins are left fl oating. all other configuration pins ( nconfig , nstatus , dclk , data[7..0] , and conf_done ) are connected to every device in the chain. configuration signals may require buffering to ensure signal integrity and prevent clock skew problems. ensure that the dclk and data lines are buffered for every fourth device. devices must be the same density and package. all devices will start and complete configuration at the same time. figure 7?10 shows multi-device fpp configur ation when both stratix ii or stratix ii gx devices are receiving the same configuration data.
altera corporation 7?33 january 2008 stratix ii device handbook, volume 2 configuring stratix ii and stratix ii gx devices figure 7?10. multiple-device fpp configuration us ing an enhanced configuration device when both devices receive the same data notes to figure 7?10 : (1) the pull-up resistor should be connected to the same supply volt age as the configuration device. (2) the ninit_conf pin is available on enhanced configuration devi ces and has an internal pull-up resistor that is always active. this means an external p ull-up resistor should not be used on the ninit_conf - nconfig line. the ninit_conf pin does not need to be connected if its functionality is not used. if ninit_conf is not used, nconfig must be pulled to v cc either directly or through a resistor. (3) the enhanced conf iguration devices? oe and ncs pins have internal programmable pull-up resistors. if internal pull-up resistors are used, external pull-up resistors should not be used on these pins. th e internal pull-up resistors are used by default in the quartus ii software. to turn off the internal pull -up resistors, check the disable ncs and oe pull-ups on configuration device option when generating programming files. (4) the nceo pins of both devices are left unconnected when conf iguring the same configuration data into multiple devices. you can use a single enhanced config uration chain to configure multiple stratix ii or stratix ii gx devices with other altera devices that support fpp configuration, such as stratix and stratix gx devices. to ensure that all devices in the chain complete config uration at the same time or that an error flagged by one device initiates re configuration in all devices, all of the device conf_done and nstatus pins must be tied together. f for more information on configuring multiple altera devices in the same configuration chain, refer to configuring mixed al tera fpga chains in the configuration handbook . ncs data[7..0] oe ninit_conf (2) gnd gnd gnd 10 k dclk v cc (1) (3) 10 k v cc (1) (3) enhanced confi g uration device conf_done data[7..0] nstatus nconfig dclk nce nceo stratix ii device conf_done data[7..0] nstatus nconfig dclk msel[3..0] nce n.c. nceo stratix ii device (4) gnd n.c. (4) (3) (3) msel[3..0]
7?34 altera corporation stratix ii device handbook, volume 2 january 2008 active serial configuration (serial configuration devices) figure 7?11 shows the timing waveform for the fpp configuration scheme using an enhanced configuration device. figure 7?11. stratix ii and stratix ii gx fpp configuration using an enhanced configuration device timing waveform note to figure 7?11 : (1) the initialization clock can come from the stratix ii or stratix ii g x device?s internal oscillator or the clkusr pin. f for timing information, refer to the enhanced configuration devices (epc4, epc8 & epc16) data sheet in volume 2 of the configuration handbook . f device configuration options and how to create configuration files are discussed further in the software settings section in volume 2 of the configuration handbook . active serial configuration (serial configuration devices) in the as configuration scheme, stratix ii and stratix ii gx devices are configured using a serial configur ation device. these configuration devices are low-cost devices with no n-volatile memory that feature a simple four-pin interface and a smal l form factor. these features make serial configuration devices an ideal low-cost configuration solution. note that as mode is only applicable for 3.3-v configurations. if i/o bank 3 is less than 3.3 v, level shifte rs are required on the output pins ( dclk , ncso , asdo ) from the stratix ii or stratix ii gx device back to the epcs device. 1 if vccio in bank 3 is set to 1.8 v , an external voltage level translator is needed to meet the v ih of the epcs device (3.3 v). tri-state user mode t loe t lc t hc t ce t oe byte byte 2 n byte 1 driven hi g h tri-state oe/nstatus ncs/conf_done dclk data[7..0] user i/o init_done ninit_conf or vcc/nconfig t cd2um (1)
altera corporation 7?35 january 2008 stratix ii device handbook, volume 2 configuring stratix ii and stratix ii gx devices f for more information on serial configuration devices, refer to the serial configuration devices (epcs1, epcs16, epcs64, and epcs128) data sheet in volume 2 of the configuration handbook . serial configuration devices provide a serial interface to access configuration data. during device configuration, stratix ii and stratix ii gx devices read configuratio n data via the serial interface, decompress data if necessary, and configure their sram cells. this scheme is referred to as the as conf iguration scheme because the device controls the configuratio n interface. this scheme contrasts with the ps configuration scheme, where the configuration device controls the interface. 1 the stratix ii and stratix ii gx decompression and design security features are fully av ailable when configuring your stratix ii or stratix ii gx device using as mode. table 7?11 shows the msel pin settings when using the as configuration scheme. serial configuration devices have a four-pin interface: serial clock input ( dclk ), serial data output ( data ), as data input ( asdi ), and an active-low chip select ( ncs ). this four-pin interface connects to stratix ii and stratix ii gx device pins, as shown in figure 7?12 . table 7?11. stratix ii and stratix ii g x msel pin settings for as configuration schemes note (2) configuration scheme m sel3 msel2 msel1 msel0 fast as (40 mhz) (1) 1000 remote system upgrade fast as (40 mhz) (1) 1001 as (20 mhz) (1) 1101 remote system upgrade as (20 mhz) (1) 1110 notes to ta b l e 7 ? 11 : (1) only the epcs16 and epcs64 devices support a dclk up to 40 mhz clock; other epcs devices support a dclk up to 20 mhz. refer to the serial configuration devices (epcs1, epcs4, epcs16, epcs64, and epcs128) data sheet in volume 2 of the configuration handbook for more information. (2) note that as mode is only applicable fo r 3.3-v configuration. if i/o bank 3 is less than 3.3-v, level shifters are required on the output pins (dclk,ncso, and asdo) from the stratix ii or stratix ii gx device back to the epcs device.
7?36 altera corporation stratix ii device handbook, volume 2 january 2008 active serial configuration (serial configuration devices) figure 7?12. single device as configuration notes to figure 7?12 : (1) connect the pull-up re sistors to a 3.3-v supply. (2) stratix ii and stratix ii gx devices use the asdo to asdi path to control the configuration device. (3) if using an epcs4 device, msel[3..0] should be set to 1101. refer to table 7?11 for more details. upon power-up, the stratix ii and stratix ii gx devices go through a por. the por delay is dependent on the porsel pin setting. when porsel is driven low, the por time is approximately 100 ms. if porsel is driven high, the por time is approximately 12 ms. during por, the device will reset, hold nstatus and conf_done low, and tri-state all user i/o pins. once the device successfully exits por, all user i/o pins continue to be tri-stated. if nio_pullup is driven low during power-up and configuration, the user i/o pins and dual-purpose i/o pins will have weak pull-up resistors which are on (after por) before and during configuration. if nio_pullup is driven high, the weak pull-up resistors are disabled. f the value of the weak pull-up resistors on the i/o pins that are on before and during configuration can be found in the dc & switching characteristics chapter in volume 1 of the stratix ii device handbook and the dc & switching characteristics chapter in volume 1 of the stratix ii gx device handbook . the configuration cycle consists of three stages: reset, configuration and initialization. while nconfig or nstatus are low, the device is in reset. after por, the stratix ii and stratix ii gx devices release nstatus , which is pulled high by an external 10-k ? pull-up resistor, and enters configuration mode. data dclk ncs asdi data0 dclk ncso asdo serial confi g uration device stratix ii or stratix ii gx fpga 10 k 10 k v cc 10 k v cc v cc gnd nceo nce nstatus nconfig conf_done (2) msel1 msel0 gnd n.c. (1) (1) (1) msel3 msel2 v cc (3) (3) (3) (3)
altera corporation 7?37 january 2008 stratix ii device handbook, volume 2 configuring stratix ii and stratix ii gx devices 1 to begin configuration, power the v ccint , v ccio , and v ccpd voltages (for the banks where th e configuration and jtag pins reside) to the appropriate voltage levels. the serial clock ( dclk ) generated by the stratix ii and stratix ii gx devices controls the entire configuration cycle and provides the timing for the serial interface. stratix ii and stratix ii gx devices use an internal oscillator to generate dclk . using the msel[] pins, you can select to use either a 40- or 20-mhz oscillator. 1 only the epcs16 and ep cs64 devices support a dclk up to 40-mhz clock; other epcs devices support a dclk up to 20-mhz. refer to the serial configuration devices data sheet for more information. the epcs4 device only supports the smallest stratix ii (ep2s15) device, which is when the sof compression is enabled. because of its insu fficient memory capacity, the epcs1 device does not support any stratix ii devices. table 7?12 shows the active serial dclk output frequencies. in both as and fast as configuration schemes, the serial configuration device latches input and control signals on the rising edge of dclk and drives out configuration data on the falling edge. stratix ii and stratix ii gx devices drive out control signals on the falling edge of dclk and latch configuration data on the falling edge of dclk . in configuration mode, stratix ii and stratix ii gx devices enable the serial configuration device by driving the ncso output pin low, which connects to the chip select ( ncs ) pin of the configuration device. the stratix ii and stratix ii gx devices use the serial clock ( dclk ) and serial data output ( asdo ) pins to send operation commands and/or read address signals to the serial conf iguration device. the configuration device provides data on its serial data output ( data ) pin, which connects to the data0 input of the stratix ii and stratix ii gx devices. table 7?12. active serial dclk output frequency oscillator minimum typical maximum units 40 mhz (1) 20 26 40 mhz 20 mhz 10 13 20 mhz note to table 7?12 : (1) only the epcs16 and epcs64 devices support a dclk up to 40-mhz clock; other epcs devices support a dclk up to 20-mhz. refer to the serial configuration devices (epcs1, epcs4, epcs16, epcs16, and epcs128) data sheet chapter in volume 2 of the configuration handbook for more information.
7?38 altera corporation stratix ii device handbook, volume 2 january 2008 active serial configuration (serial configuration devices) after all configuration bits are receiv ed by the stratix ii or stratix ii gx device, it releases the open-drain conf_done pin, which is pulled high by an external 10-k ? resistor. initialization begins only after the conf_done signal reaches a logic high level. all as configuration pins, data0 , dclk , ncso , and asdo , have weak internal pull-up resistors that are always active. after configurat ion, these pins are set as input tri-stated and are driven high by the weak internal pull-up resistors. the conf_done pin must have an external 10-k ? pull-up resistor in order for the device to initialize. in stratix ii and stratix ii gx devices, the initialization clock source is either the 10-mhz (typical ) internal oscill ator (separate from the active serial internal oscillator) or the optional clkusr pin. by default, the internal oscillator is th e clock source for initialization. if the internal oscillator is us ed, the stratix ii or stratix ii gx device provides itself with enough clock cycles for proper initiali zation. you also have the flexibility to synchronize initialization of multiple devices or to delay initialization with the clkusr option. the enable user-supplied start-up clock ( clkusr ) option can be turned on in the quartus ii software from the general tab of the device & pin options dialog box. when you enable the user supplied start-up clock option, the clkusr pin is the initialization clock source. supplying a clock on clkusr will not affect the configuration process. after all co nfiguration data has been accepted and conf_done goes high, clkusr is enabled after 600 ns. after this time period elapses, stratix ii and stratix ii gx devices require 299 clock cycles to initialize properly and enter user mode. stratix ii and stratix ii gx devices support a clkusr f max of 100 mhz. an optional init_done pin is available, which signals the end of initialization and the start of user-m ode with a low-to-high transition. the enable init_done output option is available in the quartus ii software from the general tab of the device & pin options dialog box. if the init_done pin is used, it will be hi gh due to an external 10-k ? pull-up resistor when nconfig is low and during the beginning of configuration. once the option bit to enable init_done is programmed into the device (during the first frame of configuration data), the init_done pin goes low. when initialization is complete, the init_done pin is released and pulled hi gh. this low-to-hi gh transition signals that the device has entered user mode. when initialization is complete, the device enters user mode. in user mode, the user i/o pins no longer have weak pull-up resistor s and function as assigned in your design. if an error occurs during configurat ion, stratix ii and stratix ii gx devices assert the nstatus signal low, indicating a data frame error, and the conf_done signal stays low. if the auto-restart configuration after error option (available in the quartus ii software from the general tab of the
altera corporation 7?39 january 2008 stratix ii device handbook, volume 2 configuring stratix ii and stratix ii gx devices device & pin options dialog box) is turned on, the stratix ii or stratix ii gx device resets the configuration device by pulsing ncso , releases nstatus after a reset time-out period (maximum of 100 s), and retries configuration. if this option is turned off, the sy stem must monitor nstatus for errors and then pulse nconfig low for at least 2 s to restart configuration. when the stratix ii or stratix ii gx device is in user mode, you can initiate reconfiguration by pulling the nconfig pin low. the nconfig pin should be low for at least 2 s. when nconfig is pulled low, the device also pulls nstatus and conf_done low and all i/o pins are tri-stated. once nconfig returns to a logic high level and nstatus is released by the stratix ii or stratix ii gx device, reconfiguration begins. you can configure multiple stratix i i or stratix ii gx devices using a single serial configuration device. you can cascade multiple stratix ii or stratix ii gx devices using the chip-enable ( nce ) and chip-enable-out ( nceo ) pins. the first device in the chain must have its nce pin connected to ground. you must connect its nceo pin to the nce pin of the next device in the chain. when the first de vice captures all of its configuration data from the bit stream, it drives the nceo pin low, enabling the next device in the chain. you must leave the nceo pin of the last device unconnected. the nconfig , nstatus , conf_done , dclk , and data0 pins of each device in the chain are connected (refer to figure 7?13 ). this first stratix ii or st ratix ii gx device in the chain is the configuration master and controls configuration of the entire chain. you must connect its msel pins to select the as config uration scheme. the remaining stratix ii or stratix ii gx devices are configuration slaves and you must connect their msel pins to select the ps configuration scheme. any other altera device that supports ps configuration can also be part of the chain as a configuration slave. figure 7?13 shows the pin connections for this setup.
7?40 altera corporation stratix ii device handbook, volume 2 january 2008 active serial configuration (serial configuration devices) figure 7?13. multi-device as configuration notes to figure 7?13 : (1) connect the pull-up resistors to a 3.3-v supply. (2) if using an epcs4 device, msel[3..0] should be set to 1101. refer to tab le 7?11 for more details. as shown in figure 7?13 , the nstatus and conf_done pins on all target devices are connected together with ex ternal pull-up resi stors. these pins are open-drain bidirectional pins on the devices. when the first device asserts nceo (after receiving all of its configuration data), it releases its conf_done pin. but the subsequent devices in the chain keep this shared conf_done line low until they have rece ived their configuration data. when all target devices in the chain have received their configuration data and have released conf_done , the pull-up resistor drives a high level on this line and all devices simultaneously enter initialization mode. if an error occurs at any po int during configuration, the nstatus line is driven low by the failing device. if you enable the auto-restart configuration after error option, reconf iguration of the entire chain begins after a reset time-out period (a maximum of 100 s). if the auto-restart configuration after error option is turned off, the external system must monitor nstatus for errors and then pulse nconfig low to restart configuration. the external system can pulse nconfig if it is under system control rather than tied to v cc . 1 while you can cascade stratix ii or stratix ii gx devices, serial configuration devices cannot be cascaded or chained together. data dclk ncs asdi data0 dclk ncso asdo serial confi g uration device stratix ii or stratix ii gx fpga master stratix ii or stratix ii gx fpga slave 10 k 10 k v cc v cc gnd nceo nce nstatus conf_done data0 dclk nceo nce nstatus conf_done 10 k v cc nconfig nconfig n.c. (1) (1) (1) msel1 msel0 gnd msel3 msel2 v cc (2) (2) (2) (2) msel1 msel0 gnd msel3 msel2 v c c
altera corporation 7?41 january 2008 stratix ii device handbook, volume 2 configuring stratix ii and stratix ii gx devices if the configuration bit stream size exceeds the capacity of a serial configuration device, you must select a larger configuration device and/or enable the compression feature. when configuring multiple devices, the size of the bitstream is the sum of the individual devices? configuration bitstreams. a system may have multiple devices that contain the sa me configuration data. in active serial chains, this can be implemented by storing two copies of the sof in the serial conf iguration device. the first copy would configure the master stratix ii or stratix ii gx device, and the second copy would configure all remaining sl ave devices concurrently. all slave devices must be the same density and package. the setup is similar to figure 7?13 , where the master is set up in active serial mode and the slave devices are set up in passive serial mode. to configure four identical stratix i i or stratix ii gx devices with the same sof, you could set up the ch ain similar to the example shown in figure 7?14 . the first device is the master device and its msel pins should be set to select as configuration. the other three slave devices are set up for concurrent configuration and its msel pins should be set to select ps configuration. the nceo pin from the master device drives the nce input pins on all three slave devices, and the data and dclk pins connect in parallel to all four devices. during the first configuration cycle, the master device reads its configuration data from the serial configuration device while holding nceo high. after completing it s configuration cycle, the master drives nce low and transmits the second copy of the configuration data to all three slave devices, configuring them simultaneously.
7?42 altera corporation stratix ii device handbook, volume 2 january 2008 active serial configuration (serial configuration devices) figure 7?14. multi-device as configurati on when devices receive the same data notes to figure 7?14 : (1) connect the pull-up resistors to a 3.3-v supply. (2) if using an epcs4 device, msel[3..0] should be set to 1101. refer to table 7?11 for more details. data dclk ncs asdi data0 dclk ncso asdo serial confi g uration device stratix ii fpga master 10 k 10 k v cc v cc gnd nceo nce nstatus conf_done data0 dclk stratix ii fpga slave nceo nce nstatus conf_done 10 k v cc nconfig nconfig n.c. (1) (1) (1) msel1 msel0 gnd msel3 msel2 v cc msel1 msel0 gnd msel3 msel2 v cc data0 dclk stratix ii fpga slave nceo nce nstatus conf_done nconfig n.c. msel1 msel0 gnd msel3 msel2 v cc data0 dclk stratix ii fpga slave nceo nce nstatus conf_done nconfig n.c. msel1 msel0 gnd msel3 msel2 v cc (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2)
altera corporation 7?43 january 2008 stratix ii device handbook, volume 2 configuring stratix ii and stratix ii gx devices estimating active serial configuration time active serial configuration time is dominated by the time it takes to transfer data from the serial config uration device to the stratix ii device. this serial interface is clocked by the stratix ii dclk output (generated from an internal oscill ator). as listed in table 7?12 on page 7?37 , the dclk minimum frequency when choosing to use the 40-mhz oscillator is 20 mhz (50 ns). therefore, the maxim um configuration time estimate for an ep2s15 device (5 mbits of uncompressed data) is: rbf size (minimum dclk period / 1 bit per dclk cycle) = estimated maximum configuration time 5 mbits (50 ns / 1 bit) = 250 ms to estimate the typical configuration time, use the typical dclk period as listed in table 7?12 . with a typical dclk period of 38.46 ns, the typical configuration time is 192 ms. enabling compression reduces the amount of configuration data that is transm itted to the stratix ii or stratix ii gx device, which also reduces configuration time. on average, compression reduces configuration time by 50 % . programming serial configuration devices serial configuration devices are non-volatile, flash-memory-based devices. you can program these devices in-system using the usb-blaster ? or byteblaster ? ii download cable. alternatively, you can program them using the altera programming unit (apu), supported third-party programmers, or a micropro cessor with the srunner software driver. you can perform in-system programmin g of serial configuration devices via the as programming interface. during in-system programming, the download cable disables device access to the as interface by driving the nce pin high. stratix ii and stratix ii gx devices are also held in reset by a low level on nconfig . after programming is complete, the download cable releases nce and nconfig , allowing the pull-down and pull-up resistors to drive gnd and v cc , respectively. figure 7?15 shows the download cable connections to the serial configuration device. f for more information on the usb blaster download cable, refer to the usb-blaster download cable user guide . for more information on the byteblaster ii cable, refer to the byteblaster ii downlo ad cable user guide .
7?44 altera corporation stratix ii device handbook, volume 2 january 2008 active serial configuration (serial configuration devices) figure 7?15. in-system programming of serial configuration devices notes to figure 7?15 : (1) connect these pull-up resistors to 3.3-v supply. (2) power up the byteblaster ii cable's v cc with a 3.3-v supply. (3) if using an epcs4 device, msel[3..0] should be set to 1101 . refer to table 7?11 for more details. you can program serial configuration devices with the quartus ii software with the altera programming hardware (apu) and the appropriate configuration device pr ogramming adapter. the epcs1 and epcs4 devices are offered in an eight- pin small outline in tegrated circuit (soic) package. in production environments, seri al configuration devices can be programmed using multiple methods. altera programming hardware or other third-party programming hardware can be used to program blank serial configuration devices before th ey are mounted onto printed circuit boards (pcbs). alternatively, you ca n use an on-board microprocessor to program the serial configuration device in-system using c-based software drivers provided by altera. data dclk ncs asdi data0 dclk ncso nce nconfig nstatus nceo conf_done asdo v cc v cc v cc v cc 10 k 10 k 10 k 10 k stratix ii fpga serial confi g uration device pin 1 u sb bl aster o r by te bl aser ii 1 0 -pin m a l e h eader n.c. (1) (1) (1) (2) msel1 msel0 gnd msel3 msel2 v cc (3) (3) (3) (3)
altera corporation 7?45 january 2008 stratix ii device handbook, volume 2 configuring stratix ii and stratix ii gx devices a serial configuration device can be programmed in-system by an external microprocessor using srunner. srunner is a software driver developed for embedded serial configuration device programming, which can be easily customized to fi t in different embedded systems. srunner is able to read a raw programming data (. rpd ) file and write to the serial configuration devices. the serial configuration device programming time using srunner is comparable to the programming time with the quartus ii software. f for more information about srunner, refer to an 418: srunner: an embedded solution for serial configuration device programming and the source code on the altera web site at www.altera.com . f for more information on programmin g serial configuration devices, refer to the serial configuration devices (e pcs1, epcs4, epcs16, epcs64, and epcs128) data sheet in the configuration handbook . figure 7?16 shows the timing waveform for the as configuration scheme using a serial configuration device. figure 7?16. as configuration timing note to figure 7?16 : (1) the initialization clock can come from the stratix ii or stratix ii g x device?s internal oscillator or the clkusr pin. read address bit n ? 1 bit n bit 1 bit 0 nstatus nconfig conf_done ncso dclk asdo data0 init_done user i/o user mode t c f2st1 t d h t d s u t c h t c l t cd2um (1)
7?46 altera corporation stratix ii device handbook, volume 2 january 2008 passive serial configuration table 7?13 shows the as timing parameters for stratix ii devices. passive serial configuration ps configuration of stratix ii and st ratix ii gx devices can be performed using an intelligent host, such as a max ii device or microprocessor with flash memory, an altera configuration device, or a download cable. in the ps scheme, an external host (max ii device, embedded processor, configuration device, or host pc) co ntrols configuration. configuration data is clocked into the target stra tix ii or stratix ii gx device via the data0 pin at each rising edge of dclk . 1 the stratix ii and stratix ii gx decompression and design security features are fully av ailable when configuring your stratix ii or stratix ii gx device using ps mode. table 7?14 shows the msel pin settings when using the ps configuration scheme. table 7?13. as timing parameters for stratix ii devices symbol parameter condition minimum typical maximum t cf2st1 nconfig high to nstatus high 100 t dsu data setup time before falling edge on dclk 7 t dh data hold time after falling edge on dclk 0 t ch dclk high time 10 t cl dclk low time 10 t cd2um conf_done high to user mode 20 100 table 7?14. stratix ii and stratix ii g x msel pin settings for ps configuration schemes configuration scheme m sel3 msel2 msel1 msel0 ps 0010 ps when using remote system upgrade (1) 0110 note to table 7?14 : (1) this scheme requires that you drive the runlu pin to specify either remote update or local update. for more inform ation about remote system upgrade in stratix ii devices, refer to the remote system upgrades with stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii device handbook or the remote system upgrades with stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx de vice handbook .
altera corporation 7?47 january 2008 stratix ii device handbook, volume 2 configuring stratix ii and stratix ii gx devices ps configuration using a max ii device as an external host in the ps configuration scheme, a max ii device can be used as an intelligent host that controls the tr ansfer of configuration data from a storage device, such as flash me mory, to the target stratix ii or stratix ii gx device. configuration data can be stored in rbf, hex, or ttf format. figure 7?17 shows the configuration interface connections between a stratix ii or stratix ii gx device and a max ii device for single device configuration. figure 7?17. single device ps confi guration using an external host note to figure 7?17 : (1) connect the pull-up resistor to a supply that provides an acceptable input signal for the device. v cc should be high enough to meet the v ih specification of the i/o on the device and the external host. upon power-up, stratix ii and stratix ii gx devices go through a por. the por delay is dependent on the porsel pin setting; when porsel is driven low, the por time is approximately 100 ms, if porsel is driven high, the por time is approximately 12 ms. during por, the device resets, holds nstatus low, and tri-states all user i/o pins. once the device successfully exits por, all user i/o pins continue to be tri-stated. if nio_pullup is driven low during power-up and configuration, the user i/o pins and dual-purpose i/o pins will have weak pull-up resistors which are on (after por) before and during configuration. if nio_pullup is driven high, the weak pull-up resistors are disabled. 1 you can hold nconfig low in order to stop device configuration. external host (max ii device or microprocessor) conf_done nstatus nce data0 nconfig stratix ii device memory addr data0 gnd vcc vcc 10 k 10 k dclk nceo n.c. (1) (1) msel1 msel0 gnd msel3 msel2 v cc
7?48 altera corporation stratix ii device handbook, volume 2 january 2008 passive serial configuration f the value of the weak pull-up resistors on the i/o pins that are on before and during configuration can be found in the stratix ii device handbook or the stratix ii gx device handbook . the configuration cycle consists of three stages: reset, configuration, and initialization. while nconfig or nstatus are low, the device is in reset. to initiate configuration, the max ii device must generate a low-to-high transition on the nconfig pin. 1 v ccint , v ccio , and v ccpd of the banks where the configuration and jtag pins reside need to be fully powered to the appropriate voltage levels in order to begin the configuration process. when nconfig goes high, the device comes out of reset and releases the open-drain nstatus pin, which is then pulled high by an external 10-k ? pull-up resistor. once nstatus is released, the device is ready to receive configuration data and the configuration stage begins. when nstatus is pulled high, the max ii device shou ld place the configuration data one bit at a time on the data0 pin. if you are using configuration data in rbf, hex, or ttf format, you must send th e least significant bit (lsb) of each data byte first. for example, if the rbf contains the byte sequence 02 1b ee 01 fa , the serial bitstream you shou ld transmit to the device is 0100-0000 1101-1000 0111-0111 1000-0000 0101-1111 . the stratix ii and stratix ii gx devices receive configuration data on the data0 pin and the clock is received on the dclk pin. data is latched into the device on the rising edge of dclk . data is continuously clocked into the target device until conf_done goes high. after the device has received all configuration data successfully, it releases the open-drain conf_done pin, which is pulled hi gh by an external 10-k ? pull-up resistor. a low-to-h igh transition on conf_done indicates configuration is complete and initialization of the device can begin. the conf_done pin must have an external 10-k ? pull-up resistor in order for the device to initialize. in stratix ii and stratix ii gx devices, the initialization clock source is either the internal oscillator (t ypically 10 mhz) or the optional clkusr pin. by default, the internal oscillator is the clock source for initialization. if the internal oscillator is used, the stratix ii or stratix ii gx device provides itself with enough clock cycles for proper initialization. therefore, if the internal oscillator is the initialization clock source, sending the entire configuration file to the device is sufficient to configure and initialize the device. driving dclk to the device after configuration is complete does not affect device operation.
altera corporation 7?49 january 2008 stratix ii device handbook, volume 2 configuring stratix ii and stratix ii gx devices you also have the flexibility to synchronize initialization of multiple devices or to delay initialization with the clkusr option. the enable user-supplied start-up clock ( clkusr ) option can be turned on in the quartus ii software from the general tab of the device & pin options dialog box. supplying a clock on clkusr will not affect the configuration process. after all configuration data has been accepted and conf_done goes high, clkusr will be enabled after the time specified as t cd2cu . after this time period elapses, stratix i i and stratix ii gx devices require 299 clock cycles to initialize properly and enter user mode. stratix ii and stratix ii gx devices support a clkusr f max of 100 mhz. an optional init_done pin is available, which signals the end of initialization and the start of user-m ode with a low-to-high transition. the enable init_done output option is available in the quartus ii software from the general tab of the device & pin options dialog box. if the init_done pin is used it will be high due to an external 10-k ? pull-up resistor when nconfig is low and during the beginning of configuration. once the option bit to enable init_done is programmed into the device (during the first frame of configuration data), the init_done pin will go low. when initialization is complete, the init_done pin will be released and pulled high. the max ii device must be able to detect this low-to-high transition which signals the device has entered user mode. when initialization is complete, the device enters user mode. in user-mode, the user i/o pins will no longer have weak pull-up resistors and will function as assigned in your design. to ensure dclk and data0 are not left floating at the end of configuration, the max ii device must drive them either high or low, whichever is convenient on your board. the data[0] pin is available as a user i/o pin after configuration. wh en the ps scheme is chosen in the quartus ii software, as a default this i/o pin is tri-stated in user mode and should be driven by the max ii de vice. to change th is default option in the quartus ii software, select the dual-purpose pins tab of the device & pin options dialog box. the configuration clock ( dclk ) speed must be below the specified frequency to ensure correct configuration. no maximum dclk period exists, which means you can pause configuration by halting dclk for an indefinite amount of time. if an error occurs during configuration, the device drives its nstatus pin low, resetting itself internally. the low signal on the nstatus pin also alerts the max ii device that there is an error. if the auto-restart configuration after error option (available in the quartus ii software from the general tab of the device & pin options dialog box) is turned on, the stratix ii or stratix ii gx device releases nstatus after a reset time-out period (maxi mum of 100 s). after nstatus is released and
7?50 altera corporation stratix ii device handbook, volume 2 january 2008 passive serial configuration pulled high by a pull-up resistor, th e max ii device can try to reconfigure the target device without needing to pulse nconfig low. if this option is turned off, the max ii device must generate a low-to-high transition (with a low pulse of at least 2 s) on nconfig to restart the configuration process. the max ii device can also monitor the conf_done and init_done pins to ensure successful configuration. the conf_done pin must be monitored by the max ii device to detect errors and determine when programming completes. if all configuration data is sent, but conf_done or init_done have not gone high, the ma x ii device must reconfigure the target device. 1 if the optional clkusr pin is being used and nconfig is pulled low to restart configuration duri ng device initialization, you need to ensure that clkusr continues toggling during the time nstatus is low (maximum of 100 s). when the device is in user-mode, you can initiate a reconfiguration by transitioning the nconfig pin low-to-high. the nconfig pin must be low for at least 2 s. when nconfig is pulled low, the device also pulls nstatus and conf_done low and all i/o pins are tri-stated. once nconfig returns to a logic high level and nstatus is released by the device, reconfiguration begins. figure 7?18 shows how to configure multiple devices using a max ii device. this circuit is similar to the ps configuration circuit for a single device, except stratix ii or strati x ii gx devices are cascaded for multi-device configuration.
altera corporation 7?51 january 2008 stratix ii device handbook, volume 2 configuring stratix ii and stratix ii gx devices figure 7?18. multi-device ps confi guration using an external host note to figure 7?18 : (1) the pull-up resistor should be connected to a supply that provides an acceptable input signal for all devices in the chain. v cc should be high enough to meet the v ih specification of the i/o on th e device and the external host. in multi-device ps configuration the first device?s nce pin is connected to gnd while its nceo pin is connected to nce of the next device in the chain. the last device's nce input comes from the previous device, while its nceo pin is left floating. after the fi rst device completes configuration in a multi-device configuration chain, its nceo pin drives low to activate the second device's nce pin, which prompts the second device to begin configuration. the second device in the chain begins co nfiguration within one clock cycle. therefore, the transfer of data destinations is transparent to the max ii device. all other configuration pins ( nconfig , nstatus , dclk , data0 , and conf_done ) are connected to every device in the chain. configuration signals can require buffering to ensure signal integrity and prevent clock skew problems. ensure that the dclk and data lines are buffered for every fourth device. because all device conf_done pins are tied together, all devices initialize and enter user mode at the same time. since all nstatus and conf_done pins are tied together, if any device detects an error, configuration stops for the entire chain and the entire chain must be reconfigured. for example, if the first device flags an error on nstatus , it resets the chain by pulling its nstatus pin low. this behavior is similar to a single device detecting an error. conf_done nstatus nce data 0 nconfig stratix ii or stratix ii gx device 1 stratix ii or stratix ii gx device 2 memory addr data0 gnd v cc (1) v cc (1) 10 k 10 k dclk conf_done nstatus nce data0 nconfig dclk nceo nceo n.c. external host (max ii device or microprocessor) msel1 msel0 gnd msel3 msel2 v cc msel1 msel0 gnd msel3 msel2 v cc
7?52 altera corporation stratix ii device handbook, volume 2 january 2008 passive serial configuration if the auto-restart config uration after error option is turned on, the devices release their nstatus pins after a reset time-out period (maximum of 100 s). after all nstatus pins are released and pulled high, the max ii device can try to reconfigure the chain without needing to pulse nconfig low. if this option is turn ed off, the max ii device must generate a low-to-high transition (wit h a low pulse of at least 2 s) on nconfig to restart the configuration process. in your system, you can have multi ple devices that contain the same configuration data. to support this configuration scheme, all device nce inputs are tied to gnd, while nceo pins are left fl oating. all other configuration pins ( nconfig , nstatus , dclk , data0 , and conf_done ) are connected to every device in the chain. configuration signals can require buffering to ensure signal integrity and prevent clock skew problems. ensure that the dclk and data lines are buffered for every fourth device. devices must be the same density and package. all devices will start and complete config uration at the same time. figure 7?19 shows multi-device ps configuration when both stratix ii or stratix ii gx devices are receiving the same configuration data. figure 7?19. multiple-device ps configuration when both devices receive the same data notes to figure 7?19 : (1) the pull-up resistor should be connected to a supply that provides an acceptable input signal for all devices in the chain. v cc should be high enough to meet the v ih specification of the i/o on th e device and the external host. (2) the nceo pins of both devices are left unconnected when conf iguring the same configuration data into multiple devices. you can use a single configuration chain to configure stratix ii or stratix ii gx devices with other altera devices. to ensure that all devices in the chain complete configuration at the same time or that an error flagged by one device initiates reconfiguration in all devices, all of the device conf_done and nstatus pins must be tied together. conf_done nstatus nce data 0 nconfig stratix ii device memory addr data0 gnd vcc (1) vcc (1) 10 k 10 k dclk conf_done nstatus nce data0 nconfig dclk nceo nceo n.c. stratix ii device external host (max ii device or microprocessor) msel1 msel0 gnd msel3 msel2 v cc msel1 msel0 gnd msel3 msel2 v cc n.c. gnd (2) (2)
altera corporation 7?53 january 2008 stratix ii device handbook, volume 2 configuring stratix ii and stratix ii gx devices f for more information on configuring multiple altera devices in the same configuration chain, refer to the configuring mixed altera fpga chains chapter in volume 2 of the configuration handbook . ps configuration timing figure 7?20 shows the timing waveform for ps configuration when using a max ii device as an external host. figure 7?20. ps configuration timing waveform note (1) notes to figure 7?20 : (1) the beginning of this waveform shows the device in user-mode. in user-mode, nconfig , nstatus and conf_done are at logic high levels. when nconfig is pulled low, a reconfiguration cycle begins. (2) upon power-up, the stratix ii or stratix ii gx device holds nstatus low for the time of the por delay. (3) upon power-up, before and during configuration, conf_done is low. (4) dclk should not be left floating after configuration. it shou ld be driven high or low, wh ichever is more convenient. data[0] is available as a user i/o pin after configuration an d the state of this pin depends on the dual-purpose pin settings. table 7?15 defines the timing parameters for stratix ii and stratix ii gx devices for ps configuration. nconfig nstatus (2) conf_done (3) dclk data user i/o init_done bit 0 bit 1 bit 2 bit 3 bit n t cd2um t cf2st1 t cf2cd t cfg t ch t cl t dh t dsu t cf2ck t status t clk t cf2st0 t st2ck hi g h-z user mode (4) (4) table 7?15. ps timing parameters for stratix ii and stratix ii gx devices (part 1 of 2) symbol parameter min max units t cf2cd nconfig low to conf_done low 800 ns t cf2st0 nconfig low to nstatus low 800 ns
7?54 altera corporation stratix ii device handbook, volume 2 january 2008 passive serial configuration f device configuration options and how to create configuration files are discussed further in software settings in volume 2 of the configuration handbook . an example ps design that uses a max ii device as the external host for configuration will be availabl e when devices are available. ps configuration using a microprocessor in the ps configuration scheme, a micr oprocessor can control the transfer of configuration data from a storage device, such as flash memory, to the target stratix ii or stratix ii gx device. t cfg nconfig low pulse width 2 s t status nstatus low pulse width 10 100 (1) s t cf2st1 nconfig high to nstatus high 100 (1) s t cf2ck nconfig high to first rising edge on dclk 100 s t st2ck nstatus high to first rising edge of dclk 2 s t dsu data setup time before rising edge on dclk 5 ns t dh data hold time after rising edge on dclk 0 ns t ch dclk high time 4 ns t cl dclk low time 4 ns t clk dclk period 10 ns f max dclk frequency 100 mhz t r input rise time 40 ns t f input fall time 40 ns t cd2um conf_done high to user mode (2) 20 100 s t cd2cu conf_done high to clkusr enabled 4 ? maximum dclk period t cd2umc conf_done high to user mode with clkusr option on t cd2cu + (299 ? clkusr period) notes to table 7?15 : (1) this value is applicable if users do not delay configuration by extending the nconfig or nstatus low pulse width. (2) the minimum and maximum numbers apply on ly if the internal oscillator is chos en as the clock source for starting the device. table 7?15. ps timing parameters for stratix ii and stratix ii gx devices (part 2 of 2) symbol parameter min max units
altera corporation 7?55 january 2008 stratix ii device handbook, volume 2 configuring stratix ii and stratix ii gx devices 1 all information in the ?ps configuration using a max ii device as an external host? section is also applicable when using a microprocessor as an external host. refer to that section for all configuration and timing information. ps configuration using a configuration device you can use an altera configuratio n device, such as an enhanced configuration device, to configure stratix ii and stratix ii gx devices using a serial configuration bitstream. configuration data is stored in the configuration device. figure 7?21 shows the configuration interface connections between a stratix ii or stratix ii gx device and a configuration device. 1 the figures in this chapter only show the configuration-related pins and the configuration pin connections between the configuration device and the device. f for more information on the enhanc ed configuration device and flash interface pins (such as pgm[2..0] , exclk , porsel , a[20..0] , and dq[15..0] ), refer to the enhanced configuration devices ( epc4, epc8, epc16, epcs64, and epcs128) data sheet chapter in volume 2 of the configuration handbook .
7?56 altera corporation stratix ii device handbook, volume 2 january 2008 passive serial configuration figure 7?21. single device ps configura tion using an enhanced configuration device notes to figure 7?21 : (1) the pull-up resistor should be connected to the same supply volt age as the configuration device. (2) the ninit_conf pin is available on enhanced configuration devi ces and has an internal pull-up resistor that is always active, meaning an external pull-up resistor should not be used on the ninit_conf - nconfig line. the ninit_conf pin does not need to be connected if its functionality is not used. if ninit_conf is not used, nconfig must be pulled to v cc either directly or through a resistor. (3) the enhanced conf iguration devices? oe and ncs pins have internal programmable pull-up resistors. if internal pull-up resistors are used, external pull-up resistors should not be used on these pins. th e internal pull-up resistors are used by default in the quartus ii software. to turn off the internal pull -up resistors, check the disable ncs and oe pull-ups on configuration device option when generating programming files. f the value of the internal pull-up resi stors on the enhanced configuration devices can be found in the operating conditions table of the enhanced configuration devices ( epc4, epc8, & epc16 ) d ata sheet chapter in volume 2 of the configuration handbook or the configuration devices for sram-based lut devices data sheet chapter in volume 2 of the configuration handbook . when using enhanced co nfiguration devices, nconfig of the device can be connected to ninit_conf of the configuration device, which allows the init_conf jtag instruction to initiate device configuration. the ninit_conf pin does not need to be connect ed if its functionality is not used. an internal pull -up resistor on the ninit_conf pin is always active in enhanced configuration devices, which means an external pull-up resistor should not be used if nconfig is tied to ninit_conf . upon power-up, the stratix ii and stratix ii gx devices go through a por. the por delay is dependent on the porsel pin setting. when porsel is driven low, the por time is approximately 100 ms. if porsel is driven high, the por time is approximately 12 ms. during por, the device will reset, hold nstatus low, and tri-state al l user i/o pins. the configuration device also goes through a por delay to allow the power supply to stabilize. the por time for epc2 devices is 200 ms (maximum). the por time for enhanced configur ation devices can be set to either stratix ii device dclk data oe ncs ninit_conf (2) dclk data0 nstatus conf_done nconfig vcc vcc gnd (1) (1) nce (3) (3) nceo n.c. enhanced confi g uration device (3) (3) 10 k 10 k msel1 msel0 gnd msel3 msel2 v cc
altera corporation 7?57 january 2008 stratix ii device handbook, volume 2 configuring stratix ii and stratix ii gx devices 100 ms or 2 ms, depending on its porsel pin setting. if the porsel pin is connected to gnd, the por delay is 100 ms. if the porsel pin is connected to v cc , the por delay is 2 ms. during this time, the configuration device drives its oe pin low. this low signal delays configuration because the oe pin is connected to the target device?s nstatus pin. 1 when selecting a por time, you need to ensure that the device completes power-up before the enhanced configuration device exits por. altera recommends that you choose a por time for the stratix ii or stratix ii gx device of 12 ms, while selecting a por time for the enhanced co nfiguration device of 100 ms. when both devices complete por, they release their open-drain oe or nstatus pin, which is then pulled high by a pull-up resistor. once the device successfully exits por, all user i/o pins continue to be tri-stated. if nio_pullup is driven low during power-up and configuration, the user i/o pins and dual-purpose i/o pins will have weak pull-up resistors which are on (after por) before and during configuration. if nio_pullup is driven high, the weak pull-up resistors are disabled. f the value of the weak pull-up resistors on the i/o pins that are on before and during configuration can be found in the dc & switching characteristics chapter in volume 2 of the stratix ii device handbook or the dc & switching characteristics chapter in volume 2 of the stratix ii gx device handbook . when the power supplies have reached the appropriate operating voltages, the target device senses the low-to-high transition on nconfig and initiates the configuration cycle. the configuration cycle consists of three stages: reset, configurat ion, and initialization. while nconfig or nstatus are low, the device is in reset. the beginning of configuration can be delayed by holding the nconfig or nstatus pin low. 1 to begin configuration, power the v ccint , v ccio , and v ccpd voltages (for the banks where th e configuration and jtag pins reside) to the appropriate voltage levels. when nconfig goes high, the device comes out of reset and releases the nstatus pin, which is pulled high by a pull-up resistor. enhanced configuration and epc2 devices have an optional internal pull-up resistor on the oe pin. this option is available in the quartus ii software from the general tab of the device & pin options dialog box. if this internal pull-up resistor is not used, an external 10-k ? pull-up resistor on the oe - nstatus line is required. once nstatus is released, the device is ready to receive configuration data and the configuration stage begins.
7?58 altera corporation stratix ii device handbook, volume 2 january 2008 passive serial configuration when nstatus is pulled high, oe of the configuration device also goes high and the configuration device clocks data out serially to the device using the stratix ii or stratix ii gx device?s internal oscillator. the stratix ii and stratix ii gx devices receive configuration data on the data0 pin and the clock is received on the dclk pin. data is latched into the device on the rising edge of dclk . after the device has received all configuration data successfully, it releases the open-drain conf_done pin, which is pulled high by a pull-up resistor. since conf_done is tied to the configuration device?s ncs pin, the configuration device is disabled when conf_done goes high. enhanced configuration and epc2 devices have an optional internal pull-up resistor on the ncs pin. this option is available in the quartus ii software from the general tab of the device & pin options dialog box. if this internal pull-up resistor is not used, an external 10-k ? pull-up resistor on the ncs - conf_done line is required. a low-to-high transition on conf_done indicates configuration is complete and initialization of the device can begin. in stratix ii and stratix ii gx devices, the initialization clock source is either the internal oscillator (t ypically 10 mhz) or the optional clkusr pin. by default, the internal oscillator is the clock source for initialization. if you are using internal oscillator, the stratix ii or stratix ii gx device supplies itself with enough clock cycles for proper initialization. you also have the flexibility to synchronize initialization of multiple devices or to delay initialization with the clkusr option. you can turn on the enable user-supplied start-up clock ( clkusr ) option in the quartus ii software from the general tab of the device & pin options dialog box. supplying a clock on clkusr will not affect the configuration process. after all configuration data has been accepted and conf_done goes high, clkusr will be enabled after the time specified as t cd2cu . after this time period elapses, the stra tix ii and stratix ii gx devices require 299 clock cycles to initialize properly and enter user mode. stratix ii and stratix ii gx devices support a clkusr f max of 100 mhz. an optional init_done pin is available, which signals the end of initialization and the start of user-m ode with a low-to-high transition. the enable init_done output option is available in the quartus ii software from the general tab of the device & pin options dialog box. if you are using the init_done pin, it will be high due to an external 10-k ? pull-up resistor when nconfig is low and during the beginning of configuration. once the option bit to enable init_done is programmed into the device (during the first frame of configuration data), the init_done pin goes low. when initialization is complete, the init_done pin is released and pulled hi gh. this low-to-hi gh transition signals that the device has entered us er mode. in user-mode, the user i/o
altera corporation 7?59 january 2008 stratix ii device handbook, volume 2 configuring stratix ii and stratix ii gx devices pins will no longer have weak pull-up resistors and will function as assigned in your design. enhanced configuration devices and epc2 devices drive dclk low and data0 high at the end of configuration. if an error occurs during configuration, the device drives its nstatus pin low, resetting itself internally. since the nstatus pin is tied to oe , the configuration device will also be reset. if the auto-restart configuration after error option, available in the quartus ii software, from the general tab of the device & pin options dialog box is turned on, the device automatically initiates reconfiguration if an error occurs. the stratix ii and stratix ii gx devices release the nstatus pin after a reset time-out period (maximum of 100 s). when the nstatus pin is released and pulled high by a pull-up resistor, the configuration device reconfigures the chain. if this option is turned off, the exte rnal system must monitor nstatus for errors and then pulse nconfig low for at least 2 s to restart configuration. the external system can pulse nconfig if nconfig is under system control rather than tied to v cc . in addition, if the configuration device sends all of its data and then detects that conf_done has not gone high, it re cognizes that the device has not configured successfully. enha nced configuration devices wait for 64 dclk cycles after the last configuration bit was sent for conf_done to reach a high state. epc2 devices wait for 16 dclk cycles. in this case, the configuration device pulls its oe pin low, driving the target device?s nstatus pin low. if the auto-restart configuration after error option is set in the software, the target device resets and then releases its nstatus pin after a reset time-out peri od (maximum of 100 s). when nstatus returns to a logic high level, the conf iguration device tries to reconfigure the device. when conf_done is sensed low after configuration, the configuration device recognizes that the target device has not configured successfully. therefore, your system should not pull conf_done low to delay initialization. instead, use the clkusr option to synchronize the initialization of multiple devices that are not in the same configuration chain. devices in the same configurat ion chain will initialize together if their conf_done pins are tied together. 1 if you are using the optional clkusr pin and nconfig is pulled low to restart configuration duri ng device initialization, you need to ensure that clkusr continues toggling during the time nstatus is low (maximum of 100 s). when the device is in user-mode, pulling the nconfig pin low initiates a reconfiguration. the nconfig pin should be low for at least 2 s. when nconfig is pulled low, the device also pulls nstatus and conf_done low and all i/o pins are tri-stated. because conf_done is pulled low, this
7?60 altera corporation stratix ii device handbook, volume 2 january 2008 passive serial configuration activates the configuration device because it sees its ncs pin drive low. once nconfig returns to a logic high level and nstatus is released by the device, reconfiguration begins. figure 7?22 shows how to configure multiple devices with an enhanced configuration device. this circuit is similar to the configuration device circuit for a single device, except stratix ii or stratix ii gx devices are cascaded for multi-device configuration. figure 7?22. multi-device ps configurati on using an enhanced configuration device notes to figure 7?22 : (1) the pull-up resistor should be connected to the same supply volt age as the configuration device. (2) the ninit_conf pin is available on enhanced configuration devi ces and has an internal pull-up resistor that is always active, meaning an external pull-up resistor should not be used on the ninit_conf - nconfig line. the ninit_conf pin does not need to be connected if its functionality is not used. if ninit_conf is not used, nconfig must be pulled to v cc either directly or through a resistor. (3) the enhanced conf iguration devices? oe and ncs pins have internal programmable pull-up resistors. if internal pull-up resistors are used, external pull-up resistors should not be used on these pins. th e internal pull-up resistors are used by default in the quartus ii software. to turn off the internal pull -up resistors, check the disable ncs and oe pull-ups on configuration device option when generating programming files. 1 enhanced configuration devices cannot be cascaded. when performing multi-device configuration, you must generate the configuration device's pof from each project?s sof. you can combine multiple sofs using the convert programming files window in the quartus ii software. f for more information on how to create configuration files for multi-device configuratio n chains, refer to the software settings chapter of the configuration handbook. enhanced confi g uration device dclk data oe ncs ninit_conf (2) dclk data0 nstatus conf_done nconfig vcc vcc gnd nce dclk data0 nstatus conf_done nconfig nce nceo (1) (1) (3) nceo stratix ii or stratix ii gx device 2 stratix ii or stratix ii gx device 1 (3) n.c. 10 k 10 k (3) (3) msel1 msel0 gnd msel3 msel2 v cc msel1 msel0 gnd msel3 msel2 v cc
altera corporation 7?61 january 2008 stratix ii device handbook, volume 2 configuring stratix ii and stratix ii gx devices in multi-device ps configuration, the first device?s nce pin is connected to gnd while its nceo pin is connected to nce of the next device in the chain. the last device?s nce input comes from the previous device, while its nceo pin is left floating. after the fi rst device completes configuration in a multi-device configuration chain, its nceo pin drives low to activate the second device?s nce pin, prompting the second device to begin configuration. all other configuration pins ( nconfig , nstatus , dclk , data0 , and conf_done ) are connected to every device in the chain. configuration signals can require buff ering to ensure signal integrity and prevent clock skew problems. ensure that the dclk and data lines are buffered for every fourth device. when configuring multiple devices, co nfiguration does not begin until all devices release their oe or nstatus pins. similarly, since all device conf_done pins are tied together, all devices initialize and enter user mode at the same time. since all nstatus and conf_done pins are tied together, if any device detects an error, configuration stops for the entire chain and the entire chain must be reconfigured. for example, if the first device flags an error on nstatus , it resets the chain by pulling its nstatus pin low. this low signal drives the oe pin low on the enhanced configuration device and drives nstatus low on all devices, causing them to enter a reset state. this behavior is similar to a single device detecting an error. if the auto-restart configuration after error option is turned on, the devices will automatically initiate reconfiguration if an error occurs. the devices will release their nstatus pins after a reset time-out period (maximum of 100 s). when all the nstatus pins are released and pulled high, the configuration device trie s to reconfigure the chain. if the auto-restart configuration after error option is turned off, the external system must monitor nstatus for errors and then pulse nconfig low for at least 2 s to restart configurat ion. the external system can pulse nconfig if nconfig is under system control rather than tied to v cc . the enhanced configuration devices al so support parallel configuration of up to eight devices. the n-bit ( n = 1, 2, 4, or 8) ps configuration mode allows enhanced configuration device s to concurrently configure devices or a chain of devices. in addition, thes e devices do not have to be the same device family or density as they can be any combination of altera devices. an individual enhanced configuration device data line is available for each targeted device. each data line can also feed a daisy chain of devices. figure 7?23 shows how to concurrently configure multiple devices using an enhanced configuration device.
7?62 altera corporation stratix ii device handbook, volume 2 january 2008 passive serial configuration figure 7?23. concurrent ps configura tion of multiple devices using an enhanced configuration device notes to figure 7?23 : (1) the pull-up resistor sh ould be connected to the same supply voltage as the configuration device. (2) the ninit_conf pin is available on enhanced configuration devices and has an internal pull-up resistor that is always active, meaning an external pull-up resistor should not be used on the ninit_conf - nconfig line. the ninit_conf pin does not need to be connected if it s functionality is not used. if ninit_conf is not used, nconfig must be pulled to v cc either directly or through a resistor. (3) the enhanced conf iguration devices? oe and ncs pins have internal programmable pull-up resistors. if intern al pull-up resistors are used, external pull-up resistors should not be used on th ese pins. the internal pull-up resistors are used by default in the quartus ii soft ware. to turn off the internal pull-up resistors, check the disable ncs and oe pull-ups on configuration device option when generating programming files. dclk data 0 nstatus conf_done nconfig v cc gnd (3) nce (3) stratix ii device 1 v cc dclk data 0 nconfig nce dclk data0 gnd gnd dclk data 0 oe (3) ncs (3) ninit_conf (2) data 1 data[2..6] nstatus conf_done nstatus conf_done nconfig nce data 7 10 k 10 k stratix ii device 2 stratix ii device 8 n.c. nceo n.c. nceo n.c. nceo (1) (1) enhanced confi g uration device msel1 msel0 gnd msel3 msel2 v cc msel1 msel0 gnd msel3 msel2 v cc msel1 msel0 gnd msel3 msel2 v cc
altera corporation 7?63 january 2008 stratix ii device handbook, volume 2 configuring stratix ii and stratix ii gx devices the quartus ii software only allo ws the selection of n-bit ps configuration modes, where n must be 1, 2, 4, or 8. however, you can use these modes to configure any number of devices from 1 to 8. when configuring sram-based devices using n-bit ps modes, use table 7?16 to select the appropriate configuration mode for the fastest configuration times. for example, if you configure three devices, you would use the 4-bit ps mode. for the data0 , data1 , and data2 lines, the corresponding sof data is transmitted from the config uration device to the device. for data3 , you can leave the corresponding bit3 line blank in the quartus ii software. on the pcb, leave the data3 line from the enhanced configuration device unconnected. alternatively, you can daisy chain two devices to one data line while the other data lines drive one device each. for example, you could use the 2-bit ps mode to drive two devices with data bit0 (two ep2s15 devices) and the third device (ep2s30 device) with data bit1. this 2-bit ps configuration scheme requires less space in the configuration flash memory, but can increase the total system configuration time. a system may have multiple devices that contain the sa me configuration data. to support this configuration scheme, all device nce inputs are tied to gnd, while nceo pins are left floating. a ll other configuration pins ( nconfig , nstatus , dclk , data0 , and conf_done ) are connected to every device in the chain. configuration signals can require buffering to ensure signal integrity and prevent cl ock skew problems. ensure that the dclk and data lines are buffered for every fourth device. devices must be the same density and package. all devices will start and complete table 7?16. recommended configurat ion using n-bit ps modes number of devices (1) recommended configuration mode 11-bit ps 22-bit ps 34-bit ps 44-bit ps 58-bit ps 68-bit ps 78-bit ps 88-bit ps note to table 7?16 : (1) assume that each data line is only configuring on e device, not a daisy chain of devices.
7?64 altera corporation stratix ii device handbook, volume 2 january 2008 passive serial configuration configuration at the same time. figure 7?24 shows multi-device ps configuration when the stratix ii or stratix ii gx devices are receiving the same configuration data. figure 7?24. multiple-device ps c onfiguration using an enhanced config uration device when devices receive the same data notes to figure 7?24 : (1) the pull-up resistor should be connected to the same supply volt age as the configuration device. (2) the ninit_conf pin is available on enhanced configuration devi ces and has an internal pull-up resistor that is always active, meaning an external pull-up resistor should not be used on the ninit_conf - nconfig line. the ninit_conf pin does not need to be connected if its functionality is not used. if ninit_conf is not used, nconfig must be pulled to v cc either directly or through a resistor. (3) the enhanced conf iguration devices? oe and ncs pins have internal programmable pull-up resistors. if internal pull-up resistors are used, external pull-up resistors should not be used on these pins. th e internal pull-up resistors are used by default in the quartus ii software. to turn off the internal pull -up resistors, check the disable ncs and oe pull-ups on configuration device option when generating programming files. (4) the nceo pins of all devices are left unco nnected when configuring the same configuration data into multiple devices. dclk data 0 nconfig v cc gnd (3) nce (3) v cc dclk data 0 nstatus conf_done nconfig nce nstatus conf_done dclk data0 nconfig nce gnd gnd stratix ii or stratix ii gx device 1 stratix ii or stratix ii gx device 2 last stratix ii or stratix ii gx device dclk data 0 oe ncs ninit_conf (2) nstatus conf_done n.c. nceo n.c. nceo n.c. nceo (4) (4) (4) (1) (1) 10 k 10 k (3) (3) enhanced confi g uration device msel1 msel0 gnd msel3 msel2 v cc msel1 msel0 gnd msel3 msel2 v cc msel1 msel0 gnd msel3 msel2 v cc
altera corporation 7?65 january 2008 stratix ii device handbook, volume 2 configuring stratix ii and stratix ii gx devices you can cascade several epc2 devices to configure multiple stratix ii or stratix ii gx devices. the first configuration device in the chain is the master configuration device, while the subsequent devices are the slave devices. the master configuration device sends dclk to the stratix ii or stratix ii gx devices and to the slave co nfiguration devices. the first epc device?s ncs pin is connected to the conf_done pins of the devices, while its ncasc pin is connected to ncs of the next configuration device in the chain. the last device?s ncs input comes from the previous device, while its ncasc pin is left floating. when all data from the first configuration device is sent, it drives ncasc low, which in turn drives ncs on the next configuration device. a configuration device requires less than one clock cycle to activate a subsequent configuration device, so the data stream is uninterrupted. 1 enhanced configuration devices cannot be cascaded. because all nstatus and conf_done pins are tied together, if any device detects an error, the master configur ation device stops configuration for the entire chain and the entire chain must be reconfigured. for example, if the master configuration device does not detect conf_done going high at the end of configuration, it resets the entire chain by pulling its oe pin low. this low signal drives the oe pin low on the slave configuration device(s) and drives nstatus low on all devices, causing them to enter a reset state. this behavior is similar to the device detecting an error in the configuration data.
7?66 altera corporation stratix ii device handbook, volume 2 january 2008 passive serial configuration figure 7?25 shows how to configure multiple devices using cascaded epc2 devices. figure 7?25. multi-device ps configur ation using cascaded epc2 devices notes to figure 7?25 : (1) the pull-up resistor should be connected to the same supply volt age as the configuration device. (2) the ninit_conf pin (available on enhanced conf iguration devices and epc2 device s only) has an internal pull-up resistor that is always active, meaning an extern al pull-up resistor should not be used on the ninit_conf - nconfig line. the ninit_conf pin does not need to be connected if its functionality is not used. (3) the enhanced configuration devices? and epc2 devices? oe and ncs pins have internal programmable pull-up resistors. external 10-k ?? pull-up resistors should be us ed. to turn off the internal pull-up resistors, check the disable ncs and oe pull-ups on configuration device option when generating programming files. when using enhanced configuration devices or epc2 devices, nconfig of the device can be connected to ninit_conf of the configuration device, allowing the init_conf jtag instruction to initiate device configuration. the ninit_conf pin does not need to be connected if its functionality is not used. an in ternal pull-up resistor on the ninit_conf pin is always active in the enhanced configuration devices and the epc2 devices, which means that you should n?t be using an external pull-up resistor if nconfig is tied to ninit_conf . if you are using multiple epc2 devices to configure a stratix ii or stratix ii gx device(s), only the first epc2 has its ninit_conf pin tied to the device?s nconfig pin. you can use a single configuration chain to configure stratix ii or stratix ii gx devices with other altera devices. to ensure that all devices in the chain complete configuration at the same time or that an error flagged by one device initiates reconfiguration in all devices, all of the device conf_done and nstatus pins must be tied together. epc2/epc1 device 1 dclk data oe ncs ninit_conf (2) dclk data0 nstatus conf_done nconfig vcc vcc gnd nce vcc dclk data ncs oe dclk data0 nstatus conf_done nconfig nce nceo (2) ncasc stratix ii device 1 (1) (1) (1) (3) nceo ninit_conf stratix ii device 2 (3) n.c. epc2/epc1 device 2 10 k 10 k 10 k (3) (3) msel1 msel0 gnd msel3 msel2 v cc msel1 msel0 gnd msel3 msel2 v cc
altera corporation 7?67 january 2008 stratix ii device handbook, volume 2 configuring stratix ii and stratix ii gx devices f for more information on configuring multiple altera devices in the same configuration chain, refer to the configuring mixed altera fpga chains chapter in the configuration handbook . figure 7?26 shows the timing waveform fo r the ps configuration scheme using a configuration device. figure 7?26. stratix ii and stratix ii gx ps configuration using a confi guration device timing waveform note to figure 7?26 : (1) the initialization clock can come from the stratix ii or stratix ii g x device?s internal oscillator or the clkusr pin. f for timing information, refer to the enhanced configuration devices (epc4, epc8 & epc16) data sheet chapter in volume 2 of the configuration handbook or the configuration devices for sram-based lut devices data sheet chapter in volume 2 of the configuration handbook . f device configuration options and how to create configuration files are discussed further in the software settings chapter in volume 2 of the configuration handbook . ps configuration using a download cable in this section, the generic term ?d ownload cable? includes the altera usb-blaster ? universal serial bus (usb) port download cable, masterblaster ? serial/usb communications cable, byteblaster ? ii parallel port download cable, and the byteblaster mv parallel port download cable. in ps configuration with a download ca ble, an intelligen t host (such as a pc) transfers data from a storage device to the device via the usb blaster, masterblaster, byteblaster ii, or byteblastermv cable. dd d d 0 1 2 3 d n tri-state user mode (1) t oezx t por t ch t cl t dsu t co t dh tri-state oe/nstatus ncs/conf_done dclk data user i/o init_done ninit_conf or vcc/nconfig
7?68 altera corporation stratix ii device handbook, volume 2 january 2008 passive serial configuration upon power-up, the stratix ii and stratix ii gx devices go through a por. the por delay is dependent on the porsel pin setting. when porsel is driven low, the por time is approximately 100 ms. if porsel is driven high, the por time is approximately 12 ms. during por, the device will reset, hold nstatus low, and tri-state all user i/o pins. once the device successfully exits por, all user i/o pins continue to be tri-stated. if nio_pullup is driven low during power-up and configuration, the user i/o pins an d dual-purpose i/o pins will have weak pull-up resistors which are on (after por) before and during configuration. if nio_pullup is driven high, the weak pull-up resistors are disabled. f the value of the weak pull-up resistors on the i/o pins that are on before and during configuration can be found in the dc & switching characteristics chapter in volume 1 of the stratix ii device handbook and the dc & switching characteristics chapter in volume 1 of the stratix ii gx device handbook. the configuration cycle consists of three stages: reset, configuration and initialization. while nconfig or nstatus are low, the device is in reset. to initiate configuration in this scheme, the download cable generates a low-to-high transition on the nconfig pin. 1 to begin configuration, power the v ccint , v ccio , and v ccpd voltages (for the banks where th e configuration and jtag pins reside) to the appropriate voltage levels. when nconfig goes high, the device comes out of reset and releases the open-drain nstatus pin, which is then pulled high by an external 10-k ? pull-up resistor. once nstatus is released the device is ready to receive configuration data and the configuration stage begins. the programming hardware or download cable then plac es the configuration data one bit at a time on the device?s data0 pin. the configuration data is clocked into the target device until conf_done goes high. the conf_done pin must have an external 10-k ? pull-up resistor in order for the device to initialize. when using a download cable, setting the auto-restart configuration after error option does not affect the configuration cycle because you must manually restart configuration in the quartus ii software when an error occurs. additionally, the enable user-supplied start-up clock ( clkusr ) option has no affect on the device initialization since this option is disabled in the sof when programming the device using the quartus ii programmer and download ca ble. therefore, if you turn on the clkusr option, you do not need to provide a clock on clkusr when you are configuring the device with the quartus ii programmer and a
altera corporation 7?69 january 2008 stratix ii device handbook, volume 2 configuring stratix ii and stratix ii gx devices download cable. figure 7?27 shows ps configuration for stratix ii or stratix ii gx devices using a usb blaster, masterblaster, byteblaster ii, or byteblastermv cable. figure 7?27. ps configuration using a usb blaster, mast erblaster, byteblaster ii or byteblastermv cable notes to figure 7?27 : (1) the pull-up resistor should be connected to the same supply voltage as the usb blaster, masterblaster (v io pin), byteblaster ii or byteblastermv cable. (2) the pull-up resistors on data0 and dclk are only needed if the download ca ble is the only configuration scheme used on your board. this ensures that data0 and dclk are not left floating after conf iguration. for example, if you are also using a configuration de vice, the pull-up resistors on data0 and dclk are not needed. (3) pin 6 of the header is a v io reference voltage for the masterblaster output driver. v io should match the device?s v ccio . refer to the masterblaster serial/usb communications cable user guide for this value. in the byteblastermv cable, this pin is a no connect. in the usb blaster and byteblaster ii cables, this pin is connected to nce when it is used for active serial programmin g, otherwise it is a no connect. you can use a download cable to configure multiple stratix ii or stratix ii gx devices by connecting each device?s nceo pin to the subsequent device?s nce pin. the first device?s nce pin is connected to gnd while its nceo pin is connected to the nce of the next device in the chain. the last device?s nce input comes from the previous device, while its nceo pin is left floating. al l other config uration pins, nconfig , nstatus , dclk , data0 , and conf_done are connected to every device in the chain. because all conf_done pins are tied together, all devices in the chain initialize and enter user mode at the same time. d ownlo ad cab l e 1 0 -pin m a l e h eader (ps mo de ) v cc (1) v cc (1) v cc v cc (1) v cc (1) v cc (1) stratix ii or stratix ii gx device dclk nconfig conf_done shield gnd 10 k 10 k 10 k 10 k 10 k nstatus data0 pin 1 nce gnd gnd v io (3) (2) (2) nceo n.c. msel1 msel0 gnd msel3 msel2 v cc
7?70 altera corporation stratix ii device handbook, volume 2 january 2008 passive serial configuration in addition, because the nstatus pins are tied together, the entire chain halts configuration if any de vice detects an error. the auto-restart configuration after error option does not affect the configuration cycle because you must manually restart configuration in the quartus ii software when an error occurs. figure 7?28 shows how to configure multiple stratix ii or stratix ii gx devices with a download cable. figure 7?28. multi-device ps configur ation using a usb blaster, mast erblaster, byteblaster ii or byteblastermv cable notes to figure 7?28 : (1) the pull-up resistor should be connected to the same supply voltage as the usb blaster, masterblaster (v io pin), byteblaster ii or byteblastermv cable. (2) the pull-up resistors on data0 and dclk are only needed if the download ca ble is the only configuration scheme used on your board. this is to ensure that data0 and dclk are not left floating after co nfiguration. for example, if you are also using a configuration device, the pull-up resistors on data0 and dclk are not needed. (3) pin 6 of the header is a v io reference voltage for the masterblaster output driver. v io should match the device?s v ccio . refer to the masterblaster serial/usb communications cable user guide for this value. in the byteblastermv cable, this pin is a no connect. in the usb blaster and byteblaster ii cables, this pin is connected to nce when it is used for active serial programmin g, otherwise it is a no connect. stratix ii or stratix ii gx device 1 stratix ii or stratix ii gx device 2 nce nconfig conf_done dclk nce nconfig conf_done dclk nceo gnd (ps mo de ) v cc v cc (1) v cc (1) v cc (1) v cc (1) v cc (1) nstatus nstatus data0 data0 gnd 10 k 10 k 10 k 10 k 10 k pin 1 d ownlo ad cab l e 1 0 -pin m a l e h eader nceo n.c. gnd v io (3) (2) (2) msel1 msel0 gnd msel3 msel2 v cc msel1 msel0 gnd msel3 msel2 v cc
altera corporation 7?71 january 2008 stratix ii device handbook, volume 2 configuring stratix ii and stratix ii gx devices if you are using a download cable to configure device(s) on a board that also has configuration devices, elec trically isolate the configuration device from the target device(s) an d cable. one way of isolating the configuration device is to add logic, such as a multiplexer, that can select between the configuration device and the cable. the multiplexer chip allows bidirectional transfers on the nstatus and conf_done signals. another option is to add switch es to the five common signals ( nconfig , nstatus , dclk , data0 , and conf_done ) between the cable and the configuration device. the last option is to remove the configuration device from the board when config uring the device with the cable. figure 7?29 shows a combination of a configuration device and a download cable to configure an device.
7?72 altera corporation stratix ii device handbook, volume 2 january 2008 passive serial configuration figure 7?29. ps configuration with a download cable and configurat ion device circuit notes to figure 7?29 : (1) the pull-up resistor should be connected to the same supply volt age as the configuration device. (2) pin 6 of the header is a v io reference voltage for the masterblaster output driver. v io should match the device?s v ccio . refer to the masterblaster serial/usb communications cable user guide for this value. in the byteblastermv cable, this pin is a no connect. in the usb blaster and byteblaster ii cables, this pin is connected to nce when it is used for active serial programmin g, otherwise it is a no connect. (3) you should not attempt configuration with a download cable while a configuration device is connected to a stratix ii or stratix ii gx device. instead, you should either remove the configuration device from its socket when using the download cable or place a switch on the five common signals between the download cable and the configuration device. (4) the ninit_conf pin (available on enhanced conf iguration devices and epc2 device s only) has an internal pull-up resistor that is always active. this means an exte rnal pull-up resistor should not be used on the ninit_conf - nconfig line. the ninit_conf pin does not need to be connected if its functionality is not used. (5) the enhanced configuration devices? and epc2 devices? oe and ncs pins have internal programmable pull-up resistors. if internal pull-u p resistors are used, external pull-up resistors should not be used on these pins. the internal pull-up resistors are used by default in the quartu s ii software. to turn off the internal pull-up resistors, check the disable ncs and oe pull-up resistors on configuration device option when generating programming files. f for more information on how to use the usb blaster, masterblaster, byteblaster ii or byteblastermv cables , refer to the following data sheets: usb blaster download cable user guide masterblaster serial /usb communications cable user guide byteblaster ii download cable user guide byteblastermv download cable user guide stratix ii or stratix ii gx device nce nconfig conf_done dclk nceo gnd d ownlo ad cab l e 1 0 -pin m a l e h eader (ps mo de ) v cc v cc v cc (1) v cc (1) nstatus data0 gnd 10 k 10 k 10 k pin 1 confi g uration device (3) (3) (3) (3) (3) gn d vio (2) n.c. (1) (4) (5) (5) dclk data oe ncs ninit_conf (4) (5) (5) msel1 msel0 gnd msel3 msel2 v cc
altera corporation 7?73 january 2008 stratix ii device handbook, volume 2 configuring stratix ii and stratix ii gx devices passive parallel asynchronous configuration passive parallel asynchronous (ppa) configuration uses an intelligent host, such as a microprocessor, to transfer configuration data from a storage device, such as flash me mory, to the target stratix ii or stratix ii gx device. configuration data can be stored in rbf, hex, or ttf format. the host system outputs byte-wide data and the accompanying strobe signals to the device. when using ppa, pull the dclk pin high through a 10-k ? pull- up resistor to prevent unused conf iguration input pins from floating. 1 you cannot use the stratix ii or stratix ii gx decompression and design security features if you are configuring your stratix ii or stratix ii gx device using ppa mode. table 7?17 shows the msel pin settings when using the ps configuration scheme. figure 7?30 shows the configuration inte rface connections between the device and a microprocessor for single device ppa configuration. the microprocessor or an optional addr ess decoder can control the device?s chip select pins, ncs and cs . the address decoder allows the microprocessor to select the stratix ii or stratix ii gx device by accessing a particular address, which simplifies the configuration process. hold the ncs and cs pins active during configuration and initialization. table 7?17. stratix ii and stratix ii g x msel pin settings for ppa configuration schemes configuration schem e msel3 msel2 msel1 msel0 ppa 0001 remote system upgrade ppa (1) 0101 note to table 7?17 : (1) this scheme requires that you drive the runlu pin to specify either remote update or local update. for more information about remote system upgrades in stratix ii and stratix ii gx devices, refer to the remote system upgrades with stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii device handbook or the remote system upgrades with stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook .
7?74 altera corporation stratix ii device handbook, volume 2 january 2008 passive parallel asynchronous configuration figure 7?30. single device ppa config uration using a microprocessor notes to figure 7?30 : (1) if not used, the cs pin can be connected to v cc directly. if not used, the ncs pin can be connected to gnd directly. (2) the pull-up resistor should be connected to a supply that provides an acceptable input signal for the device. v cc should be high enough to meet the v ih specification of the i/o on the device and the external host. during ppa configuration, it is only required to use either the ncs or cs pin. therefore, if you are using only one chip-select input, the other must be tied to the active state. for example, ncs can be tied to ground while cs is toggled to control configuration. the device?s ncs or cs pins can be toggled during ppa configuration if the design meets the specifications set for t cssu , t wsp , and t csh listed in table 7?18 . upon power-up, the stratix ii and stratix ii gx devices go through a por. the por delay is dependent on the porsel pin setting. when porsel is driven low, the por time is approximately 100 ms. if porsel is driven high, the por time is approximately 12 ms. during por, the device will reset, hold nstatus low, and tri-state all user i/o pins. once the device successfully exits por, all user i/o pins continue to be tri-stated. if nio_pullup is driven low during power-up and configuration, the user i/o pins an d dual-purpose i/o pins will have weak pull-up resistors which are on (after por) before and during configuration. if nio_pullup is driven high, the weak pull-up resistors are disabled. msel3 msel2 msel1 msel0 stratix ii or stratix ii gx device dclk 10 k 10 k 10 k ncs cs conf_done nstatus nce data[7..0] nws nrs nconfig rdynbsy address decoder v cc v cc v cc addr microprocessor v cc memory addr data[7..0] gnd nceo n.c. (2) (2) (2) (1) (1) gnd
altera corporation 7?75 january 2008 stratix ii device handbook, volume 2 configuring stratix ii and stratix ii gx devices 1 you can hold nconfig low in order to stop device configuration. f the value of the weak pull-up resistors on the i/o pins that are on before and during configuration can be found in the dc & switching characteristics chapter in volume 1 of the stratix ii device handbook and the dc & switching characteristics chapter in volume 1 of the stratix ii gx device handbook . the configuration cycle consists of three stages: reset, configuration and initialization. while nconfig or nstatus are low, the device is in reset. to initiate configuration, the microprocessor must generate a low-to-high transition on the nconfig pin. 1 to begin configuration, power the v ccint , v ccio , and v ccpd voltages (for the banks where th e configuration and jtag pins reside) to the appropriate voltage levels. when nconfig goes high, the device comes out of reset and releases the open-drain nstatus pin, which is then pulled high by an external 10-k ? pull-up resistor. once nstatus is released the device is ready to receive configuration data and the configuration stage begins. when nstatus is pulled high, the microprocessor should then assert the target device?s ncs pin low and/or cs pin high. next, the microprocessor places an 8-bit configuration word (one byte ) on the target device?s data[7..0] pins and pulses the nws pin low. on the rising edge of nws , the target device latches in a byte of configuration data and drives its rdynbsy signal low, which indicates it is processing the byte of configuration data. the microprocessor can then perform other system functions while the stratix ii or stratix ii gx device is processing the byte of configuration data. during the time rdynbsy is low, the stratix ii or stratix ii gx device internally processes the configuration data using its internal oscillator (typically 100 mhz). when the device is ready for the next byte of configuration data, it will drive rdynbsy high. if the microprocessor senses a high signal when it polls rdynbsy , the microprocessor sends the next byte of configuration data to the device. alternatively, the nrs signal can be strobed low, causing the rdynbsy signal to appear on data7 . because rdynbsy does not need to be monitored, this pin doesn?t need to be connected to the microprocessor. do not drive data onto the data bus while nrs is low because it will cause contention on the data7 pin. if you are not using the nrs pin to monitor configuration, it should be tied high.
7?76 altera corporation stratix ii device handbook, volume 2 january 2008 passive parallel asynchronous configuration to simplify configuration and save an i/o port, the microprocessor can wait for the total time of t busy (max) + t rdy2ws + t w2sb before sending the next data byte. in this set-up, nrs should be ti ed high and rdynbsy does not need to be connected to the microprocessor. the t busy , t rdy2ws , and t w2sb timing specifications are listed in table 7?18 on page 7?82 . next, the microprocessor checks nstatus and conf_done . if nstatus is not low and conf_done is not high, the microprocessor sends the next data byte. however, if nstatus is not low and all the configuration data has been received, the device is ready for initialization. the conf_done pin will go high one byte early in parallel configuration (fpp and ppa) modes. the last byte is required for serial configuration (as and ps) modes. a low-to-high transition on conf_done indicates configuration is complete and initialization of the device can begin. the open-drain conf_done pin is pulled high by an external 10-k ?? pull-up resistor. the conf_done pin must have an external 10-k ? pull-up resistor in order for the device to initialize. in stratix ii and stratix ii gx devices, the initialization clock source is either the internal oscillator (t ypically 10 mhz) or the optional clkusr pin. by default, the internal oscillator is the clock source for initialization. if the internal oscillator is used , the stratix ii or stratix ii gx device provides itself with enough clock cycles for proper initialization. therefore, if the internal oscillator is the initialization clock source, sending the entire configuration file to the device is sufficient to configure and initialize the device. you also have the flexibility to synchronize initialization of multiple devices or to delay initialization with the clkusr option. the enable user-supplied start-up clock ( clkusr ) option can be turned on in the quartus ii software from the general tab of the device & pin options dialog box. suppl ying a clock on clkusr does not affect the configuration process. after conf_done goes high, clkusr is enabled after the time specified as t cd2cu . after this time period elapses, the stratix ii and stratix ii gx devices re quire 299 clock cycles to initialize properly and enter user mode. stratix ii devices support a clkusr f max of 100 mhz. an optional init_done pin is available, which signals the end of initialization and the start of user-m ode with a low-to-high transition. this enable init_done output option is available in the quartus ii software from the general tab of the device & pin options dialog box. if the init_done pin is used it is high because of an external 10-k ? pull-up resistor when nconfig is low and during the beginning of configuration. once the option bit to enable init_done is programmed into the device (during the first frame of configuration data), the init_done pin goes low. when initialization is complete, the
altera corporation 7?77 january 2008 stratix ii device handbook, volume 2 configuring stratix ii and stratix ii gx devices init_done pin is released and pulled high. the microprocessor must be able to detect this low-to-high tran sition that signals the device has entered user mode. when initialization is complete, the device enters user mode. in user-mode, the user i/o pi ns no longer have weak pull-up resistors and function as assigned in your design. to ensure data[7..0] is not left floating at the end of configuration, the microprocessor must drive them either high or low, whichever is convenient on your board. after configuration, the ncs , cs , nrs , nws , rdynbsy , and data[7..0] pins can be used as user i/o pins. when choosing the ppa scheme in the quartus ii software as a default, these i/o pins are tri-stated in user mode and should be driven by the microprocessor. to change this default option in the quartus ii software, select the dual-purpose pins tab of the device & pin options dialog box. if an error occurs during configuration, the device drives its nstatus pin low, resetting itself internally. the low signal on the nstatus pin also alerts the microproce ssor that there is an error. if the auto-restart configuration after error option-available in the quartus ii software from the general tab of the device & pin options dialog box-is turned on, the device releases nstatus after a reset time-out period (maximum of 100 s). after nstatus is released and pulled high by a pull-up resistor, the microprocessor can try to reconf igure the target device without needing to pulse nconfig low. if this option is turned off, the microprocessor must generate a low-to -high transition (with a low pulse of at least 2 s) on nconfig to restart the configuration process. the microprocessor can also monitor the conf_done and init_done pins to ensure successful configuration. to detect errors and determine when programming completes, monitor the conf_done pin with the microprocessor. if the microprocessor sends all configuration data but conf_done or init_done has not gone high, the microprocessor must reconfigure the target device. 1 if you are using the optional clkusr pin and nconfig is pulled low to restart configuration during device initialization, ensure clkusr continues toggling during the time nstatus is low (maximum of 100 s). when the device is in user-mode, a reconfiguration can be initiated by transitioning the nconfig pin low-to-high. the nconfig pin should go low for at least 2 s. when nconfig is pulled low, the device also pulls nstatus and conf_done low and all i/o pins are tri-stated. once nconfig returns to a logic high level and nstatus is released by the device, reconfiguration begins.
7?78 altera corporation stratix ii device handbook, volume 2 january 2008 passive parallel asynchronous configuration figure 7?31 shows how to configure multiple stratix ii or stratix ii gx devices using a microprocessor. this circuit is similar to the ppa configuration circuit for a single device, except the devices are cascaded for multi-device configuration. figure 7?31. multi-device ppa confi guration using a microprocessor notes to figure 7?31 : (1) if not used, the cs pin can be connected to v cc directly. if not used, the ncs pin can be connected to gnd directly. (2) the pull-up resistor should be connected to a supply that provides an acceptable input signal for all devices in the chain. v cc should be high enough to meet the v ih specification of the i/o on th e device and the external host. in multi-device ppa configuration the first device?s nce pin is connected to gnd while its nceo pin is connected to nce of the next device in the chain. the last device?s nce input comes from the previous device, while its nceo pin is left floating. after the fi rst device completes configuration in a multi-device configuration chain, its nceo pin drives low to activate the second device?s nce pin, which prompts the second device to begin configuration. the second device in the chain begins co nfiguration within one clock cycle. therefore, the transfer of data destinations is transparent to the microprocessor. each device?s rdynbsy pin can have a sepa rate input to the microprocessor. alternatively, if the mi croprocessor is pin limited, all the rdynbsy pins can feed an and gate and the output of the and gate can feed the microprocessor. for example, if you have two devices in a ppa gnd v cc address decoder addr addr memory data[7..0] ncs cs (1) conf_done nstatus nce nws nrs nconfig rdynbsy ncs cs (1) conf_done nstatus nce nws nrs nconfig rdynbsy microprocessor data[7..0] v cc data[7..0] nceo n.c. nceo (2) (2) dclk v cc (2) dclk (2) v cc 10 k stratix ii device 1 stratix ii device 2 (1) (1) msel3 msel2 msel1 msel0 vcc gnd 10 k 10 k 10 k 2
altera corporation 7?79 january 2008 stratix ii device handbook, volume 2 configuring stratix ii and stratix ii gx devices configuration chain, the second device?s rdynbsy pin will be high during the time that the first device is being configured. when the first device has been successfully configured, it will drive nceo low to activate the next device in the chain and drive its rdynbsy pin high. therefore, since rdynbsy signal is driven high before configuration and after configuration before entering user-mode, the device being configured will govern the output of the and gate. the nrs signal can be used in multi-device ppa chain because the stratix ii and stratix ii gx devices tri-state the data[7..0] pins before configuration and after configuration before entering user-mode to avoid contention. therefore, only the device that is currently being configured responds to the nrs strobe by asserting data7 . all other configuration pins ( nconfig , nstatus , data[7..0] , ncs , cs , nws , nrs and conf_done ) are connected to every device in the chain. it is not necessary to tie ncs and cs together for every device in the chain, as each device?s ncs and cs input can be driven by a separate source. configuration signals may require buffering to ensure signal integrity and prevent clock skew pr oblems. ensure that the data lines are buffered for every fourth device. because all device conf_done pins are tied together, all devices initialize and enter user mode at the same time. since all nstatus and conf_done pins are tied together, if any device detects an error, configuration stops for the entire chain and the entire chain must be reconfigured. for example, if the first device flags an error on nstatus , it resets the chain by pulling its nstatus pin low. this behavior is similar to a single device detecting an error. if the auto-restart config uration after error option is turned on, the devices release their nstatus pins after a reset time-out period (maximum of 100 s). after all nstatus pins are released and pulled high, the microprocessor can try to reconfigure the chai n without needing to pulse nconfig low. if this option is tu rned off, the microprocessor must generate a low-to-high transition (with a low pulse of at least 2 s) on nconfig to restart the configuration process. in your system, you may have multi ple devices that contain the same configuration data. to support this configuration scheme, all device nce inputs are tied to gnd, while nceo pins are left fl oating. all other configuration pins ( nconfig , nstatus , data[7..0] , ncs , cs , nws , nrs and conf_done ) are connected to every device in the chain. configuration signals may require buffering to ensure signal integrity and prevent clock skew pr oblems. ensure that the data lines are buffered for every fourth device. devices must be the same density and package.
7?80 altera corporation stratix ii device handbook, volume 2 january 2008 passive parallel asynchronous configuration all devices start and complete configuration at the same time. figure 7?32 shows multi-device ppa configuration when both devices are receiving the same configuration data. figure 7?32. multiple-device ppa configuration using a microproce ssor when both devices receive the same data notes to figure 7?32 : (1) if not used, the cs pin can be connected to v cc directly. if not used, the ncs pin can be connected to gnd directly. (2) the pull-up resistor should be connected to a supply that provides an acceptable input signal for all devices in the chain. v cc should be high enough to meet the v ih specification of the i/o on th e device and the external host. (3) the nceo pins of both devices are left unconnected when conf iguring the same configuration data into multiple devices. you can use a single configuration chain to configure stratix ii or stratix ii gx devices with other altera devices that support ppa configuration, such as stratix, mercury ? , apex ? 20k, acex ? 1k, and flex ? 10ke devices. to ensure that all devices in the chain complete configuration at the same time or that an error flagged by one device initiates reconfiguration in all devices, all of the device conf_done and nstatus pins must be tied together. f for more information on configuring multiple altera devices in the same configuration chain, refer to the configuring mixed altera fpga chains chapter in volume 2 of the configuration handbook . gnd v cc address decoder addr addr memory data[7..0] ncs (1) cs (1) conf_done nstatus nce nws nrs nconfig rdynbsy ncs (1) cs (1) conf_done nstatus nce nws nrs nconfig rdynbsy microprocessor data[7..0] v cc data[7..0] nceo n.c. (3) nceo (2) (2) dclk v cc (2) dclk (2) v cc stratix ii device stratix ii device 10 k 10 k 10 k 10 k (3) gnd msel3 msel2 msel1 msel0 vcc gnd msel3 msel2 msel1 msel0 vcc gnd
altera corporation 7?81 january 2008 stratix ii device handbook, volume 2 configuring stratix ii and stratix ii gx devices ppa configuration timing figure 7?33 shows the timing waveform for the ppa configuration scheme using a microprocessor. figure 7?33. stratix ii and stratix ii gx ppa c onfiguration timing waveform using nws note (1) notes to figure 7?33 : (1) the beginning of this waveform shows the device in user-mode. in user-mode, nconfig , nstatus and conf_done are at logic high levels. when nconfig is pulled low, a reconfiguration cycle begins. (2) upon power-up, stratix ii and stratix ii gx devices hold nstatus low for the time of the por delay. (3) upon power-up, before and during configuration, conf_done is low. (4) the user can toggle ncs or cs during configuration if the design meets the specification for t cssu , t wsp , and t csh . (5) data[7..0] , cs , ncs , nws , nrs , and rdynbsy are available as user i/o pins after configuration and the state of theses pins depends on the dual-purpose pin settings. byte 0 byte 1 t dh t wsp t cf2ws nconfig nstatus ( 2) conf_done ( 3) data[7..0] (4) cs (4) ncs nws rdynbsy byte n ? 1 byte n t busy t ws2b t rdy2ws t cfg t status user i/os init_done hi g h-z t cf2st0 t cf2cd ( 5) ( 5) ( 5) ( 5) t cf2st1 t dsu t cssu t csh t cd2um (5) user-mode hi g h-z
7?82 altera corporation stratix ii device handbook, volume 2 january 2008 passive parallel asynchronous configuration figure 7?34 shows the timing waveform for the ppa configuration scheme when using a strobed nrs and nws signal. figure 7?34. stratix ii and stratix ii gx ppa confi guration timing waveform using nrs and nws note (1) notes to figure 7?34 : (1) the beginning of this waveform shows the device in user-mode. in user-mode, nconfig , nstatus and conf_done are at logic high levels. when nconfig is pulled low, a reconfiguration cycle begins. (2) upon power-up, stratix ii and stratix ii gx devices hold nstatus low for the time of the por delay. (3) upon power-up, before and during configuration, conf_done is low. (4) the user can toggle ncs or cs during configuration if the design meets the specification for t cssu , t wsp , and t csh . (5) data[7..0] , cs , ncs , nws , nrs , and rdynbsy are available as user i/o pins after configuration and the state of theses pins depends on the dual-purpose pin settings. (6) data7 is a bidirectional pin. it is an in put for configuration data input, but it is an output to show the status of rdynbsy . table 7?18 defines the timing parameters for stratix ii and stratix ii gx devices for ppa configuration. byte 0 byte 1 byte n nconfig (2) nstatus (3) conf_done (4) ncs (4) cs data[7..0] nws nrs init_done user i/o (6) data7/rdynbsy t cssu t cfg t wsp t ws2rs t dh t busy t csh t dsu t cf2ws (5) (5) (5) (5) t cd2um t rs2ws t cf2st1 t cf2scd t status t ws2rs t ws2b t rdy2ws (5) (5) user-mode hi g h-z t rsd7 table 7?18. ppa timing parameters for stratix ii and stratix ii gx devices (part 1 of 2) symbol parameter min max units t cf2cd nconfig low to conf_done low 800 ns t cf2st0 nconfig low to nstatus low 800 ns
altera corporation 7?83 january 2008 stratix ii device handbook, volume 2 configuring stratix ii and stratix ii gx devices f device configuration options and how to create configuration files are discussed further in the software settings chapter in volume 2 the configuration handbook . t cfg nconfig low pulse width 2 s t status nstatus low pulse width 10 100 (1) s t cf2st1 nconfig high to nstatus high 100 (1) s t cssu chip select setup time before rising edge on nws 10 ns t csh chip select hold time after rising edge on nws 0 ns t cf2ws nconfig high to first rising edge on nws 100 s t st2ws nstatus high to first rising edge on nws 2s t dsu data setup time before rising edge on nws 10 ns t dh data hold time after rising edge on nws 0 ns t wsp nws low pulse width 15 ns t ws2b nws rising edge to rdynbsy low 20 ns t busy rdynbsy low pulse width 745ns t rdy2ws rdynbsy rising edge to nws rising edge 15 ns t ws2rs nws rising edge to nrs falling edge 15 ns t rs2ws nrs rising edge to nws rising edge 15 ns t rsd7 nrs falling edge to data7 valid with rdynbsy signal 20 ns t r input rise time 40 ns t f input fall time 40 ns t cd2um conf_done high to user mode (2) 20 100 s t cd2cu conf_done high to clkusr enabled 40 ns t cd2umc conf_done high to user mode with clkusr option on t cd2cu + (299 ? clkusr period) notes to table 7?18 : (1) this value is obtainable if users do not delay configuration by extending the nconfig or nstatus low pulse width. (2) the minimum and maximum numbers apply on ly if the internal oscillator is chos en as the clock source for starting up the device. table 7?18. ppa timing parameters for stratix ii and stratix ii gx devices (part 2 of 2) symbol parameter min max units
7?84 altera corporation stratix ii device handbook, volume 2 january 2008 jtag configuration jtag configuration the jtag has developed a specification for boundary-scan testing. this boundary-scan test (bst) architecture offers the capability to efficiently test components on pcbs with tight lead spacing. the bst architecture can test pin connections without usin g physical test probes and capture functional data while a device is operating normally. the jtag circuitry can also be used to shift configurat ion data into the device. the quartus ii software automatically generates so fs that can be used for jtag configuration with a download cable in the quartus ii software programmer. f for more information on jtag boundary-scan testing, refer to the following documents: ieee 1149.1 (jtag) boundary-scan te sting in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii device handbook or the ieee 1149.1 (jtag) boundary-scan te sting in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook jam programming support - jtag technologies stratix ii and stratix ii gx devices are designed such that jtag instructions have precedence over any device configuration modes. therefore, jtag configuration can ta ke place without waiting for other configuration modes to complete. for example, if you attempt jtag configuration of stratix ii or stratix ii gx devices during ps configuration, ps config uration is terminated and jtag configuration begins. 1 you cannot use the stratix ii and stratix ii gx decompression or design security features if you are configuring your stratix ii or stratix ii gx device when using jtag-based configuration. a device operating in jtag mode uses four required pins, tdi , tdo , tms , and tck , and one optional pin, trst . the tck pin has an internal weak pull-down resistor, while the tdi , tms , and trst pins have weak internal pull-up resistors (typically 25 k ? ). the tdo output pin is powered by v ccio in i/o bank 4. all of the jtag input pins are powered by the 3.3-v v ccpd pin. all user i/o pins ar e tri-stated during jtag configuration. table 7?19 explains each jtag pin?s function. 1 the tdo output is powered by the v ccio power supply of i/o bank 4.
altera corporation 7?85 january 2008 stratix ii device handbook, volume 2 configuring stratix ii and stratix ii gx devices f for recommendations on how to conn ect a jtag chain with multiple voltages across the devices in the chain, refer to the ieee 1149.1 (jtag) boundary-scan testing in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii device handbook or the ieee 1149.1 (jtag) boundary-scan testing in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook . during jtag configuration, data can be downloaded to the device on the pcb through the usb blaster, masterblaster, byteblaster ii, or byteblastermv download cable. configuring devices through a cable is similar to programming devices in-system, except the trst pin should be connected to v cc . this ensures that the tap controller is not reset. figure 7?35 shows jtag configuration of a single stratix ii or stratix ii gx device. table 7?19. dedicated jtag pins pin name pin type description tdi test data input serial input pin for instructions as well as test and programming data. data is shifted in on the rising edge of tck . if the jtag interface is not required on the board, the jtag circuitry can be disa bled by connecting this pin to v cc . tdo test data output serial data output pin for instruct ions as well as test and programming data. data is shifted out on the falling edge of tck . the pin is tri-stated if data is not being shifted out of the device. if the jtag ci rcuitry is not used, leave the tdo pin unconnected. tms test mode select input pin that provides the cont rol signal to determine the transitions of the tap controller state machine. transitions wi thin the state machine occur on the rising edge of tck . therefore, tms must be set up before the rising edge of tck . tms is evaluated on the rising edge of tck . if the jtag interface is not required on the board, the jtag circuitry can be disabled by connecting this pin to v cc . tck test clock input the clock input to the bst circ uitry. some operations occur at the rising edge, while others occur at the falling edge. if t he jtag interface is not required on the board, the jtag circuitry can be disa bled by connecting this pin to gnd. trst test reset input (optional) active-low input to asynchronously reset the boundary-scan circuit. the trst pin is optional according to ieee std. 1149 .1. if the jtag interface is not required on the board, the jtag circuitry can be disabled by connecting this pin to gnd.
7?86 altera corporation stratix ii device handbook, volume 2 january 2008 jtag configuration figure 7?35. jtag configuration of a si ngle device using a download cable notes to figure 7?35 : (1) the pull-up resistor should be connected to the same supply voltage as the usb blaster, masterblaster (v io pin), byteblaster ii, or byteblastermv cable. (2) the nconfig , msel[3..0] pins should be connected to support a non- jtag configuration scheme. if only jtag configuration is used, connect nconfig to v cc , and msel[3..0] to ground. pull dclk either high or low, whichever is convenient on your board. (3) pin 6 of the header is a v io reference voltage for the masterblaster output driver. v io should match the device?s v ccio . refer to the masterblaster serial/usb communications cable user guide for this value. in the byteblastermv cable, this pin is a no connect. in the usb blaster and byteblaster ii cables, this pin is connected to nce when it is used for active serial programmin g, otherwise it is a no connect. (4) nce must be connected to gnd or driven low for successful jtag configuration. to configure a single device in a jt ag chain, the programming software places all other devices in bypass mode. in bypass mode, devices pass programming data from the tdi pin to the tdo pin through a single bypass register without being affected internally. this scheme enables the programming software to program or verify the target device. configuration data driven into the device appears on the tdo pin one clock cycle later. the quartus ii software verifies su ccessful jtag configuration upon completion. at the end of configuratio n, the software checks the state of conf_done through the jtag port. when quartus ii generates a (. jam ) file for a multi-device chain, it contai ns instructions so that all the devices in the chain will be initialized at the same time. if conf_done is not high, the quartus ii software indicates that configuration has failed. if nce (4) msel[3..0] nconfig conf_done vcc (1) vcc gnd vcc gnd vcc (2) (2) vcc (1) 10 k 10 k 10 k 10 k nstatus pin 1 d ownlo ad cab l e 1 0 -pin m a l e h eader (jtag mo de ) (to p vi e w) gnd tck tdo tms tdi 10 k gnd vio (3) (1) (1) stratix ii device nce0 n.c. trst vcc
altera corporation 7?87 january 2008 stratix ii device handbook, volume 2 configuring stratix ii and stratix ii gx devices conf_done is high, the software indicates that configuration was successful. after the configuration bit stream is transmitted serially via the jtag tdi port, the tck port is clocked an ad ditional 299 cycles to perform device initialization. stratix ii and stratix ii gx devices have dedicated jtag pins that always function as jtag pins. not only can you perform jtag testing on stratix ii and stratix ii gx devices before and after, but also during configuration. while other device families do not support jtag testing during configuration, stratix ii and stratix ii gx devices support the bypass, idcode, and sample instructions during configuration without interrupting configuration. all other jtag instructions may only be issued by first interrupting config uration and reprogramming i/o pins using the config_io instruction. the config_io instruction allows i/o buffers to be configured via the jtag port and when issued, interrup ts configuration. this instruction allows you to perform board-level testing prior to configuring the stratix ii or stratix ii gx device or waiting for a configuration device to complete configuration. once conf iguration has been interrupted and jtag testing is complete, the part must be reconfigured via jtag ( pulse_config instruction) or by pulsing nconfig low. the chip-wide reset ( dev_clrn ) and chip-wide output enable ( dev_oe ) pins on stratix ii and stratix ii gx devices do not affect jtag boundary-scan or programming operatio ns. toggling these pins does not affect jtag operations (other than the usual boundary-scan operation). when designing a board for jtag configuration of stratix ii or stratix ii gx devices, consider the dedicated configuration pins. table 7?20 shows how these pins should be connected during jtag configuration. when programming a jtag device chai n, one jtag-compatible header is connected to several devices. the number of devices in the jtag chain is limited only by the drive capability of the download cable. when four or more devices are connected in a jtag chain, altera recommends buffering the tck , tdi , and tms pins with an on-board buffer.
7?88 altera corporation stratix ii device handbook, volume 2 january 2008 jtag configuration table 7?20. dedicated configurati on pin connections during jtag configuration signal description nce on all stratix ii or stratix ii gx devices in the chain, nce should be driven low by connecting it to ground, pulling it low via a resistor, or driving it by some c ontrol circuitry. for devices that are also in multi-device fpp, as, ps, or ppa configuration chains, the nce pins should be connected to gnd during jtag configuration or jtag configured in the same order as the configuration chain. nceo on all stratix ii or stratix ii gx devices in the chain, nceo can be left floating or connected to the nce of the next device. msel these pins must not be left floating. these pins support whichever non-jtag configurati on is used in production. if only jtag configuration is used, tie these pins to ground. nconfig driven high by connecting to v cc , pulling up via a resistor, or driven high by some control circuitry. nstatus pull to v cc via a 10-k ? resistor. when configuring multiple devices in the same jtag chain, each nstatus pin should be pulled up to v cc individually. conf_done pull to v cc via a 10-k ? resistor. when configuring multiple devices in the same jtag chain, each conf_done pin should be pulled up to v cc individually. conf_done going high at the end of jtag configuration indicates successful configuration. dclk should not be left floating. drive low or high, whichever is more convenient on your board.
altera corporation 7?89 january 2008 stratix ii device handbook, volume 2 configuring stratix ii and stratix ii gx devices jtag-chain device programming is ideal when the system contains multiple devices, or when testing your system using jtag bst circuitry. figure 7?36 shows multi-device jtag configuration. figure 7?36. jtag configurat ion of multiple devices using a download cable notes to figure 7?36 : (1) the pull-up resistor should be connected to the same supply voltage as the usb blaster, masterblaster (v io pin), byteblaster ii or byteblastermv cable. (2) the nconfig, msel[3..0] pins should be connected to support a no n-jtag configuration scheme. if only jtag configuration is used, connect nconfig to v cc , and msel[3..0] to ground. pull dclk either high or low, whichever is convenient on your board. (3) pin 6 of the header is a v io reference voltage for the masterblaster output driver. v io should match the device?s v ccio . refer to the masterblaster serial/usb communications cable user guide for this value. in the byteblastermv cable, this pin is a no connect. in the usb blaster and byteblaster ii cables, this pin is connected to nce when it is used for active serial programmin g, otherwise it is a no connect. (4) nce must be connected to gnd or driven low for successful jtag configuration. the nce pin must be connected to gnd or driven low during jtag configuration. in multi-device fpp, as, ps, and ppa configuration chains, the first device?s nce pin is connected to gnd while its nceo pin is connected to nce of the next device in the chain. the last device?s nce input comes from the previous device, while its nceo pin is left floating. in addition, the conf_done and nstatus signals are all shared in multi-device fpp, as, ps, or ppa configuration chains so the devices can enter user mode at the same time af ter configuration is complete. when the conf_done and nstatus signals are shared among all the devices, every device must be configured when jtag configuration is performed. if you only use jtag configuration, altera recommends that you connect the circuitry as shown in figure 7?36 , where each of the conf_done and nstatus signals are isolated, so that ea ch device can enter user mode individually. tms tck d ownlo ad cab l e 1 0 -pin m a l e h eader (jtag mo de ) tdi tdo vcc vcc vcc pin 1 nstatus nconfig msel[3..0] nce (4) vcc conf_done vcc tms tck tdi tdo nstatus nconfig msel0 msel[3..0] nce (4) vcc conf_done vcc tms tck tdi tdo nstatus nconfig msel0 msel[3..0] nce (4) vcc conf_done vcc (1) (2) (2) (2) (2) (2) (2) (2) (2) vio (3) stratix ii device stratix ii device stratix ii device trst trst trst vcc vcc vcc 10 k 10 k (1) (1) 10 k 10 k 10 k 10 k (1) (1) (1) (1) (1) 10 k 1 k 10 k
7?90 altera corporation stratix ii device handbook, volume 2 january 2008 jtag configuration after the first device completes configuration in a multi-device configuration chain, its nceo pin drives low to activate the second device?s nce pin, which prompts the second device to begin configuration. therefore, if these devices are also in a jtag chain, make sure the nce pins are connected to gnd during jtag configuration or that the devices are jtag configured in the same order as the configuration chain. as long as the devices are jtag configured in the same order as the multi-device configuration chain, the nceo of the previous device will drive nce of the next device low when it has successfully been jtag configured. other altera devices that have jtag support can be placed in the same jtag chain for device prog ramming and configuration. 1 stratix, stratix ii, stratix ii gx, cyclone ? , and cyclone ii devices must be within the first 17 devices in a jtag chain. all of these devices have the same jtag controller. if any of the stratix, stratix ii, stratix ii gx, cyclone, and cyclone ii devices are in the 18th or after they will fail configuration. this does not affect signaltap ? ii. f for more information on configuring multiple altera devices in the same configuration chain, refer to the configuring mixed altera fpga chains chapter in the configuration handbook .
altera corporation 7?91 january 2008 stratix ii device handbook, volume 2 configuring stratix ii and stratix ii gx devices figure 7?37 shows jtag configuration of a stratix ii or stratix ii gx device with a microprocessor. figure 7?37. jtag configuration of a si ngle device using a microprocessor notes to figure 7?37 : (1) the pull-up resistor sho uld be connected to a supply that provides an acceptable input signal for all devices in the chain. v cc should be high enough to meet the v ih specification of the i/o on the device. (2) the nconfig , msel[3..0] pins should be connected to support a non-jtag configuration scheme. if only jtag configuration is used, connect nconfig to v cc , and msel[3..0] to ground. pull dclk either high or low, whichever is convenient on your board. (3) nce must be connected to gnd or driven low for successful jtag configuration. jam stapl jam stapl, jedec standard jesd-71, is a standard file format for in-system programmability (isp ) purposes. jam stapl supports programming or configuration of programmable devices and testing of electronic systems, usin g the ieee 1149.1 jtag in terface. jam stapl is a freely licensed open standard. the jam player provides an interfac e for manipulating the ieee std. 1149.1 jtag tap state machine. f for more information on jtag and jam stapl in embedded environments, refer to an 122: using jam stap l for isp & icr via an embedded processor . to download the jam player, visit the altera web site at www.altera.com . trst tdi tck tms tdo microprocessor memory addr data stratix ii device nstatus conf_done v cc v cc 1 k 1 k (1) (1) (3) nce nconfig n.c. gnd (2) (2) v cc nceo msel[3..0]
7?92 altera corporation stratix ii device handbook, volume 2 january 2008 device configuration pins device configuration pins the following tables describe the conne ctions and functionality of all the configuration related pins on the stratix ii and stratix ii gx devices. table 7?21 summarizes the stratix ii pin configuration. table 7?21. stratix ii configurat ion pin summary (part 1 of 2) note (1) bank description input/output dedica ted powered by configuration mode 3 pgm[2..0] output (2) ps, fpp, ppa, ru, lu 3 asdo output (2) as 3 ncso output (2) as 3 crc_error output (2) optional, all modes 3 data0 input (3) all modes except jtag 3 data[7..1] input (3) fpp, ppa 3 data7 bidirectional (2) , (3) ppa 3 rdynbsy output (2) ppa 3 init_done output pull-up optional, all modes 3 nstatus bidirectional yes pull-up all modes 3 nce input yes (3) all modes 3 dclk input yes (3) ps, fpp output (2) as 3 conf_done bidirectional yes pull-up all modes 8 tdi input yes vccpd jtag 8 tms input yes vccpd jtag 8 tck input yes vccpd jtag 8 trst input yes vccpd jtag 8 nconfig input yes (3) all modes 8 vccsel input yes vccint all modes 8 cs input (3) ppa 8 clkusr input (3) optional 8 nws input (3) ppa 8 nrs input (3) ppa 8 runlu input (3) ps, fpp, ppa, ru, lu 8 ncs input (3) ppa 7 porsel input yes vccint all modes 7 nio_pullup input yes vccint all modes
altera corporation 7?93 january 2008 stratix ii device handbook, volume 2 configuring stratix ii and stratix ii gx devices figure 7?38 shows the i/o bank locations. figure 7?38. stratix ii i/o bank numbers 7 pll_ena input yes (3) optional 7 nceo output yes (2) , (4) all modes 4 msel[3..0] input yes vccint all modes 4 tdo output yes (2) , (4) jtag notes to table 7?21 : (1) total number of pins is 41, tota l number of dedicated pins is 19. (2) all outputs are powered by vccio except as noted. (3) all inputs are powered by vccio or vccpd , based on the vccsel setting, except as noted. (4) an external pull-up resistor may be required for this conf iguration pin because of the multivolt i/o interface. refer to the stratix ii architecture chapter in volume 1 of the stratix ii device handbook for pull-up or level shifter recommendations for nceo and tdo . table 7?21. stratix ii configurat ion pin summary (part 2 of 2) note (1) bank description input/output dedica ted powered by configuration mode bank 2 bank 5 bank 1 bank 6 bank 3 bank 4 bank 8 bank 7 stratix ii device i/o bank numbers
7?94 altera corporation stratix ii device handbook, volume 2 january 2008 device configuration pins table 7?22 describes the dedicated configuration pins, which are required to be connected properly on your board for successful configuration. some of these pins may not be requ ired for your configuration schemes. table 7?22. dedicated configurati on pins on the stratix ii and stratix ii gx device (part 1 of 10) pin name user mode configuration scheme pin type description v ccpd n/a all power dedicated power pin. this pin is used to power the i/o pre-drivers, the jtag input pins, and the configuration input pins that are affected by the voltage level of vccsel . this pin must be connected to 3.3-v. v ccpd must ramp-up from 0-v to 3.3-v within 100 ms. if v ccpd is not ramped up within this specified time, your stratix ii or stratix ii gx device will not configure successfu lly. if your system does not allow for a v ccpd ramp-up time of 100 ms or less, you must hold nconfig low until all power supplies are stable. vccsel n/a all input dedicated input that selects which input buffer is used on the pll_ena pin and the configuration input pins; nconfig , dclk (when used as an input), nstatus (when used as an input), conf_done (when used as an input), dev_oe , dev_clrn , data[7..0] , runlu , nce , nws , nrs , cs , ncs , and clkusr . the 3.3-v/2.5-v input buffer is powered by v ccpd , while the 1.8- v/1.5-v input buffer is powered by v ccio . the vccsel input buffer has an internal 5-k ?? pull-down resistor that is always active. the vccsel input buffer is powered by v ccint and must be hardwired to v ccpd or ground. a logic high selects the 1.8-v/1.5-v input buffer, and a logic low selects the 3.3-v/2.5-v input buffer. for more information, refer to the ?vccsel pin? section.
altera corporation 7?95 january 2008 stratix ii device handbook, volume 2 configuring stratix ii and stratix ii gx devices porsel n/a all input dedicated input which selects between a por time of 12 ms or 100 ms. a logic high (1.5 v, 1.8 v, 2.5 v, 3.3 v) selects a por time of about 12 ms and a logic low selects por time of about 100 ms. the porsel input buffer is powered by v ccint and has an internal 5-k ?? pull-down resistor that is always active. the porsel pin should be tied directly to v ccpd or gnd. nio_pullup n/a all input dedicated input that chooses whether the internal pull-up resistors on the user i/o pins and dual-purpose i/o pins ( ncso , nasdo , data[7..0] , nws , nrs , rdynbsy , ncs , cs , runlu , pgm[] , clkusr , init_done , dev_oe , dev_clr ) are on or off before and during configuration. a logic high (1.5 v, 1.8 v, 2.5 v, 3.3 v) turns off the weak internal pull-up resistors, while a logic low turns them on. the nio-pullup input buffer is powered by v ccpd and has an internal 5-k ?? pull-down resistor that is always active. the nio-pullup can be tied directly to v ccpd or use a 1-k ?? pull-up resistor or tied directly to gnd. msel[3..0] n/a all input 4-bit configuration input that sets the stratix ii and stratix ii gx device configuration scheme. refer to table 7?1 for the appropriate connections. these pins must be hard-wired to v ccpd or gnd. the msel[3..0] pins have internal 5-k ?? pull-down resistors that are always active. table 7?22. dedicated configurati on pins on the stratix ii and stratix ii gx device (part 2 of 10) pin name user mode configuration scheme pin type description
7?96 altera corporation stratix ii device handbook, volume 2 january 2008 device configuration pins nconfig n/a all input configuration control input. pulling this pin low during user-mode will cause the device to lose its configuration data, enter a reset state, tri-state all i/o pins. returning this pin to a logic high level will initiate a reconfiguration. if your configuration scheme uses an enhanced configuration device or epc2 device, nconfig can be tied directly to v cc or to the configuration device?s ninit_conf pin. nstatus n/a all bidirectional open-drain the device drives nstatus low immediately after power-up and releases it after the por time. status output. if an error occurs during configuration, nstatus is pulled low by the target device. status input. if an external source drives the nstatus pin low during configuration or initialization, the target device enters an error state. driving nstatus low after configuration and initialization does not affect the configured device. if a configuration device is used, driving nstatus low will cause the configuration device to attempt to configure the device, but since the device ignores transitions on nstatus in user-mode, the device does not reconfigure. to initiate a reconfiguration, nconfig must be pulled low. the enhanced configuration devices? and epc2 devices? oe and ncs pins have optional internal programmable pull-up resistors. if internal pull-up resistors on the enhanced configuration device are used, external 10-k ? pull-up resistors should not be used on these pins. when using epc2 devices, only external 10-k ? pull-up resistors should be used. table 7?22. dedicated configurati on pins on the stratix ii and stratix ii gx device (part 3 of 10) pin name user mode configuration scheme pin type description
altera corporation 7?97 january 2008 stratix ii device handbook, volume 2 configuring stratix ii and stratix ii gx devices nstatus (continued) if vccpd and vccio are not fully powered up, the following could occur: vccpd and vccio are powered high enough for the nstatus buffer to function properly, and nstatus is driven low. when vccpd and vccio are ramped up, por trips, and nstatus is released after por expires. vccpd and vccio are not powered high enough for the nstatus buffer to function properly. in this situation, nstatus might appear logic high, triggering a configuration attempt that would fail because por did not yet trip. when vccpd and vccio are powered up, nstatus is pulled low because por did not yet trip. when por trips after vccpd and vccio are powered up, nstatus is released and pulled high. at that point, reconfiguration is triggered and the device is configured. table 7?22. dedicated configurati on pins on the stratix ii and stratix ii gx device (part 4 of 10) pin name user mode configuration scheme pin type description
7?98 altera corporation stratix ii device handbook, volume 2 january 2008 device configuration pins conf_done n/a all bidirectional open-drain status output. the target device drives the conf_done pin low before and during configuration. once al l configuration data is received without error and the initialization cycle starts, the target device releases conf_done . status input. after all data is received and conf_done goes high, the target device initializes and enters user mode. the conf_done pin must have an external 10-k ? pull-up resistor in order for the device to initialize. driving conf_done low after configuration and initialization does not affect the configured device. the enhanced configuration devices? and epc2 devices? oe and ncs pins have optional internal programmable pull-up resistors. if internal pull-up resistors on the enhanced configuration device are used, external 10-k ? pull-up resistors should not be used on these pins. when using epc2 devices, only external 10-k ? pull-up resistors should be used. nce n/a all input active-low chip enable. the nce pin activates the device with a low signal to allow configuration. the nce pin must be held low during configuration, initialization, and user mode. in single device configuration, it should be tied low. in multi-device configuration, nce of the first device is tied low while its nceo pin is connected to nce of the next device in the chain. the nce pin must also be held low for successful jtag programming of the device. table 7?22. dedicated configurati on pins on the stratix ii and stratix ii gx device (part 5 of 10) pin name user mode configuration scheme pin type description
altera corporation 7?99 january 2008 stratix ii device handbook, volume 2 configuring stratix ii and stratix ii gx devices nceo n/a all output output that drives low when device configuration is complete. in single device configuration, this pin is left floating. in multi-device configuration, this pin feeds the next device?s nce pin. the nceo of the last device in the chain is left floating. the nceo pin is powered by v ccio in i/o bank 7. for recommendations on how to connect nceo in a chain with multiple voltages across the devices in the chain, refer to the stratix ii architecture chapter in volume 1 of the stratix ii handbook or the stratix ii gx architecture chapter in volume 1 of the stratix ii gx device handbook . asdo n/a in as mode i/o in non-as mode as output control signal from the stratix ii or stratix ii gx device to the serial configuration device in as mode used to read out configuration data. in as mode, asdo has an internal pull-up resistor that is always active. ncso n/a in as mode i/o in non-as mode as output output control signal from the stratix ii or stratix ii gx device to the serial configuration device in as mode that enables the configuration device. in as mode, ncso has an internal pull-up resistor that is always active. table 7?22. dedicated configurati on pins on the stratix ii and stratix ii gx device (part 6 of 10) pin name user mode configuration scheme pin type description
7?100 altera corporation stratix ii device handbook, volume 2 january 2008 device configuration pins dclk n/a synchronous configuration schemes (ps, fpp, as) input (ps, fpp) output (as) in ps and fpp configuration, dclk is the clock input used to clock data from an external source into the target device. data is latched into the device on the rising edge of dclk . in as mode, dclk is an output from the stratix ii or stratix ii gx device that provides timing for the configuration interface. in as mode, dclk has an internal pull-up resistor (typically 25 k ? ) that is always active. in ppa mode, dclk should be tied high to v cc to prevent this pin from floating. after configuration, this pin is tri-stated. in schemes that use a configuration device, dclk will be driven low after configuration is done. in schemes that use a control host, dclk should be driven either high or low, whichever is more convenient. toggling this pin after configuration does not affect the configured device. data0 i/o ps, fpp, ppa, as input data input. in serial configuration modes, bit-wide configuration data is presented to the target device on the data0 pin. the v ih and v il levels for this pin are dependent on the input buffer selected by the vccsel pin. refer to the section ?vccsel pin? on page 7?10 for more information. in as mode, data0 has an internal pull-up resistor that is always active. after configuration, data0 is available as a user i/o pin and the state of this pin depends on the dual-purpose pin settings. after configuration, epc1 and epc1441 devices tri-state this pin, while enhanced configuration and epc2 devices drive this pin high. table 7?22. dedicated configurati on pins on the stratix ii and stratix ii gx device (part 7 of 10) pin name user mode configuration scheme pin type description
altera corporation 7?101 january 2008 stratix ii device handbook, volume 2 configuring stratix ii and stratix ii gx devices data[7..1] i/o parallel configuration schemes (fpp and ppa) inputs data inputs. byte-wide configuration data is presented to the target device on data[7..0] . the v ih and v il levels for this pin are dependent on the input buffer selected by the vccsel pin. refer to the section ?vccsel pin? on page 7?10 for more information. in serial configuration schemes, they function as user i/o pins during configuration, which means they are tri-stated. after ppa or fpp configuration, data[7..1] are available as user i/o pins and the state of these pin depends on the dual-purpose pin settings. data7 i/o ppa bidirectional in the ppa configuration scheme, the data7 pin presents the rdynbsy signal after the nrs signal has been strobed low. the v ih and v il levels for this pin are dependent on the input buffer selected by the vccsel pin. refer to the section ?vccsel pin? on page 7?10 for more information. in serial configuration schemes, it functions as a user i/o pin during configuration, which means it is tri-stated. after ppa configuration, data7 is available as a user i/o and the state of this pin depends on the dual-purpose pin settings. nws i/o ppa input write strobe input. a low-to-high transition causes the device to latch a byte of data on the data[7..0] pins. in non-ppa schemes, it functions as a user i/o pin during configuration, which means it is tri-stated. after ppa configuration, nws is available as a user i/o pins and the state of this pin depends on the dual-purpose pin settings. table 7?22. dedicated configurati on pins on the stratix ii and stratix ii gx device (part 8 of 10) pin name user mode configuration scheme pin type description
7?102 altera corporation stratix ii device handbook, volume 2 january 2008 device configuration pins nrs i/o ppa input read strobe input. a low input directs the device to drive the rdynbsy signal on the data7 pin. if the nrs pin is not used in ppa mode, it should be tied high. in non-ppa schemes, it functions as a user i/o during configuration, which means it is tri-stated. after ppa configuration, nrs is available as a user i/o pin and the state of this pin depends on the dual-purpose pin settings. rdynbsy i/o ppa output ready output. a high output indicates that the target device is ready to accept another data byte. a low output indicates that the target device is busy and not ready to receive another data byte. in ppa configuration schemes, this pin will drive out high after power-up, before configuration and after configuration before entering user-mode. in non-ppa schemes, it functions as a user i/o pin during configuration, which means it is tri-stated. after ppa configuration, rdynbsy is available as a user i/o pin and the state of this pin depends on the dual-purpose pin settings. table 7?22. dedicated configurati on pins on the stratix ii and stratix ii gx device (part 9 of 10) pin name user mode configuration scheme pin type description
altera corporation 7?103 january 2008 stratix ii device handbook, volume 2 configuring stratix ii and stratix ii gx devices ncs/cs i/o ppa input chip-select inputs. a low on ncs and a high on cs select the target device for configuration. the ncs and cs pins must be held active during configuration and initialization. during the ppa configuration mode, it is only required to use either the ncs or cs pin. therefore, if only one ch ip-select input is used, the other must be tied to the active state. for example, ncs can be tied to ground while cs is toggled to control configuration. in non-ppa schemes, it functions as a user i/o pin during configuration, which means it is tri-stated. after ppa configuration, ncs and cs are available as user i/o pins and the state of these pins depends on the dual-purpose pin settings. runlu n/a if using remote system upgrade i/o if not remote system upgrade in fpp, ps or ppa input input that selects between remote update and local update. a logic high (1.5-v, 1.8-v, 2.5-v, 3.3-v) selects remote update and a logic low selects local update. when not using remote update or local update configuration modes, this pin is available as general-purpose user i/o pin. pgm[2..0] n/a if using remote system upgrade i/o if not using remote system upgrade in fpp, ps or ppa output these output pins select one of eight pages in the memory (either flash or enhanced configuration device) when using a remote system upgrade mode. when not using remote update or local update configuration modes, these pins are available as general-purpose user i/o pins. table 7?22. dedicated configuration pins on the stratix ii and stratix ii gx device (part 10 of 10) pin name user mode configuration scheme pin type description
7?104 altera corporation stratix ii device handbook, volume 2 january 2008 device configuration pins table 7?23 describes the optional configuration pins. if these optional configuration pins are not enabled in the quartus ii software, they are available as general-purpose user i/o pins. therefore, during configuration, these pins function as user i/o pins and are tri-stated with weak pull-up resistors. table 7?23. optional configuration pins pin name user mode pi n type description clkusr n/a if option is on. i/o if option is off. input optional user-supplied cl ock input synchronizes the initialization of one or more devices. this pin is enabled by turning on the enable user-supplied start-up clock ( clkusr ) option in the quartus ii software. init_done n/a if option is on. i/o if option is off. output open-drain status pin can be used to indicate when the device has initialized and is in user mode. when nconfig is low and during the beginning of configuration, the init_done pin is tri-stated and pulled high due to an external 10-k ? pull-up resistor. once the option bit to enable init_done is programmed into the device (during the first frame of configuration data), the init_done pin will go low. when initialization is complete, the init_done pin will be released and pulled high and the device enters user mode. thus, the monitoring circuitry must be able to detect a low-to-high transition. this pin is enabled by turning on the enable init_done output option in the quartus ii software. dev_oe n/a if option is on. i/o if option is off. input optional pin that allows the user to override all tri-states on the device. when this pin is driven low, all i/o pins are tri-stated; when this pin is driven high, all i/o pins behave as programmed. this pin is enabled by turning on the enable device-wide output enable ( dev_oe ) option in the quartus ii software. dev_clrn n/a if option is on. i/o if option is off. input optional pin that allows you to override all clears on all device registers. when this pin is driven low, all registers are cleared; when th is pin is driven high, all registers behave as progra mmed. this pin is enabled by turning on the enable device-wide reset ( dev_clrn ) option in the quartus ii software.
altera corporation 7?105 january 2008 stratix ii device handbook, volume 2 configuring stratix ii and stratix ii gx devices table 7?24 describes the dedicated jtag pins. jtag pins must be kept stable before and during configuratio n to prevent accidental loading of jtag instructions. the tdi , tms, and trst have weak internal pull-up resistors (typically 25 k ? ) while tck has a weak internal pull-down resistor. if you plan to use the signaltap embedded logic array analyzer, you need to connect the jtag pins of the stratix ii or stratix ii gx device to a jtag header on your board. table 7?24. dedicated jtag pins (part 1 of 2) pin name user mode pin type description tdi n/a input serial input pin for instructions as well as test and programming data. data is shifted in on the rising edge of tck . the tdi pin is powered by the 3.3-v v ccpd supply. if the jtag interface is not required on the board, the jtag circuitry can be disabled by connecting this pin to v cc . tdo n/a output serial data output pin for instructions as well as test and programming data. data is shifted out on the falling edge of tck . the pin is tri-stated if data is not being shifted out of the device. the tdo pin is powered by v ccio in i/o bank 4. for recommendations on connecting a jtag chain with multiple voltages across the devices in the chain, refer to the ieee 1149.1 (jtag) boundary scan testing in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii handbook or the ieee 1149.1 (jtag) boundary scan testing in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook . if the jtag circuitry is not us ed, leave the tdo pin unconnected. tms n/a input input pin that provides the control signal to determine the transitions of the tap controller state machine. transiti ons within the state machine occur on the rising edge of tck . therefore, tms must be set up before the rising edge of tck . tms is evaluated on the rising edge of tck . the tms pin is powered by the 3.3-v v ccpd supply. if the jtag interface is not required on the board, the jtag circuitry can be disabled by connecting this pin to v cc .
7?106 altera corporation stratix ii device handbook, volume 2 january 2008 conclusion conclusion stratix ii and stratix ii gx devices can be configured in a number of different schemes to fit your system?s need. in additi on, configuration bitstream encryption, configuration data decompression, and remote system upgrade support supplement the stratix ii and stratix ii gx configuration solution. referenced documents this chapter references the following documents: an 122: using jam stapl for isp & icr via an embedded processor an 418: srunner: an embedded solution for serial conf iguration device programming byteblaster ii download cable user guide byteblastermv download cable user guide configuration devices for sram-b ased lut devices data sheet chapter in volume 2 of the configuration handbook . configuring mixed altera fpga chains in volume 2 of the configuration handbook dc & switching characteristics chapter in volume 1 of the stratix ii device handbook dc & switching characteristics chapter in volume 1 of the stratix ii gx device handbook enhanced configuration devices (e pc4, epc8 & epc16) data sheet in volume 2 of the configuration handbook ieee 1149.1 (jtag) boundary-scan te sting in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii device handbook ieee 1149.1 (jtag) boundary-scan te sting in stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook jam programming support - jtag technologies masterblaster serial /usb communications cable user guide tck n/a input the clock input to the bst circuitr y. some operations occur at the rising edge, while others occur at the falling edge. the tck pin is powered by the 3.3-v v ccpd supply. if the jtag interface is not required on the board, the jtag circuitry can be disabled by connecting tck to gnd. trst n/a input active-low input to asynchronous ly reset the boundary-scan circuit. the trst pin is optional according to ieee std. 1149.1. the trst pin is powered by the 3.3-v v ccpd supply. if the jtag interface is not required on the board, the jtag circuitry can be disabled by connecting the trst pin to gnd. table 7?24. dedicated jtag pins (part 2 of 2) pin name user mode pin type description
altera corporation 7?107 january 2008 stratix ii device handbook, volume 2 configuring stratix ii and stratix ii gx devices remote system upgrades with st ratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii device handbook remote system upgrades with st ratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook . usb-blaster download cable user guide serial configuration devices (epc s1, epcs4, epcs16, epcs64, and epcs128) data sheet chapter in volume 2 of the configuration handbook . software settings in volume 2 of the configuration handbook stratix ii gx architecture chapter in volume 1 of the stratix ii gx device handbook stratix ii device handbook stratix ii gx device handbook document revision history table 7?25 shows the revision history for this chapter. table 7?25. document revision history (part 1 of 2) date and document version changes made summary of changes january 2008, v4.5 updated runlu and pgm[2..0] information in ta b l e 7 ? 2 2 . ? updated handnote in ?configuration data decompression? section. updated notes in: table 7?3 table 7?10 table 7?12 table 7?15 table 7?18 ? updated tdo row for tables 7?19 and 7?24 .? added the ?referenced documents? section. ? minor text edits. ? no change for the stratix ii gx device handbook only: formerly chapter 12. the chapter number changed due to the addition of the stratix ii gx dynamic reconfiguration chapter. no content change. ?
7?108 altera corporation stratix ii device handbook, volume 2 january 2008 document revision history may 2007, v4.4 updated ?power-on reset circuit? section updated ?vccsel pin? section updated ?configuration data decompression? section updated ?active serial configuration (serial configuration devices)? section updated ?output configuration pins? section ? added notes to ?fpp configuration using a max ii device as an external host? and ?passive parallel asynchronous configuration? section. ? updated table 13?5 updated table 13?6 updated table 13?8 updated table 13?11 ? removed table 7-7. ? added new ?output configuration pins? section. ? corrected typo in ?configuration devices? section. ? corrected conf_done in table 13?22. ? february 2007 v4.3 added the ?document revision history? section to this chapter. ? april 2006, v4.2 chapter updated as part of the stratix ii device handbook update. ? no change formerly chapter 11. chapter number change only due to chapter addition to section i in february 2006; no content change. ? december 2005, v4.1 chapter updated as part of the stratix ii device handbook update. ? october 2005 v4.0 added chapter to the stratix ii gx device handbook . ? table 7?25. document revision history (part 2 of 2) date and document version changes made summary of changes
altera corporation 8?1 january 2008 8. remote system upgrades with stratix ii and stratix ii gx devices introduction system designers today face difficult challenges such as shortened design cycles, evolving standards, and system deployments in remote locations. stratix ? ii and stratix ii gx fpgas help overcome these challenges with their inherent re-programmability and dedicated circuitry to perform remote system upgrades. remote syst em upgrades help deliver feature enhancements and bug fixes without costly recalls, reduce time-to- market, and extend product life. stratix ii and stratix ii gx fpgas feature dedicated remote system upgrade circuitry. soft logic (either the nios ? embedded processor or user logic) implemented in a stratix ii or stratix ii gx device can download a new configuration image from a remote location, store it in configuration memory, and direct the dedicated remote system upgrade circuitry to initiate a reconfiguration cycle. the dedicated circuitry performs error detection during and after the configuration process, recovers from any error condition by reverting back to a safe configuration image, and provides error status information. this dedicated remote system upgrade circuitry is unique to stratix, strati x ii, and stratix ii gx fpgas and helps to avoid system downtime. remote system upgrade is supported in all stratix ii and stratix ii gx configuration schemes: fast passive parallel (fpp), active serial (as), passive serial (ps), and passive parallel asynchronous (ppa). remote system upgrade can also be implemen ted in conjunction with advanced stratix ii and stratix ii gx features such as real-time decompression of configuration data and design securi ty using the advanced encryption standard (aes) for secure an d efficient field upgrades. this chapter describes the function ality and implementation of the dedicated remote system upgrade circuitry. it also defines several concepts related to remote syst em upgrade, including factory configuration, application configuration, remote update mode, local update mode, the user watchdog ti mer, and page mode operation. additionally, this chapter provides design guidelines for implementing remote system upgrade with the various supported configuration schemes. sii52008-4.5
8?2 altera corporation stratix ii device handbook, volume 2 january 2008 functional description functional description the dedicated remote system upgrade circuitry in stratix ii and stratix ii gx fpgas manages remote configuration and provides error detection, recovery, and status informat ion. user logic or a nios processor implemented in the fpga logic arra y provides access to the remote configuration data source and an interface to the system?s configuration memory. stratix ii and stratix ii gx fpga?s remote system upgrade process involves the following steps: 1. a nios processor (or user logic) implemented in the fpga logic array receives new configuration data from a remote location. the connection to the remote source is a communication protocol such as the transmission control pro tocol/internet protocol (tcp/ip), peripheral component interconnect (pci), user datagram protocol (udp), universal asyn chronous receiver/tran smitter (uart), or a proprietary interface. 2. the nios processor (or user logic) stores this new configuration data in non-volatile configuratio n memory. the non-volatile configuration memory can be any standard flash memory used in conjunction with an intellig ent host (for example, a max ? device or microprocessor), the serial config uration device, or the enhanced configuration device. 3. the nios processor (or user logic) initiates a reconfiguration cycle with the new or updated configuration data. 4. the dedicated remote system upgr ade circuitry detects and recovers from any error(s) that might occur during or after the reconfiguration cycle, and provides error status information to the user design.
altera corporation 8?3 january 2008 stratix ii device handbook, volume 2 remote system upgrades with stratix ii and stratix ii gx devices figure 8?1 shows the steps required for pe rforming remote configuration updates. (the numbers in the figure be low coincide with the steps above.) figure 8?1. functional diagram of stratix ii or stratix ii gx remote system upgrade stratix ii and stratix ii gx fpgas support remote system upgrade in the fpp, as, ps, and ppa configuration schemes. serial configuration devices use the as scheme to configure stratix ii and stratix ii gx fpgas. a max ii device (or microprocessor and flash configuration schemes) uses fpp, ps, or ppa sc hemes to configure stratix ii and stratix ii gx fpgas. enhanced configuration devices use the fpp or ps configuration schemes to configure stratix ii and stratix ii gx fpgas. 1 the jtag-based configuration scheme does not support remote system upgrade. development location memory stratix ii/stratix ii gx device confi g uration stratix ii/stratix ii gx device control module data data data confi g uration 1 2 3
8?4 altera corporation stratix ii device handbook, volume 2 january 2008 functional description figure 8?2 shows the block diagrams for implementing remote system upgrade with the various stratix ii and stratix ii gx configuration schemes. figure 8?2. remote system upgrade block diagrams for various stratix ii and stratix ii gs configuration schemes 1 for the active serial configuration scheme, the remote system upgrade only supports single device configurations. you must set the mode select pins ( msel[3..0] ) and the runlu pin to select the configuration scheme and remote system upgrade mode best suited for your system. table 8?1 lists the pin setting s for stratix ii and stratix ii gx fpgas. standard config uration mode refers to normal fpga configuration mode with no support for remote system upgrades, and the remote system upgrade circuitry is disabled. the following sections describe the local update and rem ote update remote system upgrade modes. stratix ii/stratix ii gx device processor flash memory stratix ii device enhanced configuration device enhanced confi g uration device max ii device & flash memory max ii device flash memory stratix ii/stratix ii gx device stratix ii/stratix ii gx device serial configuration device serial confi g uration device or user lo g ic nios processor or user lo g ic nios processor or user lo g ic nios processor external processor & flash memory
altera corporation 8?5 january 2008 stratix ii device handbook, volume 2 remote system upgrades with stratix ii and stratix ii gx devices f for more information on standard configuration schemes supported in stratix ii and stratix ii gx fpgas, see the configuring stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii handbook and the configuring stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx handbook . configuration image types and pages when using remote system upgrade, fpga configuration bitstreams are classified as factory configuration images or application configuration images. an image, also referred to as a configuration, is a design loaded into the fpga that performs certain user-defined functi ons. each fpga in your system requires one factor y image and one or more application table 8?1. stratix ii and st ratix ii gx remote system upgrade modes configuration schem e msel[3..0] runlu remote system upgrade mode fpp 0000 - standard 0100 (1) 0 local update 0100 (1) 1 remote update fpp with decompression and/or design security feature enabled (2) 1011 - standard 1100 (1) 0 local update 1100 (1) 1 remote update fast as (40 mhz) (3) 1000 - standard 1001 1 remote update as (20 mhz) (3) 1101 - standard 1110 1 remote update ps 0010 - standard 0110 (1) 0 local update 0110 (1) 1 remote update ppa 0001 - standard 0101 (1) 0 local update 0101 (1) 1 remote update notes to ta b l e 8 ? 1 : (1) these schemes require that you drive the runlu pin to specify either remote update or local update mode. as schemes only support the remote update mode. (2) these modes are only supported when using a max ii de vice or microprocessor and flash for configuration. in these modes, the host system must output a dclk that is 4 x the data rate. (3) the epcs16 and epcs64 serial configuration devices su pport a dclk up to 40 mhz; other epcs devices support a dclk up to 20 mhz. see the serial configuration devices (epcs1, epcs4, epcs16, epcs64, and epcs128) data sheet in volume 2 of the configuration handbook for more information.
8?6 altera corporation stratix ii device handbook, volume 2 january 2008 functional description images. the factory im age is a user-defined fall-back, or safe, configuration and is responsible for administering remote updates in conjunction with the dedicated circuitry. application images implement user-defined functionality in the target fpga. a remote system update involves storing a new application configuration image or updating an existing one via the remote communication interface. after an application configuration image is stored or updated remotely, the user design in the fpga initiates a reconfiguration cycle with the new image. any errors during or after this cycle are detected by the dedicated remote system upgrad e circuitry and cause the fpga to automatically revert to the factor y image. the factory image then performs error processing and re covery. while error processing functionality is limited to the factor y configuration, both factory and application configurations can download and store remote updates and initiate system reconfiguration. stratix ii and stratix ii gx fpgas select between the different configuration images stored in the system configuration memory using the page address pins or start address registers. a page is a section of the configuration memory space that co ntains one configuration image for each fpga in the system . one page stores one system configuration, regardless of the number of fpgas in the system. page address pins select the configuration image within an enhanced configuration device or flash memory (max ii device or microprocessor setup). page start address regist ers are used when stratix ii and stratix ii gx fpgas are configured in as mode with serial configuration devices. figure 8?3 illustrates page mode operation in stratix ii and stratix ii gx fpgas.
altera corporation 8?7 january 2008 stratix ii device handbook, volume 2 remote system upgrades with stratix ii and stratix ii gx devices figure 8?3. page mode operation in st ratix ii & strati x ii gx fpgas stratix ii and stratix ii gx devices drive out three page address pins, pgm[2..0] , to the max ii device or microprocessor or enhanced configuration device. these page pins select between eight configuration pages. page zero ( pgm[2..0] = 000 ) must contain the factory configuration, and the other seven pa ges are application configurations. the pgm[] pins are pointers to the start address and length of each page, and the max ii device, microprocess or, and enhanced configuration devices perform this translation. 1 when implementing remote system upgrade with an intelligent-host-based configuration, your max ii device or microprocessor should emulate the page mode feature supported by the enhanced configuration device, which translates pgm pointers to a memory address in the configuration memory. your max ii device or microprocessor must provide a similar translation feature. f for more information about the enha nced configuration device page mode feature, refer to the dyna mic configuration (page mode) implementation section of the enhanced configuration devices (epc4, epc8 & epc16) data sheet chapter in volume 2 of the configuration handbook . when implementing remote system upgrade with as configuration, a dedicated 7-bit page start address register inside stratix ii and stratix ii gx fpgas determines the start addresses for configuration pages within the serial configuration device. the pgm[6..0] registers form bits [22..16] of the 24-bit start address while the other 17 bits are confi g uration memory sof n pa g e n sof 0 pa g e 0 stratix ii/ stratix ii gx device data[ ] p age s e l ect pin s o r s tart a ddress r eg i ster pgm[ ] c on f i g u rat ion data
8?8 altera corporation stratix ii device handbook, volume 2 january 2008 remote system upgrade modes set to zero: stadd[23..0] = {1'b0, pgm[6..0], 16'b0} . during as configuration, stratix ii and strati x ii gx fpgas use this 24-bit page start address to obtain configuration data from the serial configuration devices. remote system upgrade modes remote system upgrade has two mode s of operation: remote update mode and local update mode. the remote and local update modes allow you to determine the functionality of your system upon power up and offer different features. the runlu input pin selects between the remote update (logic high) and local update (logic low) modes. overview in remote update mode, stratix ii and stratix ii gx fpgas load the factory configuration image upon po wer up. the user-defined factory configuration should determine which application configuration is to be loaded and trigger a reconfiguration cycle. remote update mode allows up to eight configuration images (o ne factory plus seven application images) when used with the max i i device or microprocessor and flash-based configuration or an enhanced configuration device. when used with serial configuration devices, the remote update mode allows an application co nfiguration to start at any flash sector boundary. this translates to a maximum of 128 pages in the epcs64 and 32 pages in the epcs16 device, where the minimum size of each page is 512 kbits. additionally, the remote update mode features a user watchdog timer that can detect functional errors in an application configuration. local update mode is a simplified version of the remote update mode. in this mode, stratix ii and stratix ii gx fpgas directly load the application configuration, bypassing the factory conf iguration. this mode is useful if your system is required to boot into user mode with minimal startup time. it is also useful du ring system prototyping, as it allows you to verify functionality of the appl ication configuration. in local update mode, a maximum of two configuration images or pages is supported: one factory configur ation, located at page address pgm[2..0] = 000 , and one application config uration, located at page address pgm[2..0] = 001 . because the page address of the application configuration is fixed, the local update mode does not require the factory configuration image to determine which application is to be loaded. if any errors are encountered while load ing the application configuration, stratix ii and stratix ii gx fpgas revert to the factory configuration. the user watchdog timer feature is not supported in this mode.
altera corporation 8?9 january 2008 stratix ii device handbook, volume 2 remote system upgrades with stratix ii and stratix ii gx devices 1 also, local update mode does not support as configuration with the serial configuration devices because these devices don?t support a dynamic pointer to pa ge 001 start address location. table 8?2 details the differences between remote and local update modes. remote update mode when stratix ii and stratix ii gx fp gas are first powered up in remote update mode, it loads the factory configuration located at page zero (page address pins pgm[2..0] = "000" ; page registers pgm[6..0] = "0000000" ). you should always store the factory configuration image for your system at page address zero. a factory configuration image is a bitstream for the fpga(s) in your sy stem that is pr ogrammed during production and is the fall-back image when errors occur. this image is stored in non-volatile memory and is never updated or modified using table 8?2. differences between remote and local update modes features remote update mode local update mode runlu input pin setting 1 0 page selection upon power up pgm[2..0] = 000 (factory) pgm[2..0] = 001 (application) supported configurations max ii device or microprocessor-based configuration, serial configuration, and enhanced configuration devices (fpp, ps, as, ppa) max ii device or microprocessor-based configuration and enhanced configuration devices (fpp, ps, ppa) number of pages supported eight pages for external host or controller based configuration; up to 128 pages (512 kbits/page) for serial configuration device two pages user watchdog timer available disabled remote system upgrade control and status register read/write access allowed in factory configuration. read access in application configuration only status register read access allowed in local update mode (factory and application configurations). write access to control register is disabled
8?10 altera corporation stratix ii device handbook, volume 2 january 2008 remote system upgrade modes remote access. this corresponds to pgm[2..0] = 000 of the enhanced configuration device or standard flash memory, and start address location 0x000000 in the seri al configuration device. the factory image is user design ed and contains soft logic to: process any errors based on status information from the dedicated remote system upgrade circuitry communicate with the remote host and receive new application configurations, and store this new configuration data in the local non-volatile memory device determine which application configuration is to be loaded into the fpga enable or disable the user watchdog timer and load its time-out value (optional) instruct the dedicated remote system upgrade circuitry to initiate a reconfiguration cycle figure 8?4 shows the transitions between the factory and application configurations in remote update mode. figure 8?4. transitions between configur ations in remote update mode set control register and reconfigure set control register and reconfigure reload a different application reload a different application application n configuration application 1 configuration factory configuration (page 0) configuration error configuration error power up configuration error
altera corporation 8?11 january 2008 stratix ii device handbook, volume 2 remote system upgrades with stratix ii and stratix ii gx devices after power up or a configuration error, the factory configuration logic should write the remote system upgr ade control register to specify the page address of the application conf iguration to be loaded. the factory configuration should also specify whether or not to enable the user watchdog timer for the application configuration and, if enabled, specify the timer setting. the user watchdog timer ensures that the application configuration is valid and functional. after confirmi ng the system is healthy, the user-designed application configuration should reset the timer periodically during user-mode operatio n of an applicatio n configuration. this timer reset logic should be a user-designed hardware and/or software health monitoring signal that indicates error-free system operation. if the user application configuration detects a functional problem or if the system hangs, the timer is not reset in time and the dedicated circuitry update s the remote system upgrade status register, triggering the device to load the factory configuration. the user watchdog timer is automatically di sabled for factory configurations. 1 only valid application configurations designed for remote update mode include the logic to reset the timer in user mode. 1 for more information about the user watchdog timer, see ?user watchdog timer? on page 8?20 . if there is an error while loading the application configuration, the remote system upgrade status register is wri tten by the stratix ii or stratix ii gx fpga?s dedicated remote system upgrade circuitry, specifying the cause of the reconfiguration. actions that cause the remote system upgrade status register to be written are: nstatus driven low externally internal crc error user watchdog timer time out a configuration reset (logic array nconfig signal or external nconfig pin assertion) stratix ii and stratix ii gx fpgas automatically load the factory configuration located at page address zero. this user-designed factory configuration should read the remote system upgrade status register to determine the reason for reconfiguration. the factory configuration should then take appropriate error re covery steps and write to the remote system upgrade control register to determine the next application configuration to be loaded.
8?12 altera corporation stratix ii device handbook, volume 2 january 2008 remote system upgrade modes when stratix ii or stratix ii gx devices successfully load the application configuration, they enter into user mode. in user mode, the soft logic (nios processor or state machine and the remote communication interface) assists the stratix ii or stra tix ii gx device in determining when a remote system update is arrivi ng. when a remote system update arrives, the soft logic receives th e incoming data, writes it to the configuration memory device, and triggers the device to load the factory configuration. the factory configuration reads the remote system upgrade status register, determines the valid application configuration to load, writes the remote system upgrad e control register accordingly, and initiates system reconfiguration. stratix ii and stratix ii gx fpgas suppo rt the remote update mode in the as, fpp, ps, and ppa configuration schemes. in the fpp, ps, and ppa schemes, the max ii device, microprocessor, or enhanced configuration device should sample the pgm[2..0] outputs from the stratix ii or stratix ii gx fpga and transmit the appropriate configuration image. in the as scheme, the stratix ii or stratix ii gx device uses the page addresses to read configuration data out of the serial configuration device. local update mode local update mode is a simplified version of the remote update mode. this feature allows systems to lo ad an application configuration immediately upon power up without loading the factory configuration first. local update mode does not require the factory configuration to determine which application configuration to load, because only one application configuration is allowed (at page address one ( pgm [2..0] = 001 ). you can update this application configuration remotely. if an error occurs while loading the application configuration, the factory configuration is automatically loaded. upon power up or nconfig assertion, the dedicated remote system upgrade circuitry dr ives out ?001? on the pgm[] pins selecting the application configuration stored in page one. if the device encounters any errors during the configuration cycle, the remote system upgrade circuitry retries configuration by driving pgm[2..0] to zero ( pgm[2..0] = 000 ) to select the factory configuration image. the error conditions that trigger a return to the factory configuration are: an internal crc error an external error signal ( nstatus detected low)
altera corporation 8?13 january 2008 stratix ii device handbook, volume 2 remote system upgrades with stratix ii and stratix ii gx devices when the remote system upgrade circuitry detects an external configuration reset ( nconfig pulsed low) or internal configuration reset (logic array nconfig assertion), the device attempts to reload the application configuration from page one. figure 8?5 shows the transitions between configurations in local update mode. figure 8?5. transitions between confi gurations in local update mode stratix ii and stratix ii gx fpgas suppo rt local update mode in the fpp, ps, and ppa configuration schemes. in these schemes, the max ii device, microprocessor, or enhanced configuration device should sample the pgm[2..0] outputs from the stratix ii or stratix ii gx fpga and transmit the appropriate configuration image. local update mode is not supported with the as conf iguration scheme, (or serial configuration device), because the stratix ii or stratix ii gx fpga cannot determine the start address of the application configuration page upon power up. while the factory configuration is always located at memory address 0x000000, the applicat ion configuration can be located at any other sector boundary within the serial configuration device. the start address depends on the size of the factory configuration and is user selectable. hence, only remote update mode is supported in the as configuration scheme. application confi g uration (pa g e 001) core or external nconfig assertion confi g uration error core or external nconfig assertion pow er up o r n c onfig assert ion factory confi g uration (pa g e 000) confi g uration error
8?14 altera corporation stratix ii device handbook, volume 2 january 2008 dedicated remote system upgrade circuitry 1 local update mode is not supported in the as configuration scheme (with a serial configuration device). local update mode supports read ac cess to the remote system upgrade status register. the factory configurat ion image can use this error status information to determine if a new a pplication configuration must be downloaded from the remote source . after a remote update, the user design should assert the logic array configuration reset ( nconfig ) signal to load the new application configuration. the device does not support write ac cess to the remote system upgrade control register in local update mode. write access is not required because this mode only supports one applicat ion configuration (eliminating the need to write in a page address) and does not support the user watchdog timer (eliminating the need to enable or disable the timer or specify its time-out value). 1 the user watchdog timer is disabled in local update mode. 1 write access to the remote system upgrade control register is disabled in local update mode. however, the device supports read access to obtain error status information. dedicated remote system upgrade circuitry this section explains the implementation of the stratix ii or stratix ii gx remote system upgrade dedicated circuitry. the remote system upgrade circuitry is implemented in hard logic. this dedicated circuitry interfaces to the user-defined factory applicatio n configurations implemented in the fpga logic array to provide the complete remote configuration solution. the remote system upgrade circuitry contains the remote system upgrade registers, a watchdog timer, and a state machine that controls those components. figure 8?6 shows the remote system upgrade block?s data path.
altera corporation 8?15 january 2008 stratix ii device handbook, volume 2 remote system upgrades with stratix ii and stratix ii gx devices figure 8?6. remote system upgrade circuit data path remote system upgrade registers the remote system upgrade block contai ns a series of registers that store the page addresses, watchdog timer settings, and stat us information. these registers are detailed in table 8?3 . logic array shift register status re g ister (sr) bit [4..0] control re g ister bit [20..0] din capture dout bit [4..0] lo g ic clkout ru_shiftnld ru_captnupdt ru_clk ru_din ru_nconfig ru_nrstimer user watchdo g timer ru_dout capture clkin update lo g ic capture din bit [20..0] dout update update re g ister bit [20..0] timeout rsu state machine internal oscillator table 8?3. remote system upgrade registers (part 1 of 2) register description shift register this register is ac cessible by the logic array and allows the update, status, and control registers to be written and sampled by user logi c. write access is enabled in remote update mode for factory configurations to allow writ es to the update register. write access is disabled in local update mode and for all applicat ion configurations in remote update mode. control register this register cont ains the current page address, the user watchdog timer settings, and one bit specifying whether the current configuration is a factory configuration or an application configuration. during a read operation in an appl ication configuration, this register is read into the shift register. when a reconfiguration cycle is initiated, the contents of the update register are written into the control register.
8?16 altera corporation stratix ii device handbook, volume 2 january 2008 dedicated remote system upgrade circuitry the remote system upgrade control and status registers are clocked by the 10-mhz internal oscillator (the same oscillator that controls the user watchdog timer). however, the remote system upgrade shift and update registers are clocked by the user clock input ( ru_clk ). remote system upgr ade control register the remote system upgrade control register stores the application configuration page address and user watchdog timer settings. the control register functionality depe nds on the remote system upgrade mode selection. in remote update mode, the control register page address bits are set to all zeros ( 7'b0 = 0000_000 ) at power up in order to load the factory configuration. however, in local update mode the control register page address bits power up as ( 7'b1 = 0000_001 ) in order to select the application configuration. additionally, the control register cannot be updated in local update mode, whereas a factory configuration in remote update mode has write access to this register. the control register bit positions are shown in figure 8?7 and defined in table 8?4 . in the figure, the numbers show the bit position of a setting within a register. for example, bit number 8 is the enable bit for the watchdog timer. figure 8?7. remote system upgrade control register update register this register contains data similar to that in the control register. however, it can only be updated by the factory configuration by shifting data into the shift register and issuing an update operation. when a reconfiguration cycle is triggered by the factory configuration, the control register is updated with the contents of the update register. during a read in a factory configuration, this register is read into the shift register. status register this register is written to by the remo te system upgrade circuitry on every reconfiguration to record the cause of the reconfiguration. this in formation is used by the factory configuration to determine the appropriate action following a re configuration. during a capture cycle, this register is read into the shift register. table 8?3. remote system upgrade registers (part 2 of 2) register description wd_timer[11..0] wd_en pgm[6..3] pgm[2..0] anf 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
altera corporation 8?17 january 2008 stratix ii device handbook, volume 2 remote system upgrades with stratix ii and stratix ii gx devices the application-not-factory ( anf ) bit indicates whether the current configuration loaded in the stratix ii or stratix ii gx device is the factory configuration or an applic ation configuration. this bit is set high at power up in local update mode, and is set low by the remote system upgrade circuitry when an error conditio n causes a fall-back to factory configuration. when the anf bit is high, the control register access is limited to read operations. when the anf bit is low, the register allows write operations and disa bles the watchdog timer. 1 in remote update mode, factory configuration design should set this bit high (1'b1) when updati ng the contents of the update register with applic ation page address and watchdog timer settings. table 8?4. remote system upgrade control register contents control register bit remote system upgrade mode value definition anf (1) local update remote update 1?b1 1'b0 application not factory pgm[2..0] local update remote update (fpp, ps, ppa) 3'b001 3'b000 page mode select remote update (as) 3'b000 as configuration start address ( stadd [ 18..16 ]) pgm[6..3] local update remote update (fpp, ps, ppa) 4'b0000 4'b0000 not used remote update (as) 4'b0000 as configuration start address ( stadd[22..19] ) wd_en remote update 1'b0 user watchdog timer enable bit wd_timer[11..0] remote update 12'b000000000000 user watchdog time-out value (most significant 12 bits of 29-bit count value: { wd_timer[11..0] , 17'b0} ) note to ta b l e 8 ? 4 : (1) in remote update mode, the remote co nfiguration block does not update the anf bit automatically (you can update it manually). in local update mo de, the remote configuration updates the anf bit with 0 in the factory page and 1 in the application page.
8?18 altera corporation stratix ii device handbook, volume 2 january 2008 dedicated remote system upgrade circuitry remote system upgrade status register the remote system upgrade status re gister specifies the reconfiguration trigger condition. the various trig ger and error conditions include: crc (cyclic redundancy check) error during application configuration nstatus assertion by an external device due to an error fpga logic array triggered a reconfiguration cycle, possibly after downloading a new applicat ion configuration image external configuration reset ( nconfig ) assertion user watchdog timer time out figure 8?8 and table 8?5 specify the contents of the status register. the numbers in the figure show the bit positions within a 5-bit register. figure 8?8. remote system upgrade status register table 8?5. remote system upgr ade status register contents status register bit definition por reset value crc (from configuration) crc error caused reconfiguration 1 bit '0' nstatus nstatus caused reconfiguration 1 bit '0' core (1) core_nconfig device logic array caused reconfiguration 1 bit '0' nconfig nconfig caused reconfiguration 1 bit '0' wd watchdog timer caused reconfiguration 1 bit '0' note to ta b l e 8 ? 5 : (1) logic array reconfiguration forces the system to load the application configuration data into the stratix ii or stratix ii gx device. this occurs after the factory configuration specifies the appropriate application configuration page address by updating the update register. wd 4 crc 0 nconfig 3 nstatus 1 core_nconfig 2
altera corporation 8?19 january 2008 stratix ii device handbook, volume 2 remote system upgrades with stratix ii and stratix ii gx devices remote system upgrade state machine the remote system upgrade control and update registers have identical bit definitions, but serve different roles (see table 8?3 on page 8?15 ). while both registers can only be upda ted when the fpga is loaded with a factory configuration image, the update register writes are controlled by the user logic, and the control register writes are controlled by the remote system upgrade state machine. in factory configurations, the user logic should send the anf bit (set high), the page address, and watchdog timer settings for the next application configuration bit to the update register. when the logic array configuration reset ( ru_nconfig ) goes high, the remote system upgrade state machine updates the control register with the contents of the update register and initiates system reconfiguration from the new application page. in the event of an error or reconfiguration trigger condition, the remote system upgrade state machine directs the system to load a factory or application configuration (page zero or page one, based on mode and error condition) by setting the control register accordingly. table 8?6 lists the contents of the control register after such an event occurs for all possible error or trigger conditions. the remote system upgrade status register is updated by the dedicated error monitoring circuitry after an error condition but before the factory configuration is loaded. table 8?6. control register contents after an error or reconfiguration trigger condition reconfiguration error/trigger control register setting remote update local update nconfig reset all bits are 0 pgm[6..0] = 7'b0000001 anf = 1 all other bits are 0 nstatus error all bits are 0 all bits are 0 core triggered reconfiguration update register pgm[6..0] = 7'b0000001 anf = 1 all other bits are 0 crc error all bits are 0 all bits are 0 wd time out all bits are 0 all bits are 0
8?20 altera corporation stratix ii device handbook, volume 2 january 2008 dedicated remote system upgrade circuitry read operations during factory configuration access the contents of the update register. this feature is used by the user logic to verify that the page address and watchdog timer sett ings were written correctly. read operations in application configurations access the contents of the control register. this information is used by the user logic in the application configuration. user watchdog timer the user watchdog timer prevents a faulty application configuration from stalling the device indefinitely. the system uses the timer to detect functional errors after an application configuration is successfully loaded into the fpga. the user watchdog timer is a counter that counts down from the initial value loaded into the remote system upgrade control register by the factory configuration. the counter is 29-bits-wide and has a maximum count value of 2 29 . when specifying the user watchdog timer value, specify only the most significant 12 bits. the granularity of the timer setting is 2 15 cycles. the cycle time is ba sed on the frequency of the 10-mhz internal oscillator. table 8?7 specifies the operating range of the 10-mhz internal oscillator. the user watchdog timer begins counting once the application configuration enters fpga user mode. this timer must be periodically reloaded or reset by the application configuration before the timer expires by asserting ru_nrstimer . if the application configuration does not reload the user watchdog timer before the count expires, a time-out signal is generated by the remote system upgrade dedicated circuitry. the time-out signal tells the remote syst em upgrade circuitry to set the user watchdog timer status bit ( wd ) in the remote system upgrade status register and reconfigures the device by loading the factory configuration. the user watchdog timer is not enable d during the configuration cycle of the fpga. errors during configuration are detected by the crc engine. also, the timer is disabled for factor y configurations. functional errors should not exist in the factory configuration since it is stored and validated during production an d is never updated remotely. table 8?7. 10-mhz internal os cillator spec ifications minimum typical maximum units 56.510mhz
altera corporation 8?21 january 2008 stratix ii device handbook, volume 2 remote system upgrades with stratix ii and stratix ii gx devices 1 the user watchdog timer is disa bled in factory configurations and during the configuration cycle of the application configuration. it is enabled af ter the application configuration enters user mode. interface signals between remote system upgrade circuitry and fpga logic array the dedicated remote system upgrade circuitry drives (or receives) seven signals to (or from) the fpga logic arra y. the fpga logic array uses these signals to read and write the remote system upgrade control, status, and update registers using the remote system upgrade shift register. table 8?8 lists each of these seven signals and describes their functionality. except for ru_nrstimer and ru_captnupdt , the logic array signals are enabled for both remote and local update modes and for both factory and application configurations. ru_nrstimer is only valid for application configurations in remote update mode , since local update configurations and factory configurations have the user watchdog timer disabled. when ru_captnupdt is low, the device can write to the update register only for factory configurations in remote update mode, since this is the only case where the update register is writ ten to by the user logic. when the ru_nconfig signal goes high, the contents of the update register are written into the control register for controlling the next configuration cycle. table 8?8. interface signals between remote system upgrade circuitry and fpga logic array (part 1 of 3) signal name signal direction description ru_nrstimer input to remote system upgrade block (driven by fpga logic array) request from the application conf iguration to reset the user watchdog timer with its initial coun t. a falling edge of this signal triggers a reset of the user watchdog timer. ru_nconfig input to remote system upgrade block (driven by fpga logic array) when driven low, this signal triggers the device to reconfigure. if asserted by the factory configuration in remote update mode, the application configuration specified in the remote update control register is loaded. if requested by the application configuration in remote update mode, the factory configuration is loaded. in the local updated mode, the application configuration is loaded whenever this signal is asserted.
8?22 altera corporation stratix ii device handbook, volume 2 january 2008 dedicated remote system upgrade circuitry ru_clk input to remote system upgrade block (driven by fpga logic array) clocks the remote system upgrade shift register and update register so that the contents of the status, control, and update registers can be read, and so that the contents of the update register can be loaded. the shift register latches data on the rising edge of this clock signal. ru_shiftnld input to remote system upgrade block (driven by fpga logic array) this pin determines if the shi ft register contents are shifted over during the next clock edge or loaded in/out. when this signal is driven high (1'b1), the remote system upgrade shift register shifts data left on each rising edge of ru_clk . when ru_shiftnld is driven low (1'b0) and ru_captnupdt is driven low (1'b0), the remote system upgrade update register is updated with the contents of the shift register on the rising edge of ru_clk . when ru_shiftnld is driven low (1'b0) and ru_captnupdt is driven high (1'b1), the remote system upgrade shift register captures t he status register and either the control or update register (depending on whether the current configuration is application or factory, respectively) on the rising edge of ru_clk . ru_captnupdt input to remote system upgrade block (driven by fpga logic array) this pin determines if the cont ents of the shift register are captured or updated on the next clock edge. when the ru_shiftnld signal is driven high (1'b1), this input signal has no function. when ru_shiftnld is driven low (1'b0) and ru_captnupdt is driven high (1'b1), the remote system upgrade shift register captures t he status register and either the control or update register (depending on whether the current configuration is application or factory, respectively) on the rising edge of ru_clk . when ru_shiftnld is driven low (1'b0) and ru_captnupdt is driven low (1'b0), the remote system upgrade update register is updated with the contents of the shift register on the rising edge of ru_clk . in local update mode, a low input on ru_captnupdt has no function, because the update r egister cannot be updated in this mode. table 8?8. interface signals between remote system upgrade circuitry and fpga logic array (part 2 of 3) signal name signal direction description
altera corporation 8?23 january 2008 stratix ii device handbook, volume 2 remote system upgrades with stratix ii and stratix ii gx devices remote system upgrade pin descriptions table 8?9 describes the dedicated remote system upgrade configuration pins. f for descriptions of all the configuration pins, refer to the configuring stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii handbook and the configuring stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx handbook . ru_din input to remote system upgrade block (driven by fpga logic array) data to be written to the remote system upgrade shift register on the rising edge of ru_clk . to load data into the shift register, ru_shiftnld must be asserted. ru_dout output from remote system upgrade block (driven to fpga logic array) output data from the remote system upgrade shift register to be read by logic array logic. ne w data arrives on each rising edge of ru_clk . table 8?8. interface signals between remote system upgrade circuitry and fpga logic array (part 3 of 3) signal name signal direction description
8?24 altera corporation stratix ii device handbook, volume 2 january 2008 quartus ii software support quartus ii software support implementation in your design re quires an remote system upgrade interface between the fpga logic array and remote system upgrade circuitry. you also need to generate configuration files for production and remote programming of the syst em configuration memory. the quartus ? ii software provides these features. the two implementation options, altremote_update megafunction and remote system upgrade atom, are for the interface between the remote system upgrade circuitry and the fpga logic array interface. altremote_update megafunction the altremote_update megafunction provides a memory-like interface to the remote system upgr ade circuitry and handles the shift register read/write protocol in fpga logic. this implementation is suitable for designs that implement the factory configuration functions using a nios processor in the fpga. table 8?9. stratix ii and st ratix ii gx remote system upgrade pins pin name user mode configuration scheme pin type description runlu n/a if using remote system upgrade in fpp, ps, as, or ppa modes. i/o if not using these modes. remote configuration in fpp, ps, or ppa input input that selects between remote update and local update. a logic high (1.5-v, 1.8- v, 2.5-v, 3.3-v) selects remote update, and a logic low selects local update. when not using remote update or local update configuration modes, this pin is available as a general-purpose user i/o pin. when using remote configuration in as mode, set the runlu pin to high because as does not support local update. pgm[2..0] n/a if using remote system upgrade in fpp, ps, as, or ppa modes. i/o if not using these modes. remote configuration in fpp, ps or ppa output these output pins select one of eight pages in the memory (either flash or enhanced configuration device) when using remote update mode. when not using remote update or local update configuration modes, these pins are available as general-purpose user i/o pins.
altera corporation 8?25 january 2008 stratix ii device handbook, volume 2 remote system upgrades with stratix ii and stratix ii gx devices tables 8?10 and 8?11 describe the input and outp ut ports available on the altremote_update megafunction. table 8?12 shows the param[2..0] bit settings. table 8?10. input ports of the altr emote_update megafunction (part 1 of 2) port name require d source description clock y logic array clock input to the altremote_update block. all operations are performed with respects to the rising edge of this clock. reset y logic array asynchronous reset, which is used to initialize the remote update block. to ensure proper operation, the remote update block must be reset before first accessing the remote update block. this signal is not affected by the bu sy signal and will reset the remote update block even if busy is logic high. this means that if the reset signal is driven logic high during writing of a parameter, the parameter will not be properly written to the remote update block. reconfig y logic array when driven logic high, reconfigurat ion of the device is initiated using the current parameter settings in the remote update block. if busy is asserted, this signal is ignored. this is to ensure all parameters are completely written before reconfiguration begins. reset_timer n logic array this signal is required if you ar e using the watchdog timer feature. a logic high resets the internal watchdog timer. this signal is not affected by the busy signal and can reset the timer even when the remote update block is busy. if this port is left connected, the default value is 0. read_param n logic array once read_param is sampled as a logic high, the busy signal is asserted. while the parameter is being read, the busy signal remains asserted, and inputs on param[] are ignored. once the busy signal is deactivated, the next parameter can be read. if this port is left unconnected, the default value is 0. write_param n logic array this signal is required if you intend on writing parameters to the remote update block. when driven logic high, the parameter specified on the param[] port should be written to the remote update block with the value on data_in[] . the number of valid bits on data_in[] is dependent on the parameter type. this signal is sampled on the rising edge of clock and should only be asserted for one clock cycle to prevent the parameter from being re-read on subsequent clock cycles. once write_param is sampled as a logic high, the busy signal is asserted. while the parameter is being written, the busy signal remains asserted, and inputs on param[] and data_in[] are ignored. once the busy signal is deactivated, the next parameter can be written. this signal is only valid when the current_configuration parameter is factory since parameters cannot be written in application configurations. if th is port is left unconnected, the default value is 0.
8?26 altera corporation stratix ii device handbook, volume 2 january 2008 quartus ii software support param[2..0] n logic array 3-bit bus that selects which parameter should be read or written. if this port is left unconnected, the default value is 0. data_in[11..0] n logic array this signal is required if you intend on writing parameters to the remote update block 12-bit bus used when writing parameters, which specifies the parameter value. the parameter value is requested using the param[] input and by driving the write_param signal logic high, at wh ich point the busy signal goes logic high and the value of t he parameter is captured from this bus. for some parameters, not all 12 bits are used, in which case only the least significant bi ts are used. this port is ignored if the current_configuration parameter is set to an application configuration since writing of parameters is only allowed in the factory configuration. if this port is left unconnected, the default value is 0. note to ta b l e 8 ? 1 0 : (1) logic array source means that you can drive the port from internal logic or any general-purpose i/o pin. table 8?11. output ports of the altr emote_update megafunction (part 1 of 2) port name required destination description busy y logic array when this signal is a logi c high, the remote update block is busy either reading or writing a parameter. when the remote update block is busy, it ignores its data_in[] , param[] , and reconfig inputs. this signal goes high when read_param or write_param is asserted and remains asserted until the operation is complete. pgm_out[2..0] y pgm[2..0] pins 3-bit bus that specifies the page pointer of the configuration data to be loaded when the device is reconfigured. this port must be connected to the pgm[] output pins, which should be connected to the external configuration device. table 8?10. input ports of the altr emote_update megafunction (part 2 of 2) port name require d source description
altera corporation 8?27 january 2008 stratix ii device handbook, volume 2 remote system upgrades with stratix ii and stratix ii gx devices data_out[11..0] n logic array 12-bit bus used when readi ng parameters, which reads out the parameter value. the parameter value is requested using the param[] input and by driving the read_param signal logic high, at which point the busy signal goes logic high. when the busy signal goes low, the value of the parameter is driven out on this bus. the data_out[] port is only valid after a read_param has been issued and once the busy signal is deasserted. at any other time, its output values are invalid. for example, even though the data_out[] port may toggle during a writing of a parameter, these values are not a valid representation of what was actually written to the remote update block. for some parameters, not all 12 bits are used, in which case only the least significant bits are used. note to ta b l e 8 ? 11 : (1) logic array destination means that you can drive the port to internal logic or any general-purpose i/o pin. table 8?12. parameter settings for the altremote_update megafun ction (part 1 of 2) selected parameter param[2..0] bit setting width of parameter value por reset value description status register contents 000 5 5 bit '0 specifies the reason for re-configuration, which could be caused by a crc error during configuration, nstatus being pulled low due to an error, the device core caused an error, nconfig pulled low, or the watchdog timer timed-out. this parameter can only be read. watchdog timeout value 010 12 12 bits '0 user watchdog timer time-out value. writing of this parameter is only allowed when in the factory configuration. watchdog enable 011 1 1 bit '0 user watchdog timer enable. writing of this parameter is only allowed when in the factory configuration page select 100 3 (fpp, ps, ppa) 3 bit '001' - local configuration page mode selection. writing of this parameter is only allowed when in the factory configuration. 3 bit '000' - remote configuration 7 (as) 7 bit '0000000' - remote configuration table 8?11. output ports of the altr emote_update megafunction (part 2 of 2) port name required destination description
8?28 altera corporation stratix ii device handbook, volume 2 january 2008 system design guidelines remote system upgrade atom the remote system upgrade atom is a wysiwyg atom or primitive that can be instantiated in your design. the primitive is used to access the remote system upgrade shift register , logic array reset, and watchdog timer reset signals. the ports on this primitive are the same as those listed in table 8?8 . this implementation is suitable for designs that implement the factory configuration functions using state machines (without a processor). system design guidelines the following general guidelines are applicable when implementing remote system upgrade in stratix ii and stratix ii gx fpgas. guidelines for specific configuration schemes are also discussed in this section. after downloading a new applicatio n configuration, the soft logic implemented in the fpga can validate the integrity of the data received over the remote communica tion interface. this optional step helps avoid configuration attempts with bad or incomplete configuration data. however, in th e event that bad or incomplete configuration data is sent to the fpga, it detects the data corruption using the crc signature attached to each configuration frame. the auto-reconfigure on configurat ion error option bit is ignored when remote system upgrade is enab led in your system. this option is always enabled in remote conf iguration designs, allowing your system to return to the safe factor y configuration in the event of an application configuration error or user watchdog timer time out. current configuration (anf) 101 1 1 bit '0' - factory specifies whether the current configuration is factory or and application configuration. this parameter can only be read. 1 bit '1' - application illegal values 001 110 111 table 8?12. parameter settings for the altremote_update megafun ction (part 2 of 2) selected parameter param[2..0] bit setting width of parameter value por reset value description
altera corporation 8?29 january 2008 stratix ii device handbook, volume 2 remote system upgrades with stratix ii and stratix ii gx devices remote system upgrade with serial configuration devices remote system upgrade support in the as configuration scheme is similar to support in other schemes, with the following exceptions: the remote system upgrade block provides the as configuration controller inside the stratix ii or stra tix ii gx fpga with a 7-bit page start address ( pgm[6..0] ) instead of driving the 3-bit page mode pins ( pgm[2..0] ) used in fpp, ps, and ppa configuration schemes. this 7-bit address forms the 24- bit configuration start address ( stadd[23..0] ). table 8?13 illustrates the start address generation using the page address registers. the configuration start address for factory configuration is always set to 24'b0. pgm[2..0] pins on stratix ii devices are not used in as configuration schemes and can not be used as regular i/o pins. the nios asmi peripheral can be used to update configuration data within the serial configuration device. remote system upgrade with a max ii device or microprocessor and flash device this setup requires the max ii device or microprocessor to support page addressing. max ii or microprocess or devices implementing remote system upgrade should emulate the e nhanced configurat ion device page mode feature. the pgm[2..0] output pins from the stratix ii or stratix ii gx device must be sampled to determine which configuration image is to be loaded into the fpga. if the fpga does not release conf_done after all data has been sent, the max ii microprocessor should reset th e fpga back to the factory image by pulsing its nstatus pin low. table 8?13. as configuration start address generation serial configuration device serial configuration device density (mb) add[23] pgm[6..0] (add[22..16]) add[15..0] epcs64 64 0 msb[6..0] all 0s epcs16 16 0 00, msb[4..0] all 0s epcs4 4 0 0000, msb[2..0] all 0s
8?30 altera corporation stratix ii device handbook, volume 2 january 2008 system design guidelines the max ii device or microprocessor and flash configuration can use fpp, ps, or ppa. decompression and design security features are supported in the fpp (requires 4 dclk) and ps modes only. figure 8?9 shows a system block diagram for remote system upgrade with the max ii device or microprocessor and flash. figure 8?9. system block diagram for remote system upgrade with max ii device or microprocessor and flash device notes to figure 8?9 : (1) connect the pull-up resistor to a supply that provides an acceptable input signal for the device. (2) connect runlu to gnd or v cc to select between remote and local update modes. (3) connect msel[3..0] to 0100 to enable remote update remote system upgrade mode. remote system upgrade with enhanced configuration devices enhanced configuration devices support remote system upgrade with fpp or ps configuration scheme s. the stratix ii or stratix ii gx decompression and design security features are only supported in the ps mode. the enhanced configuration device?s decompression feature is supported in both ps and fpp schemes. in remote update mode, neither the factory configuration nor the application configurations should alter the enhanced configuration device?s option bits or the page 000 factory configuration data. this ensures that an error during remote update can always be resolved by reverting to the factory configuration located at page 000. external host (max ii device or microprocessor) conf_done nstatus nce data[7..0] nconfig stratix ii/stratix ii gx device memory addr data[7..0] gnd msel[3..0] v cc (1) v cc (1) dclk nceo n.c. 10 k 10 k pgm[2..0] runlu (2) (3)
altera corporation 8?31 january 2008 stratix ii device handbook, volume 2 remote system upgrades with stratix ii and stratix ii gx devices the enhanced configuration device features an error checking mechanism to detect instances when the fpga fails to detect the configuration preamble. in th ese instances, the enhanced configuration device pulses the nstatus signal low, and the remote system upgrade circuitry attempts to load the factory configuration. figure 8?10 shows a system block diagram for remote system upgrade with enhanced configuration devices. figure 8?10. system block diagram fo r remote system upgrade with enhanced configuration devices notes to figure 8?10 : (1) connect the pull-up resistor to a supply that provides an acceptable input signal for the device. (2) connect runlu to gnd or v cc to select between remote and local update modes. (3) connect msel[3..0] to 0100 to enable remote update remote system upgrade mode. conclusion stratix ii and stratix ii gx devices offer remote system upgrade capability, where you can upgrade a system in real-time through any network. remote system upgrade he lps to deliver feature enhancements and bug fixes without costly recalls, reduces time to market, and extends product life cycles. the dedicated re mote system upgrade circuitry in stratix ii and stratix ii gx devices pr ovides error detection, recovery, and status information to ensure reliable reconfiguration. referenced documents this chapter references the following documents: configuring stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii handbook stratix ii/stratix ii gx device enhanced confi g uration device dclk data[7..0] oe ncs ninit_conf (2) dclk data[7..0] nstatus conf_done nconfig v cc v cc gnd (1) (1) nce (3) (3) nceo n.c. runlu msel[3..0] 10 k 10 k (3) (3) pgm[2..0] pgm[2..0] external flash interface (2) (3)
8?32 altera corporation stratix ii device handbook, volume 2 january 2008 document revision history configuring stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx handbook enhanced configuration devices (e pc4, epc8 & epc16) data sheet chapter in volume 2 of the configuration handbook serial configuration devices (epc s1, epcs4, epcs16, epcs64, and epcs128) data sheet in volume 2 of the configuration handbook document revision history table 8?14 shows the revision history for this chapter. table 8?14. document revision history date and document version changes made summary of changes january 2008, v4.5 updated pgm[2..0] information in table 8?9 . ? updated ta b l e 8 ? 7 . added the ?referenced documents? section. ? minor text edits. ? no change for the stratix ii gx device handbook only: formerly chapter 13. the chapter number changed due to the addition of the stratix ii gx dynamic reconfiguration chapter. no content change. ? may 2007, v4.4 updated note to ?functional description? section. ? minor text edit to ?remote system upgrade with serial configuration devices? section. ? february 2007 v4.3 added the ?document revision history? section to this chapter. ? april 2006, v4.2 chapter updated as part of the stratix ii device handbook update. ? no change formerly chapter 12. chapter number change only due to chapter addition to section i in february 2006; no content change. ? december 2005, v4.1 chapter updated as part of the stratix ii device handbook update. ? october 2005 v4.0 added chapter to the stratix ii gx device handbook . ?
altera corporation 9?1 january 2008 9. ieee 1149.1 (jtag) boundary-scan testing for stratix ii and stratix ii gx devices introduction as printed circuit boards (pcbs) become more complex, the need for thorough testing becomes increasi ngly important. advances in surface-mount packaging and pcb ma nufacturing have resulted in smaller boards, making traditional te st methods (such as ; external test probes and ?bed-of-nails? test fixture) harder to implement. as a result, cost savings from pcb space reductions increases the cost for traditional testing methods. in the 1980s, the joint test action gr oup (jtag) developed a specification for boundary-scan testing that was la ter standardized as the ieee std. 1149.1 specification. this boundary-sca n test (bst) architecture offers the capability to test efficiently componen ts on pcbs with tight lead spacing. this bst architecture tests pin connections without using physical test probes and captures functional data while a device is operating normally. boundary-scan cells in a device can force signals onto pins or capture data from pin or logic array signals. forced test data is serially shifted into the boundary-scan cells. captured data is serially shifted out and externally compared to expected results. figure 9?1 illustrates the concept of bst. figure 9?1. ieee std. 1149.1 boundary-scan testing core logic serial data in boundary-scan cell ic core logic serial data out jtag device 1 jtag device 2 pin signal tested connection sii52009-3.3
9?2 altera corporation stratix ii device handbook, volume 2 january 2008 ieee std. 1149.1 bst architecture this chapter discusses how to use th e ieee std. 1149.1 bst circuitry in stratix ? ii and stratix gx devices, including: ieee std. 1149.1 bst architecture ieee std. 1149.1 boun dary-scan register ieee std. 1149.1 bst operation control i/o voltage support in jtag chain ieee std. 1149.1 bst circuitry utilization ieee std. 1149.1 bst circuitry disabling ieee std. 1149.1 bst guidelines boundary-scan description language (bsdl) support in addition to bst, you can use the ieee std. 1149.1 controller for stratix ii and stratix ii gx device in-circuit re configuration (icr). however, this chapter only discusses the bst feature of the ieee std. 1149.1 circuitry. f for information on configuring strati x ii devices via the ieee std. 1149.1 circuitry, refer to the configuring stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii device handbook , or the configuring stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook . 1 when configuring via ijag make sure that stratix ii, stratix ii gx, stratix, cyclone ? ii, and cyclone devices are within the first 17 devices in a jt ag chain. all of these devices have the same jtag controller. if any of the stratix ii, stratix ii gx, stratix, cyclone ii, and cyclone devices are in the 18th or further position, configurat ion fails. this does not affect signaltap ? ii or boundary-scan testing. ieee std. 1149.1 bst architecture a stratix ii and stratix ii gx device operating in ieee std. 1149.1 bst mode uses four required pins, tdi , tdo , tms and tck , and one optional pin, trst . the tck pin has an internal weak pull-down resistor, while the tdi , tms and trst pins have weak internal pull-ups. the tdo output pin is powered by v ccio in i/o bank 4. all of the jtag input pins are powered by the 3.3-v v ccpd supply. all user i/o pins are tri-stated during jtag configuration. 1 for recommendations on how to connect a jtag chain with multiple voltages across the de vices in the chain, refer to ?i/o voltage support in jtag chain? on page 9?17 .
altera corporation 9?3 january 2008 stratix ii device handbook, volume 2 ieee 1149.1 (jtag) boundary-scan testin g for stratix ii and stratix ii gx devices table 9?1 summarizes the functions of each of these pins. the ieee std. 1149.1 bst circuitry requires the following registers: the instruction register determines the action to be performed and the data register to be accessed. the bypass register is a 1-bit-long data register that provides a minimum-length serial path between tdi and tdo . the boundary-scan register is a sh ift register composed of all the boundary-scan cells of the device. table 9?1. ieee std. 1149.1 pin descriptions pin description function tdi test data input serial input pin for instruct ions as well as test and programming data. data is shifted in on the rising edge of tck . tdo test data output serial data output pin for inst ructions as well as test and programming data. data is shifted out on the falling edge of tck . the pin is tri-stated if data is not being shifted out of the device. tms test mode select input pin that provides the c ontrol signal to determine the transitions of the test access port (tap) controller state machine. transitions within the state machine occur at the rising edge of tck . therefore, tms must be set up before the rising edge of tck . tms is evaluated on the rising edge of tck . tck test clock input the clock input to the bst circuitry. some operations occur at the rising edge, while others occur at the falling edge. trst test reset input (optional) active-low input to asynchronous ly reset the boundary-scan circuit. this pin should be driven low when not in boundary-scan operation and for non-jtag users the pin s hould be permanently tied to gnd.
9?4 altera corporation stratix ii device handbook, volume 2 january 2008 ieee std. 1149.1 boundary-scan register figure 9?2 shows a functional model of the ieee std. 1149.1 circuitry. figure 9?2. ieee std. 1149.1 circuitry note to figure 9?2 : (1) refer to the appropriate device data sheet for register lengths. ieee std. 1149.1 boundary-scan testing is controlled by a test access port (tap) controller. for more information on the tap controller, refer to ?ieee std. 1149.1 bst operation control? on page 9?7 . the tms and tck pins operate the tap controller, and the tdi and tdo pins provide the serial path for the data registers. the tdi pin also provides data to the instruction register, which then ge nerates control logic for the data registers. ieee std. 1149.1 boundary-scan register the boundary-scan register is a large serial shift register that uses the tdi pin as an input and the tdo pin as an output. the boundary-scan register consists of 3-bit peripheral elements that are associated with stratix ii or stratix ii gx i/o pins. you can use th e boundary-scan register to test external pin connec tions or to capture internal data. a updateir clockir shiftir updatedr clockdr shiftdr tdi instruction register bypass register boundary-scan register instruction decode tms tclk ta p controller icr registers tdo data registers device id register trst (1) (1) (1)
altera corporation 9?5 january 2008 stratix ii device handbook, volume 2 ieee 1149.1 (jtag) boundary-scan testin g for stratix ii and stratix ii gx devices f refer to the configuration & testing chapter in volume 1 of the stratix ii device handbook , or the configuration & testing chapter in volume 1 of the stratix ii gx device handbook for the stratix ii family device boundary-scan register lengths. figure 9?3 shows how test data is serially shifted around the periphery of the ieee std. 1149.1 device. figure 9?3. boundary-scan register boundary-scan cells of a stratix ii or stratix ii gx device i/o pin the stratix ii or the stratix ii gx devi ce 3-bit boundary-scan cell (bsc) consists of a set of capture register s and a set of update registers. the capture registers can connect to internal device data via the outj , oej , and pin_in signals, while the update registers connect to external data through the pin_out , and pin_oe signals. the global control signals for the ieee std. 1149.1 bst registers (such as shift, clock, and update) are generated internally by the tap controller. the mode signal is generated by a decode of the instruction register. the data signal path for the boundary-scan register ru ns from the serial data in (sdi) signal to the serial data out (sdo) signal. th e scan register begins at the tdi pin and ends at the tdo pin of the device. tck trst (1) tms tap controller tdi internal lo g ic tdo e ac h per i p h era l e l e m e n t i s e i t h er a n i/o p in, ded i cated in p u t p in, o r ded i cated c on f i g u rat ion p in.
9?6 altera corporation stratix ii device handbook, volume 2 january 2008 ieee std. 1149.1 boundary-scan register figure 9?4 shows the stratix ii and stratix ii gx device?s user i/o boundary-scan cell. figure 9?4. stratix ii and stra tix ii gx device's user i/o bsc with ieee std. 1149.1 bst circuitry table 9?2 describes the capture and update register capabilities of all boundary-scan cells within stratix ii and stratix ii gx devices. 0 1 dq output dq oe dq input dq input dq output dq oe from or to device i/o cell circuitry and/or logic array 0 1 0 1 0 1 0 1 0 1 0 1 pin_out inj oej outj v cc sdo pin shift sdi clock update highz mode pin_oe pin_in output buffer capture registers update registers global signals table 9?2. stratix ii and stratix ii gx device b oundary scan cell descriptions (part 1 of 2) note (1) pin type captures drives comments output capture register oe capture register input capture register output update register oe update register input update register user i/o pins outj oej pin_in pin_out pin_oe inj na dedicated clock input 01 pin_in n.c. (2) n.c. (2) n.c. (2) pin_in drives to clock network or logic array
altera corporation 9?7 january 2008 stratix ii device handbook, volume 2 ieee 1149.1 (jtag) boundary-scan testin g for stratix ii and stratix ii gx devices ieee std. 1149.1 bst operation control stratix ii and stratix ii gx devices im plement the following ieee std. 1149.1 bst instructions: sample/preload instruction mode is used to take snapshot of the device data without interrupt ing normal device operations extest instruction mode is used to check external pin connections between devices bypass instruction mode is used when an instruction code consisting of all ones is load ed into the instruction register idcode instruction mode is used to identify the devices in an ieee std. 1149.1 chain usercode instruction mode is used to examine the user electronic signature within the device al ong an ieee std. 1149.1 chain. dedicated input (3) 01 pin_in n.c. (2) n.c. (2) n.c. (2) pin_in drives to control logic dedicated bidirectional (open drain) (4) 0 oej pin_in n.c. (2) n.c. (2) n.c. (2) pin_in drives to configuration control dedicated bidirectional (5) outj oej pin_in n.c. (2) n.c. (2) n.c. (2) pin_in drives to configuration control and outj drives to output buffer dedicated output (6) outj 00n.c. (2) n.c. (2) n.c. (2) outj drives to output buffer notes to ta b l e 9 ? 2 : (1) tdi , tdo , tms , tck , all v cc and gnd pin types, vref , and temp_diode pins do not have bscs. (2) no connect (n.c.). (3) this includes pins pll_ena , nconfig , msel0 , msel1 , msel2 , msel3 , nce , vccsel , porsel , and nio_pullup . (4) this includes pins conf_done and nstatus . (5) this includes pin dclk . (6) this includes pin nceo . table 9?2. stratix ii and stratix ii gx device b oundary scan cell descriptions (part 2 of 2) note (1) pin type captures drives comments output capture register oe capture register input capture register output update register oe update register input update register
9?8 altera corporation stratix ii device handbook, volume 2 january 2008 ieee std. 1149.1 bst operation control clamp instruction mode is used to allow the state of the signals driven from the pins to be de termined from the boundary-scan register while the bypass register is selected as the serial path between the tdi and tdo ports highz instruction mode sets all of th e user i/o pins to an inactive drive state the bst instruction length is 10 bits. these instructions are described later in this chapter. f for summaries of the bst instructions and their instruction codes, refer to the configuration & testing chapter in volume 1 of the stratix ii device handbook , or the configuration & testing chapter in volume 1 of the stratix ii gx device handbook . the ieee std. 1149.1 tap controller, a 16-state state machine clocked on the rising edge of tck , uses the tms pin to control ieee std. 1149.1 operation in the device. figure 9?5 shows the tap controller state machine.
altera corporation 9?9 january 2008 stratix ii device handbook, volume 2 ieee 1149.1 (jtag) boundary-scan testin g for stratix ii and stratix ii gx devices figure 9?5. ieee std. 1149.1 tap controller state machine when the tap controller is in the test_logic/reset state, the bst circuitry is disabled, the device is in normal operation, and the instruction register is initialized with idcode as the initial instruction. at device power-up, the tap controller starts in this test_logic/reset state. in addition, forcing the tap controller to the test_logic/reset state is done by holding tms high for five tck clock cycles or by holding the trst pin low. once in the test_logic/reset state, the tap controller remains in this state as long as tms is held high (while tck is clocked) or trst is held low. select_dr_scan capture_dr shift_dr exit1_dr pause_dr exit2_dr update_dr shift_ir exit1_ir pause_ir exit2_ir update_ir tms = 0 tms = 0 tms = 0 tms = 1 tms = 0 tms = 1 tms = 1 tms = 0 tms = 1 tms = 0 tms = 1 tms = 1 tms = 0 tms = 0 tms = 1 tms = 1 tms = 0 tms = 1 tms = 0 tms = 0 tms = 1 tms = 0 tms = 0 tms = 1 tms = 0 run_test/ idle tms = 0 test_logic/ reset tms = 1 tms = 0 tms = 1 tms = 1 tms = 1 tms = 1 capture_ir select_ir_scan
9?10 altera corporation stratix ii device handbook, volume 2 january 2008 ieee std. 1149.1 bst operation control figure 9?6 shows the timing requirements fo r the ieee std. 1149.1 signals. figure 9?6. ieee std. 1149.1 timing waveforms to start ieee std. 1149.1 operation, select an instruction mode by advancing the tap controller to the shift instruction register ( shift_ir ) state and shift in the appropriate instruction code on the tdi pin. the waveform diagram in figure 9?7 represents the entry of the instruction code into the instruction register. figure 9?7 shows the values of tck , tms , tdi , tdo , and the states of the tap controller. from the reset state, tms is clocked with the pattern 01100 to advance the tap controller to shift_ir . figure 9?7. selecting the instruction mode tdo tck t jpzx t jpco t jph t jpxz t jcp t jpsu t jcl t jch tdi tms signal to be captured signal to be driven t jszx t jssu t jsh t jsco t jsxz tck tms tdi tdo ta p _ s tat e shift_ir run_test/idle select_ir_scan select_dr_scan test_logic/reset capture_ir exit1_ir
altera corporation 9?11 january 2008 stratix ii device handbook, volume 2 ieee 1149.1 (jtag) boundary-scan testin g for stratix ii and stratix ii gx devices the tdo pin is tri-stated in all states except in the shift_ir and shift_dr states. the tdo pin is activated at the first falling edge of tck after entering either of the shift states and is tri-stated at the first falling edge of tck after leaving either of the shift states. when the shift_ir state is activated, tdo is no longer tri-stated, and the initial state of the instruction register is shifted out on the falling edge of tck . tdo continues to shift out the contents of the instruction register as long as the shift_ir state is active. the tap controller remains in the shift_ir state as long as tms remains low. during the shift_ir state, an instruction code is entered by shifting data on the tdi pin on the rising edge of tck . the last bit of the instruction code is clocked at the same time that the next state, exit1_ir , is activated. set tms high to activate the exit1_ir state. once in the exit1_ir state, tdo becomes tri-stated again. tdo is always tri-stated except in the shift_ir and shift_dr states. after an instruction code is entered correctly, the tap controller advances to serially shift test data in one of thr ee modes. the three serially shift test data instruction modes are discussed on the following pages: ?sample/preload instruction mode? on page 9?11 ?extest instruction mode? on page 9?13 ?bypass instruction mode? on page 9?15 sample/preload instruction mode the sample/preload instruction mode allows you to take a snapshot of device data without interrupting norm al device operation. however, this instruction is most ofte n used to preload the test data into the update registers prior to loading the extest instruction. figure 9?8 shows the capture, shift, and update phases of the sample / preload mode.
9?12 altera corporation stratix ii device handbook, volume 2 january 2008 ieee std. 1149.1 bst operation control figure 9?8. ieee std. 1149.1 bst sample/preload mode 1 0 dq dq 1 0 1 0 1 0 dq dq 1 0 dq dq 1 0 outj oej mode inj capture registers update registers sdo sdi shift clock update 1 0 dq dq 1 0 1 0 1 0 dq dq 1 0 dq dq 1 0 outj oej sdi shift clock update mode sdo inj capture registers update registers capture phase in the capture phase, the signals at the pin, oej and outj, are load ed into the capture registers. the clock signals is supplied by the tap controller?s clockdr output. the data retained in these registers consists of signals from normal device operation. shift and update phases in the shift phas e, the previously captured signals at the pin, oej and outj, are shifted out of the boundary-scan register via the tdo pin using clock. as data is shifted out, the patterns for the next test can be shifted in via the tdi pin. in the update phase, data is transferred from the capture to the update registers using the update clock. the data stored in the update registers can be used for the ex test instruction.
altera corporation 9?13 january 2008 stratix ii device handbook, volume 2 ieee 1149.1 (jtag) boundary-scan testin g for stratix ii and stratix ii gx devices during the capture phase, multiplex ers preceding the capture registers select the active device data signals. this data is then clocked into the capture registers. the multiplexers at the outputs of the update registers also select active device data to pr event functional interruptions to the device. during the shift phase, the bo undary-scan shift register is formed by clocking data through capture registers around the device periphery and then out of the tdo pin. the device can simultaneously shift new test data into tdi and replace the contents of th e capture registers. during the update phase, data in the capture re gisters is transferred to the update registers. this data can then be used in the extest instruction mode. refer to ?extest instruction mode? on page 9?13 for more information. figure 9?9 shows the sample/preload waveforms. the sample/preload instruction code is shifted in through the tdi pin. the tap controller advances to the capture_dr state and then to the shift_dr state, where it remains if tms is held low. the data that was present in the capture registers after the capture phase is shifted out of the tdo pin. new test data shifted into the tdi pin appears at the tdo pin after being clocked through the entire boundary-scan register. figure 9?9 shows that the instruction code at tdi does not appear at the tdo pin until after the capture register data is shifted out. if tms is held high on two consecutive tck clock cycles, the tap co ntroller advances to the update_dr state for the update phase. figure 9?9. sample/prelo ad shift data register waveforms extest instruction mode the extest instruction mode is used primarily to check external pin connections between devices. unlike the sample/preload mode, extest allows test data to be forced onto the pin signals. by forcing known logic high and low levels on output pins, opens and shorts can be detected at pins of any device in the scan chain. data stored in boundary-scan register is shifted out of tdo. after boundary-scan register data has been shifted out, data entered into tdi will shift out of tdo. update_ir shift_dr exit1_dr select_dr capture_dr exit1_ir update_dr shift_ir instruction code tck tms tdi tdo tap_state
9?14 altera corporation stratix ii device handbook, volume 2 january 2008 ieee std. 1149.1 bst operation control figure 9?10 shows the capture, shift, and update phases of the extest mode. figure 9?10. ieee std. 1149.1 bst extest mode 1 0 dq dq 1 0 1 0 1 0 dq dq 1 0 dq dq 1 0 outj oej mode inj capture registers update registers sdi shift clock update sdo 1 0 dq dq 1 0 1 0 1 0 dq dq 1 0 dq dq 1 0 outj oej mode inj capture registers update registers sdi shift clock update sdo capture phase in the capture phase, the signals at the pin, oej and outj, are loaded into the capture registers. the clock signals is supplied by the tap controller?s clockdr output. previously retained data in the update registers drive the pin_in, inj, and allows the i/o pin to tri-state or drive a signal out. a ?1? in the oej update register tri-states the output buffer. shift and update phases in the shift pha se, the previously captured signals at the pin, oej and outj, are shifted out of the boundary-scan register via the tdo pin using clock. as data is shifted out, the patterns for the next test can be shifted in via the tdi pin. in the update phase, data is transferred from the capture registers to the update registers using the update clock. the update registers then drive the pin_in, inj, and allow the i/o pin to tri-state or drive a signal out.
altera corporation 9?15 january 2008 stratix ii device handbook, volume 2 ieee 1149.1 (jtag) boundary-scan testin g for stratix ii and stratix ii gx devices extest selects data differently than sample/preload . extest chooses data from the update registers as the source of the output and output enable signals. once the extest instruction code is entered, the multiplexers select the update register data. thus, data stored in these registers from a previous extest or sample/preload test cycle can be forced onto the pin signals. in the capt ure phase, the results of this test data are stored in the capture registers and then shifted out of tdo during the shift phase. new test data can then be stored in the update registers during the update phase. the extest waveform diagram in figure 9?11 resembles the sample/preload waveform diagram, except for the instruction code. the data shifted out of tdo consists of the data that was present in the capture registers after the capture phase. new test data shifted into the tdi pin appears at the tdo pin after being clocked through the entire boundary-scan register. figure 9?11. extest shift data register waveforms bypass instruction mode the bypass mode is activated when an instruction code of all ones is loaded in the instruction register. the waveforms in figure 9?12 show how scan data passes through a device once the tap controller is in the shift_dr state. in this state, data si gnals are clocked into the bypass register from tdi on the rising edge of tck and out of tdo on the falling edge of the same clock pulse. data stored in boundary-scan register is shifted out of tdo. after boundary-scan register data has been shifted out, data entered into tdi will shift out of tdo. update_ir shift_dr exit1_dr select_dr capture_dr exit1_ir update_dr shift_ir instruction code tck tms tdi tdo tap_state
9?16 altera corporation stratix ii device handbook, volume 2 january 2008 ieee std. 1149.1 bst operation control figure 9?12. bypass shift data register waveforms idcode instruction mode the idcode instruction mode is used to identify the devices in an ieee std. 1149.1 chain. when idcode is selected, the device identification register is loaded with the 32-bit ve ndor-defined identification code. the device id register is connected between the tdi and tdo ports, and the device idcode is shifted out. f for more information on the idcode for stratix ii and stratix ii gx devices refer to the configuration & testing chapter in volume 1 of the stratix ii device handbook , or the configuration & testing chapter in volume 1 of the stratix ii gx device handbook. usercode instruction mode the usercode instruction mode is used to examine the user electronic signature (ues) within the devices alon g an ieee std. 1149.1 chain. when this instruction is selected, the device identification register is connected between the tdi and tdo ports. the user-defined ues is shifted into the device id register in parallel from the 32-bit usercode register. the ues is then shifted out through the device id register. 1 the ues value is not user defined until after the device is configured. before configuration, the ues value is set to the default value. data shifted into tdi on the rising edge of tck is shifted out of tdo on the falling edge of the same tck pulse. update_ir select_dr_scan capture_dr exit1_ir exit1_dr update_dr shift_dr instruction code tck tms tdi tdo tap_state shift_ir bit 2 bit 3 bit 1 bit 2 bit 4 bit 1
altera corporation 9?17 january 2008 stratix ii device handbook, volume 2 ieee 1149.1 (jtag) boundary-scan testin g for stratix ii and stratix ii gx devices clamp instruction mode the clamp instruction mode is used to allow the state of the signals driven from the pins to be determin ed from the boundary-scan register while the bypass register is select ed as the serial path between the tdi and tdo ports. the state of all signals driven from the pins are completely defined by the data held in the boundary-scan register. 1 if you are testing after configuring the device, the programmable weak pull -up resister or the bus hold feature overrides the clamp value (the value stored in the update register of the boundary-scan cell) at the pin. highz instruction mode the highz instruction mode sets all of th e user i/o pins to an inactive drive state. these pins are tri-stated until a new jtag instruction is executed. when this instruction is lo aded into the instruction register, the bypass register is connected between the tdi and tdo ports. 1 if you are testing after configuring the device, the programmable weak pull -up resistor or the bus hold feature overrides the highz value at the pin. i/o voltage support in jtag chain the jtag chain supports several devices. however, you should use caution if the chain contains devices that have different v ccio levels. the output voltage level of the tdo pin must meet the specifications of the tdi pin it drives. the tdi pin is powered by v ccpd (3.3 v). for stratix ii and stratix ii gx devices, the v ccio power supply of bank 4 powers the tdo pin. table 9?3 shows board design recommendations to ensure proper jtag chain operation. you can interface the tdi and tdo lines of the devices that have different v ccio levels by inserting a level shifter between the devices. if possible, you should build the jtag chain in such a way that a device with a higher v ccio level drives to a device with an equal or lower v ccio level. this way, a level shifter is used only to shift the tdo level to a level acceptable to the jtag tester. figure 9?13 shows the jtag chain of mixed voltages and how a level shifter is inserted in the chain.
9?18 altera corporation stratix ii device handbook, volume 2 january 2008 i/o voltage support in jtag chain figure 9?13. jtag chain of mixed voltages table 9?3. supported tdo/tdi voltage combinations device tdi input buffer power stratix ii and stratix ii gx tdo v ccio voltage level in i/o bank 4 v ccio = 3.3 v v ccio = 2.5 v v ccio = 1.8 v v ccio = 1.5 v stratix ii and stratix ii gx always v ccpd (3.3v) v (1) v (2) v (3) level shifter required non-stratix ii vcc = 3.3 v v (1) v (2) v (3) level shifter required vcc = 2.5 v v (1) , (4) v (2) v (3) level shifter required vcc = 1.8 v v (1) , (4) v (2) , (5) v level shifter required vcc = 1.5 v v (1) , (4) v (2) , (5) v (6) v notes to ta b l e 9 ? 3 : (1) the tdo output buffer meets v oh (min) = 2.4 v. (2) the tdo output buffer meets v oh (min) = 2.0 v. (3) an external 250- ? pull-up resistor is not required, but recommended if signal levels on the board are not optimal. (4) input buffer must be 3.3-v tolerant. (5) input buffer must be 2.5-v tolerant. (6) input buffer must be 1.8-v tolerant. 3.3 v v ccio level shifter 2.5 v v ccio 1.8 v v ccio 1.5 v v ccio tester tdo tdi must be 3.3 v tolerant. shift tdo to level accepted by tester if necessary. must be 1.8 v tolerant. must be 2.5 v tolerant.
altera corporation 9?19 january 2008 stratix ii device handbook, volume 2 ieee 1149.1 (jtag) boundary-scan testin g for stratix ii and stratix ii gx devices using ieee std. 1149.1 bst circuitry stratix ii and stratix ii gx devices have dedicated jtag pins and the ieee std. 1149.1 bst circ uitry is enabled upon device power-up. not only can you perform bst on stratix ii and stratix ii gx fpgas before and after, but also during configuratio n. stratix ii and stratix ii gx fpgas support the bypass , idcode and sample instructions during configuration without interrupting conf iguration. to send all other jtag instructions, you must interrupt configuration using the config_io instruction. the config_io instruction allows you to configure i/o buffers via the jtag port, and when issued, interrupts configuration. this instruction allows you to perform board-level testing prior to configuring the stratix ii or the stratix ii gx fpga or you can wait for the configuration device to complete configuration. on ce configuration is interrupted and jtag bst is complete, you must reconfigure the part via jtag ( pulse_config instruction) or by pulsing nconfig low. 1 when you perform jtag boundary-scan testing before configuration, the nconfig pin must be held low. the chip-wide reset ( dev_clrn ) and chip-wide output enable ( dev_oe ) pins on stratix ii and stratix ii gx devices do not affect jtag boundary-scan or configuration operat ions. toggling these pins does not disrupt bst operation (other than the expected bst behavior). when you design a board for jtag configuration of stratix ii or stratix ii gx devices, you need to consider the conn ections for the dedicated configuration pins. f for more information on using the ie ee std.1149.1 circuitry for device configuration, refer to the configuring stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii device handbook or the configuring stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook . bst for configured devices for a configured device, the input buffers are turned off by default for i/o pins that are set as output only in the design file. you cannot sample on the configured device output pins with the default bsdl file when the input buffers are turned off. you can set the quartus ii software to always enable the input buffers on a configured device so it behaves the same as an unconfigured device for boundary-scan testing, allowing sample function on output pins in the de sign. this aspect can cause slight increase in standby current because th e unused input buff er is always on. in the quartus ii software, do the following: 1. choose settings (assignments menu).
9?20 altera corporation stratix ii device handbook, volume 2 january 2008 disabling ieee std. 1149.1 bst circuitry 2. click assembler . 3. turn on always enable input buffers . disabling ieee std. 1149.1 bst circuitry the ieee std. 1149.1 bst circuitry fo r stratix ii and stratix ii gx devices is enabled upon device power-up. because the ieee std. 1149.1 bst circuitry is used for bst or in-circuit reconfiguration, you must enable the circuitry only at specific times as mentioned in, ?using ieee std. 1149.1 bst circuitry? on page 9?19 . 1 if you are not using the ieee std. 1149.1 circuitry in stratix ii or stratix ii gx, then you should pe rmanently disable the circuitry to ensure that you do not inadve rtently enable when it is not required. table 9?4 shows the pin connections necess ary for disabling the ieee std. 1149.1 circuitry in stratix ii and stratix ii gx devices. guidelines for ieee std. 1149.1 boundary-scan testing use the following guidelines when performing boundary-scan testing with ieee std. 1149.1 devices: if the ?10...? pattern does not shift out of the instruction register via the tdo pin during the firs t clock cycle of the shift_ir state, the tap controller did not reach the proper state. to solve this problem, try one of the following procedures: verify that the tap controller has reached the shift_ir state correctly. to advance the tap controller to the shift_ir state, return to the reset state and send the code 01100 to the tms pin. table 9?4. disabling ieee std. 1149.1 circuitry jtag pins (1) connection for disabling tms v cc tck gnd tdi v cc tdo leave open trst gnd note to ta b l e 9 ? 4 : (1) there is no software option to disable jtag in stratix ii or stratix ii gx devices. the jtag pins are dedicated.
altera corporation 9?21 january 2008 stratix ii device handbook, volume 2 ieee 1149.1 (jtag) boundary-scan testin g for stratix ii and stratix ii gx devices check the connections to the v cc , gnd, jtag, and dedicated configuration pins on the device. perform a sample/preload test cycle prior to the first extest test cycle to ensure that known data is present at the device pins when you enter the extest mode. if the oej update register contains a 0, the data in the outj update register is driven out. the state must be known and correct to avoid contention with other devices in the system. do not perform extest testing during icr. this instruction is supported before or after icr, but not during icr. use the config_io instruction to interrupt configuration and then perform testing, or wait for configuration to complete. if performing testing before configuration, hold nconfig pin low. after configuration, an y pins in a differential pin pair cannot be tested. therefore, performing bst after configuration requires editing of bsc group defi nitions that correspond to these differential pin pairs. the bsc group should be redefined as an internal cell. 1 refer to the boundary-scan description language (bsdl) file for more information on editing. f for more information on boundary scan testing, contact altera applications group. boundary-scan description language (bsdl) support the boundary-scan description lang uage (bsdl), a subset of vhdl, provides a syntax that allows you to de scribe the features of an ieee std. 1149.1 bst-capable device that can be tested. test software development systems then use the bsdl files for test generation, analysis, and failure diagnostics. f for more information, or to receive bsdl files for ieee std. 1149.1-compliant stratix ii and stratix i i gx devices, visit the altera web site at www.altera.com . conclusion the ieee std. 1149.1 bst circuitry av ailable in stratix ii and stratix ii gx devices provides a cost-effective and efficient way to test systems that contain devices with tight lead spacin g. circuit boards with altera and other ieee std. 1149.1-comp liant devices can use the extest , sample/preload , and bypass modes to create serial patterns that internally test the pin connections between devices and check device operation.
9?22 altera corporation stratix ii device handbook, volume 2 january 2008 references references bleeker, h., p. van den eijnden, and f. de jong. boundary-scan test: a practical approach . eindhoven, the netherla nds: kluwer academic publishers, 1993. institute of electrical and electronics engineers, inc. ieee standard test access port and boundary-scan architecture (ieee std 1149.1-2001). new york: institute of electrical and electronics engineers, inc., 2001. maunder, c. m., and r. e. tulloss. the test access port and boundary-scan architecture . los alamitos: ieee comp uter society press, 1990. referenced documents this chapter references the following documents: configuration & testing chapter in volume 1 of the stratix ii device handbook configuration & testing chapter in volume 1 of the stratix ii gx device handbook configuring stratix ii & stratix ii gx de vices chapter in volume 2 of the stratix ii device handbook configuring stratix ii & stratix ii gx devices chapter in volume 2 of the stratix ii gx device handbook document revision history table 9?5 shows the revision history for this chapter. table 9?5. document revision history (part 1 of 2) date and document version changes made summary of changes january 2008, v3.3 added ?referenced documents? section. ? minor text edits. ? no change for the stratix ii gx device handbook only: formerly chapter 14. the chapter number changed due to the addition of the stratix ii gx dynamic reconfiguration chapter. no content change. ? february 2007 v3.2 added the ?document revision history? section to this chapter. ? april 2006, v3.1 chapter updated as part of the stratix ii device handbook update. ?
altera corporation 9?23 january 2008 stratix ii device handbook, volume 2 ieee 1149.1 (jtag) boundary-scan testin g for stratix ii and stratix ii gx devices no change formerly chapter 13. chapter number change only due to chapter addition to section i in february 2006; no content change. ? october 2005 v3.0 added chapter to the stratix ii gx device handbook . ? table 9?5. document revision history (part 2 of 2) date and document version changes made summary of changes
9?24 altera corporation stratix ii device handbook, volume 2 january 2008 document revision history
altera corporation section vi?1 preliminary section vi. pcb layout guidelines this section provides informatio n for board layout designers to successfully layout th eir boards for stratix ? ii devices. these chapters contain the required pcb layout guidelines and package specifications. this section contains the following chapters: chapter 10, package information for stratix ii & stratix ii gx devices chapter 11, high-speed board layout guidelines revision history refer to each chapter for its own specific revision history. for information on when each chapter was updated, refer to the chapter revision dates section, which appears in the full handbook.
section vi?2 altera corporation preliminary pcb layout guidelines stratix ii device handbook, volume 2
altera corporation 10?1 may 2007 10. package information for stratix ii & stratix ii gx devices introduction this chapter provides pack age information for altera ? stratix ? ii and stratix ii gx devices, including: device and package cross reference thermal resistance values package outlines tables 10?1 and 10?2 show which altera stratix ii and stratix ii gx devices, respectively, are available in fineline bga ? (fbga) packages. table 10?1. stratix ii devices in fbga packages device package pins ep2s15 flip-chip fbga 484 flip-chip fbga 672 ep2s30 flip-chip fbga 484 flip-chip fbga 672 ep2s60 flip-chip fbga 484 flip-chip fbga 672 flip-chip fbga 1,020 ep2s90 flip-chip fbga 484 flip-chip fbga 780 flip-chip fbga 1,020 flip-chip fbga 1,508 ep2s130 flip-chip fbga 780 flip-chip fbga 1,020 flip-chip fbga 1,508 ep2s180 flip-chip fbga 1,020 flip-chip fbga 1,508 sii52010-4.3
10?2 altera corporation stratix ii gx device handbook, volume 2 may 2007 thermal resistance thermal resistance thermal resistance values for stratix ii devices are provided for a board that meets jdec specifications and for a typical board. the following values are provided: ? ja (c/w) still air?junction-to-ambi ent thermal resistance with no air flow when a heat sink is not used. ? ja (c/w) 100 ft./min.?junction-to-ambient thermal resistance with 100 ft./min. airflow when a heat sink is not used. ? ja (c/w) 200 ft./min.?junction-to-ambient thermal resistance with 200 ft./min. airflow when a heat sink is not used. ? ja (c/w) 400 ft./min.?junction-to-ambient thermal resistance with 400 ft./min. airflow when a heat sink is not used. ? jc ?junction-to-case thermal resistance for device. ? jb ?junction-to-board thermal resistance for device. tables 10?3 provides ? ja (junction-to-ambient thermal resistance), ? jc (junction-to-case thermal resistance), and ? jb (junction-to-board thermal resistance) values for stratix ii devices on a board meeting jedec specifications for thermal resistance calculation. the jedec board specifications require two signal an d two power/ground planes and are available at www.jedec.org . table 10?2. stratix ii gx devices in fbga packages device package pins ep2sgx30 flip-chip fbga 780 ep2sgx60 flip-chip fbga 780 flip-chip fbga 1,152 ep2sgx90 flip-chip fbga 1,152 flip-chip fbga 1,508 ep2sgx130 flip-chip fbga 1,508 table 10?3. stratix ii device thermal resistance for b oards meeting jedec spec ifications (part 1 of 2) device pin count package ? ja ( c/w) still air ? ja ( c/w) 100 ft./min. ? ja ( c/w) 200 ft./min. ? ja ( c/w) 400 ft./min. ? jc ( c/w) ? jb ( c/w) ep2s15 484 fbga 13.1 11.1 9.6 8.3 0.36 4.19 672 fbga 12.2 10.2 8.8 7.6 0.36 4.09 ep2s30 484 fbga 12.6 10.6 9.1 7.9 0.21 3.72 672 fbga 11.7 9.7 8.3 7.1 0.21 3.35
altera corporation 10?3 may 2007 stratix ii gx device handbook, volume 2 package information for stratix ii & stratix ii gx devices table 10?4 provides ? ja (junction-to-ambient thermal resistance), ? jc (junction-to-case thermal resistance), and ? jb (junction-to-board thermal resistance) values for stratix ii devices on a board with the information shown in table 10?5 . ep2s60 484 fbga 12.3 10.3 8.8 7.5 0.13 3.38 672 fbga 11.4 9.4 7.8 6.7 0.13 2.95 1,020 fbga 10.4 8.4 7.0 5.9 0.13 2.67 ep2s90 484 hybrid fbga 12.0 9.9 8.3 7.1 0.07 3.73 780 fbga 10.8 8.8 7.3 6.1 0.09 2.59 1,020 fbga 9.2 8.2 6.8 5.7 0.10 2.41 1,508 fbga 9.3 7.4 6.1 5.0 0.10 2.24 ep2s130 780 fbga 10.1 8.7 7.2 6.0 0.07 2.44 1,020 fbga 9.5 8.1 6.7 5.5 0.07 2.24 1,508 fbga 8.6 7.3 6.0 4.8 0.07 2.08 ep2s180 1,020 fbga 9.0 7.9 6.5 5.4 0.05 2.10 1,508 fbga 8.1 7.1 5.8 4.7 0.05 1.94 table 10?3. stratix ii device thermal resistance for b oards meeting jedec spec ifications (part 2 of 2) device pin count package ? ja ( c/w) still air ? ja ( c/w) 100 ft./min. ? ja ( c/w) 200 ft./min. ? ja ( c/w) 400 ft./min. ? jc ( c/w) ? jb ( c/w) table 10?4. stratix ii device thermal resi stance for typical board (part 1 of 2) device pin count package ? ja ( c/w) still air ? ja ( c/w) 100 ft./min. ? ja ( c/w) 200 ft./min. ? ja ( c/w) 400 ft./min. ? jc ( c/w) ? jb ( c/w) ep2s15 484 fbga 12.6 9.9 8.1 6.7 0.36 2.48 672 fbga 11.4 8.8 7.2 5.9 0.36 2.41 ep2s30 484 fbga 12.3 9.6 7.8 6.4 0.21 2.02 672 fbga 11.1 8.5 6.9 5.6 0.21 1.95 ep2s60 484 fbga 12.1 9.4 7.6 6.3 0.13 1.74 672 fbga 10.9 8.3 6.6 5.4 0.13 1.56 1,020 fbga 9.6 7.1 5.6 4.5 0.13 1.33 ep2s90 484 hybrid fbga 11.2 8.9 7.2 5.9 0.07 2.48 780 fbga 10.0 7.6 6.1 4.9 0.09 1.22 1,020 fbga 9.2 6.9 5.5 4.4 0.10 1.16 1,508 fbga 8.2 6.0 4.7 3.7 0.10 1.15
10?4 altera corporation stratix ii gx device handbook, volume 2 may 2007 thermal resistance table 10?6 provides ? ja (junction-to-ambient thermal resistance) and ? jc (junction-to-case thermal resistance) values for stratix ii devices. ep2s130 780 fbga 9.3 7.5 6.0 4.8 0.07 1.12 1,020 fbga 8.5 6.8 5.3 4.2 0.07 1.03 1,508 fbga 7.5 5.8 4.6 3.6 0.07 1.02 ep2s180 1,020 fbga 8.0 6.7 5.3 4.2 0.05 0.93 1,508 fbga 7.1 5.7 4.5 3.5 0.05 0.91 table 10?4. stratix ii device thermal resi stance for typical board (part 2 of 2) device pin count package ? ja ( c/w) still air ? ja ( c/w) 100 ft./min. ? ja ( c/w) 200 ft./min. ? ja ( c/w) 400 ft./min. ? jc ( c/w) ? jb ( c/w) table 10?5. board specifications notes (1) , (2) pin count package signal layers power/ground layers size (mm) 1,508 fbga 12 12 100 100 1,020 fbga 10 10 93 93 780 fbga 9 9 89 89 672 fbga 8 8 87 87 484 fbga 7 7 83 83 notes to ta b l e 1 0 ? 5 : (1) power layer cu thickness 35 um, cu 90%. (2) signal layer cu thickness 17 um, cu 15%. table 10?6. stratix ii gx de vice thermal resistance device pin count package ? ja ( c/w) still air ? ja ( c/w) 100 ft./min. ? ja ( c/w) 200 ft./min. ? ja ( c/w) 400 ft./min. ? jc ( c/w) ep2sgx30 780 fbga 11.1 8.6 7.2 6.0 0.24 ep2sgx60 780 fbga 10.9 8.4 6.9 5.8 0.15 1,152 fbga 9.9 7.5 6.1 5.0 0.15 ep2sgx90 1,152 fbga 9.6 7.3 5.9 4.9 0.11 1,508 fbga 9.0 6.7 5.4 4.4 0.11 ep2sgx130 1,508 fbga 8.3 6.6 5.3 4.3 0.10
altera corporation 10?5 may 2007 stratix ii gx device handbook, volume 2 package information for stratix ii & stratix ii gx devices package outlines the package outlines are listed in or der of ascending pin count. altera package outlines meet the requirements of jedec publication no. 95. 484-pin fbga - flip chip all dimensions and tolerances conform to asme y14.5m ? 1994. controlling dimension is in millimeters. pin a1 may be indicated by an id dot, or a special feature, in its proximity on the package surface. tables 10?7 and 10?8 show the package information and package outline figure references, respectively , for the 484-pin fbga packaging. table 10?7. 484-pin fbga package information description specification ordering code reference f package acronym fbga substrate material bt solder ball composition regular: 63sn:37pb (typ.) pb-free: sn:3ag:0.5cu (typ.) jedec outline reference ms-034 variation: aaj-1 maximum lead coplanarity 0.008 inches (0.20 mm) weight 5.8 g moisture sensitivity level p rinted on moisture barrier bag table 10?8. 484-pin fbga package outline dimensions (part 1 of 2) symbol millimeter min. nom. max. a??3.50 a1 0.30 ? ? a2 0.25 ? 3.00 a3 ? ? 2.50 d 23.00 bsc e 23.00 bsc
10?6 altera corporation stratix ii gx device handbook, volume 2 may 2007 package outlines figure 10?1 shows a package outline for the 484-pin fineline bga packaging. figure 10?1. 484-pin fbga package outline 672-pin fbga - flip chip all dimensions and tolerances conform to asme y14.5m - 1994. controlling dimension is in millimeters. pin a1 may be indicated by an id dot, or a special feature, in its proximity on package surface. b 0.50 0.60 0.70 e 1.00 bsc table 10?8. 484-pin fbga package outline dimensions (part 2 of 2) symbol millimeter min. nom. max. d a1 a3 a2 a e e e b pin a1 id pin a1 corner bottom view top view
altera corporation 10?7 may 2007 stratix ii gx device handbook, volume 2 package information for stratix ii & stratix ii gx devices tables 10?9 and 10?10 show the package inform ation and package outline figure references, respectively , for the 672-pin fbga packaging. table 10?9. 672-pin fbga package information description specification ordering code reference f package acronym fbga substrate material bt solder ball composition regular: 63sn:37pb (typ.) pb-free: sn:3ag:0.5cu (typ.) jedec outline reference ms-034 variation: aal-1 maximum lead coplanarity 0.008 inches (0.20 mm) weight 7.7 g moisture sensitivity level printed on moisture barrier bag table 10?10. 672-pin fbga package outline dimensions symbol millimeters min. nom. max. a??3.50 a1 0.30 ? ? a2 0.25 ? 3.00 a3 ? ? 2.50 d 27.00 bsc e 27.00 bsc b 0.50 0.60 0.70 e 1.00 bsc
10?8 altera corporation stratix ii gx device handbook, volume 2 may 2007 package outlines figure 10?2 shows a package outline for the 672-pin fineline bga packaging. figure 10?2. 672-pin fbga package outline e d e e a1 a2 b a3 a pin a1 id pin a1 corner bottom view top view
altera corporation 10?9 may 2007 stratix ii gx device handbook, volume 2 package information for stratix ii & stratix ii gx devices 780-pin fbga - flip chip all dimensions and tolerances conform to asme y14.5m - 1994. controlling dimension is in millimeters. pin a1 may be indicated by an id dot, or a special feature, in its proximity on package surface. tables 10?11 and 10?12 show the package information and package outline figure references, respective ly, for the 780-pin fbga packaging. table 10?11. 780-pin fbga package information description specification ordering code reference f package acronym fbga substrate material bt solder ball composition regular: 63sn:37pb (typ.) pb-free: sn:3ag:0.5cu (typ.) jedec outline reference ms-034 variation: aam-1 maximum lead coplanarity 0.008 inches (0.20 mm) weight 8.9 g moisture sensitivity level printed on moisture barrier bag table 10?12. 780-pin fbga package outline dimensions symbol millimeters min. nom. max. a??3.50 a1 0.30 ? ? a2 0.25 ? 3.00 a3 ? ? 2.50 d 29.00 bsc e 29.00 bsc b 0.50 0.60 0.70 e 1.00 bsc
10?10 altera corporation stratix ii gx device handbook, volume 2 may 2007 package outlines figure 10?3 shows a package outline for the 780-pin fineline bga packaging. figure 10?3. 780-pin fbga package outline pin a1 id pin a1 corner bottom view top view e d e e a1 a2 b a3 a
altera corporation 10?11 may 2007 stratix ii gx device handbook, volume 2 package information for stratix ii & stratix ii gx devices 1,020-pin fbga - flip chip all dimensions and tolerances conform to asme y14.5m - 1994. controlling dimension is in millimeters. pin a1 may be indicated by an id dot, or a special feature, in its proximity on package surface. tables 10?13 and 10?14 show the package information and package outline figure references, respective ly, for the 1,020-pin fbga packaging. table 10?13. 1,020-pin fbga package information description specification ordering code reference f package acronym fbga substrate material bt solder ball composition regular: 63sn:37pb (typ.) pb-free: sn:3ag:0.5cu (typ.) jedec outline reference ms-034 variation: aap-1 maximum lead coplanarity 0.008 inches (0.20 mm) weight 11.5 g moisture sensitivity level printed on moisture barrier bag table 10?14. 1,020-pin fbga package outline dimensions symbol millimeters min. nom. max. a??3.50 a1 0.30 ? ? a2 0.25 ? 3.00 a3 ? ? 2.50 d 33.00 bsc e 33.00 bsc b 0.50 0.60 0.70 e 1.00 bsc
10?12 altera corporation stratix ii gx device handbook, volume 2 may 2007 package outlines figure 10?4 shows a package outline fo r the 1,020-pin fineline bga packaging. figure 10?4. 1,020-pin fbga package outline d e pin a1 id b e e a3 a1 a2 pin a1 corner a bottom view top view
altera corporation 10?13 may 2007 stratix ii gx device handbook, volume 2 package information for stratix ii & stratix ii gx devices 1,152-pin fbga - flip chip all dimensions and tolerances conform to asme y14.5m - 1994. controlling dimension is in millimeters. pin a1 may be indicated by an id dot, or a special feature, in its proximity on package surface. tables 10?15 and 10?16 show the package information and package outline figure references, respective ly, for the 1,152-pin fbga packaging. table 10?15. 1,152-pin fbga package information description specification ordering code reference f package acronym fbga substrate material bt solder ball composition regular: 63sn:37pb (typ.) pb-free: sn:3ag:0.5cu (typ.) jedec outline reference ms-034 variation: aar-1 maximum lead coplanarity 0.008 inches (0.20 mm) weight 12.0 g moisture sensitivity level printed on moisture barrier bag table 10?16. 1,152-pin fbga package outline dimensions symbol millimeters min. nom. max. a??3.50 a1 0.30 ? ? a2 0.25 ? 3.00 a3 ? ? 2.50 d 35.00 bsc e 35.00 bsc b 0.50 0.60 0.70 e 1.00 bsc
10?14 altera corporation stratix ii gx device handbook, volume 2 may 2007 package outlines figure 10?5 shows a package outline fo r the 1,152-pin fineline bga packaging. figure 10?5. 1,152-pin fbga package outline bottom view top view e d pin a1 id a2 a3 a1 a pin a1 corner e b e
altera corporation 10?15 may 2007 stratix ii gx device handbook, volume 2 package information for stratix ii & stratix ii gx devices 1,508-pin fbga - flip chip all dimensions and tolerances conform to asme y14.5m - 1994. controlling dimension is in millimeters. pin a1 may be indicated by an id dot, or a special feature, in its proximity on package surface. tables 10?17 and 10?18 show the package information and package outline figure references, respective ly, for the 1,508-pin fbga packaging. table 10?17. 1,508-pin fbga package information description specification ordering code reference f package acronym fbga substrate material bt solder ball composition regular: 63sn:37pb (typ.) pb-free: sn:3ag:0.5cu (typ.) jedec outline reference ms-034 variation: aau-1 maximum lead coplanarity 0.008 inches (0.20 mm) weight 14.6 g moisture sensitivity level printed on moisture barrier bag table 10?18. 1,508-pin fbga package outline dimensions symbol millimeters min. nom. max. a??3.50 a1 0.30 ? ? a2 0.25 ? 3.00 a3 ? ? 2.50 d 40.00 bsc e 40.00 bsc b 0.50 0.60 0.70 e 1.00 bsc
10?16 altera corporation stratix ii gx device handbook, volume 2 may 2007 package outlines figure 10?6 shows a package outline fo r the 1,508-pin fineline bga packaging. figure 10?6. 1,508-pin fbga package outline pin a1 corner b e e d pin a1 id a2 a3 a1 a e top view bottom view
altera corporation 10?17 may 2007 stratix ii gx device handbook, volume 2 package information for stratix ii & stratix ii gx devices document revision history table 10?19 shows the revision hi story for this chapter. table 10?19. document revision history date and document version changes made summary of changes no change for the stratix ii gx device handbook only: formerly chapter 15. the chapter number changed due to the addition of the stratix ii gx dynamic reconfiguration chapter. no content change. ? may 2007, v4.3 minor change to table 10?3 .? february 2007 v4.2 added the ?document revision history? section to this chapter. ? no change formerly chapter 14. chapter number change only due to chapter addition to section i in february 2006; no content change. ? december 2005, v4.1 chapter updated as part of the stratix ii device handbook update. ? october 2005 v4.0 added chapter to the stratix ii gx device handbook .?
10?18 altera corporation stratix ii gx device handbook, volume 2 may 2007 document revision history
altera corporation 11?1 may 2007 11. high-speed board layout guidelines introduction printed circuit board (pcb) layout be comes more complex as device pin density and system frequency increa se. a successful high-speed board must effectively integrate devices and other elements while avoiding signal transmission problems associat ed with high-speed i/o standards. because altera ? devices include a variety of high-speed features, including fast i/o pins and edge rates less than one hundred picoseconds, it is imperative that an effective design successfully: reduces system noise by filtering and evenly distributing power to all devices matches impedance and terminates the signal line to diminish signal reflection minimizes crosstalk between parallel traces reduces the effects of ground bounce this chapter provides guidelines for effective high-speed board design using altera devices and discusses the following issues: pcb material selection transmission line layouts routing schemes for minimizing cr osstalk and maintaining signal integrity termination schemes simultaneous switching noise (ssn) electromagnetic interference (emi) additional fpga-specific board design/signal integrity information pcb material selection fast edge rates contribute to noise and crosstalk, depending on the pcb dielectric construction material. diel ectric material can be assigned a dielectric constant ( ? r ) that is related to the force of attraction between two opposite charges se parated by a distance in a uniform medium as follows: f = q 1 q 2 4 r 2 sii52012-1.4
11?2 altera corporation stratix ii device handbook, volume 2 may 2007 pcb material selection where: q 1 , q 2 = charges r = distance between the charges (m) f = force (n) = permittivity of dielectric ( f /m). each pcb substrate has a different relative dielectric constant. the dielectric constant is the ratio of the permittivity of a substance to that of free space, as follows: where: r = dielectric constant o = permittivity of empty space ( f /m) = permittivity ( f /m) the dielectric constant compares th e effect of an insulator on the capacitance of a conductor pair, with the capacitance of the conductor pair in a vacuum. the dielectric co nstant affects the impedance of a transmission line. signals can propagat e faster in materials that have a lower dielectric constant. a high-frequency signal that propagat es through a long line on the pcb from driver to receiver is severely affected by the loss tangent of the dielectric material. a large loss tangent means higher dielectric absorption. the most widely used dielectric ma terial for pcbs is fr-4, a glass laminate with epoxy resin that m eets a wide variety of processing conditions. the dielectric constant for fr-4 is be tween 4.1 and 4.5. getek is another material that can be us ed in high-speed boards. getek is composed of epoxy and resin (polyphe nylene oxide) and has a dielectric constant between 3.6 and 4.2. ? r = ? ? ?
altera corporation 11?3 may 2007 stratix ii device handbook, volume 2 high-speed board layout guidelines table 11?1 shows the loss tangent value for fr-4 and getek materials. transmission line layout the transmission line is a trace and has a distributed mixture of resistance (r), inductance (l), and ca pacitance (c). there are two types of transmission line layouts, microstrip and stripline. figure 11?1 shows a microstrip transmission line layout, which refers to a trace routed as the top or bottom layer of a pcb and has one voltage-reference plane (power or ground). figure 11?2 shows a stripline transmission line layout, which uses a trace routed on the inside layer of a pcb and has two voltage-referenc e planes (power and/or ground). figure 11?1. microstrip tr ansmission line layout note (1) note to figure 11?1 : (1) w = width of trace, t = thickness of trace, and h = height between trace and reference plane. figure 11?2. stripline tr ansmission line layout note (1) note to figure 11?2 : (1) w = width of trace, t = thickness of trace, and h = height between trace and two reference planes. table 11?1. loss tangent value of fr-4 & getek materials manufacturer material loss tangent value ge electromaterials getek 0.010 @ 1 mhz isola laminate systems fr-4 0.019 @ 1 mhz w dialectric m aterial p ower/ g nd trace h t w d i e l ectr i c m ater i a l pow er /g r oun d h t race pow er /g r oun d t
11?4 altera corporation stratix ii device handbook, volume 2 may 2007 transmission line layout impedance calculation any circuit trace on the pcb has charac teristic impedance associated with it. this impedance is dependent on the width ( w ) of the trace, the thickness ( t ) of the trace, the dielectric co nstant of the material used, and the height ( h ) between the trace and reference plane. microstrip impedance a circuit trace routed on an outsid e layer of the pcb with a reference plane (gnd or v cc ) below it, constitutes a microstrip layout. use the following microstrip impedance equati on to calculate the impedance of a microstrip trace layout: using typical values of w = 8 mil, h = 5 mil, t = 1.4 mil, the dielectric constant, and (fr-4) = 4.1, with the microstrip impedance equation, solving for microstrip impedance (z o ) yields: 1 the measurement unit in the micr ostrip impedance equation is mils (i.e., 1 mil = 0.001 inches). also, copper (cu) trace thickness is usually measured in ounces for example, 1 oz = 1.4 mil). figure 11?3 shows microstrip trace impedance with changing trace width ( w ), using the values in the micros trip impedance equation, keeping dielectric height and tr ace thickness constant. z 0 = 87 r + 1.41 ln () 5.98 h 0.8 w + t z 0 = z 0 ~ 87 4.1 + 1.41 ln () 5.98 (5) 0.8(8) + 1.4 50
altera corporation 11?5 may 2007 stratix ii device handbook, volume 2 high-speed board layout guidelines figure 11?3. microstrip trace im pedance with changing trace width figure 11?4 shows microstrip trace impe dance with changing height, using the values in the microstrip impedance equation, keeping trace width and trace thickness constant. figure 11?4. microstrip trace impedance with changing height the impedance graphs show that the change in impedance is inversely proportional to trace width and directly proportional to trace height above the ground plane. 80 70 60 50 40 30 20 10 0 4 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9 z 0 w (mil) z 0 () t = 1.4 mils h = 5.0 mils 80 70 60 50 40 30 20 10 0 456789 h (mil) z 0 () 10 z 0 t = 1.4 mils w = 8.0 mils
11?6 altera corporation stratix ii device handbook, volume 2 may 2007 transmission line layout figure 11?5 plots microstrip trace impe dance with changing trace thickness using the values in the mi crostrip impedance equation, keeping trace width and dielectric height constant. figure 11?5 shows that as trace thickness increases, trace impedance decreases. figure 11?5. microstrip trace impedanc e with changing trace thickness stripline impedance a circuit trace routed on the inside layer of the pcb with two low-voltage reference planes (power and/or gnd) constitutes a stripline layout. you can use the following stripline impe dance equation to calculate the impedance of a stripline trace layout: using typical values of w = 9 mil, h = 24 mil, t = 1.4 mil, dielectric constant and (fr-4) = 4.1 with the stripline impedance equation and solving for stripline impedance (z o ) yields: figure 11?6 shows impedance with changing trace width using the stripline impedance equation, keeping height and thickness constant for stripline trace. 60 50 40 30 20 10 0 0.7 1.4 2.8 4.2 t (mil) z 0 ( ) z 0 h = 5.0 mils w = 8.0 mils z o = 60 r ln () 4 h 0.67 ( t + 0.8 w ) z o = 60 4.1 ln ( ) 4 ( 24 ) 0.67 (1.4) + 0.8(9) z o ~ 50
altera corporation 11?7 may 2007 stratix ii device handbook, volume 2 high-speed board layout guidelines figure 11?6. stripline trace imped ance with changing trace width figure 11?7 shows stripline trace impedanc e with changing dielectric height using the stripline impedance equation, keeping trace width and trace thickness constant. figure 11?7. stripline trace impedance with changing dielectric height as with the microstrip layout, th e stripline layout impedance also changes inversely proportional to line width and directly proportional to height. however, the rate of change with trace height above gnd is much slower in a stripline layout compared with a microstrip layout. a stripline layout has a signal sandwiched by fr-4 material, whereas a microstrip layout has one conductor open to ai r. this exposure causes a higher effective dielectric constant in stripline layouts compared with microstrip 80 70 60 50 40 30 20 10 0 4 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9 w (mil) z 0 ( ) 10 z 0 t = 1.4 mils h = 24.0 mils 80 70 60 50 40 30 20 10 0 16 20 24 28 32 36 h (mil) z 0 ( ) 40 44 z 0 t = 1.4 mils w = 9.0 mils
11?8 altera corporation stratix ii device handbook, volume 2 may 2007 transmission line layout layouts. thus, to achieve the same impe dance, the dielectric span must be greater in stripline layouts compared with microstrip layouts. therefore, stripline-layout pcbs with controlled impedance lines are thicker than microstrip-layout pcbs. figure 11?8 shows stripline trace impedance with changing trace thickness, using the stripline impe dance equation, keeping trace width and dielectric he ight constant. figure 11?8 shows that the characteristic impedance decreases as the trace thickness increases. figure 11?8. stripline trace impedanc e with changing trace thickness propagation delay propagation delay (t pd ) is the time required for a signal to travel from one point to another. transmission line pr opagation delay is a function of the dielectric constant of the material. microstrip layout propagation delay you can use the following equation to calculate the microstrip trace layout propagation delay: stripline layout propagation delay you can use the following equation to calculate the stripline trace layout propagation delay. 60 50 40 30 20 10 0 0.7 1.4 2.8 4.2 t (mil) z 0 ( ) z 0 h = 24.0 mils w = 9.0 mils t pd (microstrip) = 0.475 r + 0.67 85 t pd (stripline) = r 85
altera corporation 11?9 may 2007 stratix ii device handbook, volume 2 high-speed board layout guidelines figure 11?9 shows the propagation delay ve rsus the dielectric constant for microstrip and stripline traces. as the dielectric constant increases, the propagation delay also increases. figure 11?9. propagation delay versus dielectric constant for microstrip & stripline traces pre-emphasis typical transmission media like copper trace and coaxial cable have low-pass characteristics, so they a ttenuate higher frequencies more than lower frequencies. a typical digital signal that approximates a square wave contains high frequencies ne ar the switching region and low frequencies in the constant region. when this signal travels through low-pass media, its higher frequencies are attenuated more than the lower frequencies, resulting in increased signal rise times. consequently, the eye opening narrows and the pr obability of error increases. the high-frequency content of a signal is also degraded by what is called the ?skin effect.? the cause of skin effect is the high-frequency current that flows primarily on the surface (skin) of a conductor. the changing current distribution caus es the resistance to incr ease as a function of frequency. you can use pre-emphasis to compensate for the skin effect. by fourier analysis, a square wave si gnal contains an infinite number of frequencies. the high frequencies are located in the low-to-high and high-to-low transition regions and the low frequencie s are located in the flat (constant) regions. increasing the signal?s am plitude near the transition region emphasizes higher frequencies more than the lower frequencies. when this pre-emphasized signal passes through low-pass media, it will come out with minimal distortion, if you apply the correct amount of pre-emphasis (see figure 11?10 ). 300 250 200 150 100 50 0 12 34567 89 r t pd (ps/inch) microstrip stripline t = 1.4 z 0 = 50 w stripline = 9.0 mils w microstrip = 8.0 mils
11?10 altera corporation stratix ii device handbook, volume 2 may 2007 transmission line layout figure 11?10. input & output signal s with & without pre-emphasis |h (jw)| 1 w signal is attenuated at high frequencies. transmission line output v o (t) input v i (t) v i (t) v o (t) input signal approximates a square wave but has no pre-emphasis. output signal has higher rise time, and the eye opening is smaller. input signal has pre-emphasis. v i (t) v o (t) output signal has similar rise time and eye opening as input signal. t t t t
altera corporation 11?11 may 2007 stratix ii device handbook, volume 2 high-speed board layout guidelines stratix ? ii and stratix gx devices provide programmable pre-emphasis to compensate for variable lengths of transmission media. you can set the pre-emphasis to between 5 and 25 % , depending on the value of the output differential voltage (v od ) in the stratix gx device. table 11?2 shows the available stratix gx programmable pre-emphasis settings. routing schemes for minimizing crosstalk & maintaining signal integrity crosstalk is the unwanted coupling of signals between parallel traces. proper routing and layer stack-up through microstrip and stripline layouts can minimize crosstalk. to reduce crosstalk in dual-stripline layouts that have two signal layers next to each other, route all traces perpendicular, increase the distance between the two signal layers, and minimize the distance between the signal layer and the adjacent reference plane (see figure 11?11 ). table 11?2. programmable pre-emphasis with stratix gx devices v od pre-emphasis setting (%) 510152025 400 420 440 460 480 500 480 504 528 552 576 600 600 630 660 690 720 750 800 840 880 920 960 1,000 960 1,008 1,056 1,104 1,152 1,200 1,000 1,050 1,100 1,150 1,200 1,250 1,200 1,260 1,320 1,380 1,440 1,500 1,400 1,470 1,540 - - - 1,440 1,512 1,584 - - - 1,5001,575---- 1,600-----
11?12 altera corporation stratix ii device handbook, volume 2 may 2007 routing schemes for minimizing crosstalk & maintaining signal integrity figure 11?11. dual- and single-stripline layouts take the following actions to reduce crosstalk in either microstrip or stripline layouts: widen spacing between signal lines as much as routing restrictions will allow. try not to bring traces clos er than three times the dielectric height. design the transmission line so th at the conductor is as close to the ground plane as possible. this technique will couple the transmission line tightl y to the ground plane and help decouple it from adjacent signals. use differential routing techniques where possible, especially for critical nets (i.e., matc h the lengths as well as the turns that each trace goes through). if there is significant coupling, route single-ended signals on different layers orthogonal to each other. minimize parallel run lengths between single-ended signals. route with short parallel sections and minimize long, coupled sections between nets. crosstalk also increases when two or more single-ended traces run parallel and are not spaced far enou gh apart. the distance between the centers of two adjacent traces should be at least four times the trace width, as shown in figure 11?12 . to improve design performance, lower the distance between the trace and the gr ound plane to under 10 mils without changing the separation between the two traces. w w d i e l ectr i c m ater i a l g r oun d g r oun d h t race single-stripline layout dual-stripline layout
altera corporation 11?13 may 2007 stratix ii device handbook, volume 2 high-speed board layout guidelines figure 11?12. separating traces for crosstalk compared with high dielectric materials, low dielectric materials help reduce the thickness between th e trace and ground plane while maintaining signal integrity. figure 11?13 plots the relationship of height versus dielectric constant using the microstrip impedance and stripline impedance equations, keeping impedance, width, and thickness constant. figure 11?13. height versus dielectric constant signal trace routing proper routing helps to maintain signal integrity. to route a clean trace, you should perform simulation with good signal integrity tools. the following section describes the two different types of signal traces available for routing, single-ended tr aces, and differential pair traces. a 4a a 30 25 20 15 10 5 0 2.2 2.9 3.3 4.1 4.5 r h (mil) microstrip stripline t = 1.4 z 0 = 50 w stripline = 9.0 mils w microstrip = 8.0 mils
11?14 altera corporation stratix ii device handbook, volume 2 may 2007 routing schemes for minimizing crosstalk & maintaining signal integrity single-ended trace routing a single-ended trace connects the source and the load/receiver. single-ended traces are used in ge neral point-to-point routing, clock routing, low-speed, and non-critical i/o routing. this section discusses different routing schemes for clock signals. you can use the following types of routing to drive multip le devices with the same clock: daisy chain routing with stub without stub star routing serpentine routing use the following guidelines to impr ove the clock tran smission line?s signal integrity: keep clock traces as straight as possible. use arc-shaped traces instead of right-angle bends. do not use multiple signal layers for clock signals. do not use vias in clock transmission lines. vias can cause impedance change and reflection. place a ground plane next to the oute r layer to minimize noise. if you use an inner layer to route the cl ock trace, sandwich the layer between reference planes. terminate clock signals to minimize reflection. use point-to-point clock trac es as much as possible. daisy chain routing with stubs daisy chain routing is a common practice in designing pcbs. one disadvantage of daisy chain routing is that stubs, or short traces, are usually necessary to connect devices to the main bus (see figure 11?14 ). if a stub is too long, it will induce tran smission line reflections and degrade signal quality. therefore, the stub le ngth should not ex ceed the following conditions: td stub < (t 10 % to 90 % )/3 where td stub = electrical delay of the stub t 10 % to 90 % = rise or fall time of signal edge for a 1-ns rise-time edge, the stub leng th should be less than 0.5 inches (see the ?references? section). if your design uses multiple devices, all stub lengths should be equal to minimize clock skew.
altera corporation 11?15 may 2007 stratix ii device handbook, volume 2 high-speed board layout guidelines 1 if possible, you should avoid us ing stubs in your pcb design. for high-speed designs, even very short stubs can create signal integrity problems. figure 11?14. daisy chain routing with stubs figures 11?15 through 11?17 show the spice simula tion with different stub length. as the stub length decrea ses, there is less reflection noise, which causes the eye opening to increase. figure 11?15. stub length = 0.5 inch figure 11?16. stub length = 0.25 inch device 1 device 2 clock source m a in bu s s t u b t er min at ion r es i st o r de vi ce pin (bga b a ll)
11?16 altera corporation stratix ii device handbook, volume 2 may 2007 routing schemes for minimizing crosstalk & maintaining signal integrity figure 11?17. stub length = zero inches daisy chain routing without stubs figure 11?18 shows daisy chain routing with the main bus running through the device pins, eliminating stubs. this layout removes the risk of impedance mismatch between the main bus and the stubs, minimizing signal integrity problems. figure 11?18. daisy chain r outing without stubs star routing in star routing, the clock signal travel s to all the devices at the same time (see figure 11?19 ). therefore, all trace leng ths between the clock source and devices must be matched to mini mize the clock skew. each load should be identical to minimize signal integrity problems. in star routing, you must match the impedance of the ma in bus with the impedance of the long trace that connec ts to multiple devices. device 1 device 2 clock source t er min at ion r es i st o r m a in bu s de vi ce pin (bga b a ll)
altera corporation 11?17 may 2007 stratix ii device handbook, volume 2 high-speed board layout guidelines figure 11?19. star routing serpentine routing when a design requires equal-leng th traces between the source and multiple loads, you can bend some traces to match trace lengths (see figure 11?20 ). however, improper trace bending affects signal integrity and propagation delay. to mini mize crosstalk, ensure that s ? 3 ? h , where s is the spacing between the parallel sections and h is the height of the signal trace above the reference ground plane (see figure 11?21 ). device 1 clock source m a in bu s device 2 t er min at ion r es i st o r device 3 de vi ce pin (bga b a ll)
11?18 altera corporation stratix ii device handbook, volume 2 may 2007 routing schemes for minimizing crosstalk & maintaining signal integrity figure 11?20. serpentine routing 1 altera recommends avoiding serp entine routing, if possible. instead, use arcs to create equal-length traces. differential trace routing to maximize signal integrity, proper routing techniques for differential signals are important for high-speed designs. figure 11?21 shows two differential pairs using the microstrip layout. figure 11?21. differential trace routing note (1) note to figure 11?21 : (1) d = distance between two differential pair signals; w = width of a trace in a differential pair; s = distance between the trace in a differential pair; and h = dielectric height above the group plane. use the following guidelines when using two differential pairs: keep the distance between the differential traces ( s ) constant over the entire trace length. clock source t er min at ion r es i st o r t er min at ion r es i st o r s device 1 device 2 w w d s w w s dielectric material gn d h
altera corporation 11?19 may 2007 stratix ii device handbook, volume 2 high-speed board layout guidelines ensure that d > 2 s to minimize the crosstalk between the two differential pairs. place the differential traces s = 3 h as they leave the device to minimize reflection noise. keep the length of the two differential traces the same to minimize the skew and phase difference. avoid using multiple vias because they can cause impedance mismatch and inductance. termination schemes mismatched impedance causes signals to reflect back and forth along the lines, which causes ringing at the lo ad receiver. the ringing reduces the dynamic range of the receiver and can cause false triggering. to eliminate reflections, the impedance of the source (z s ) must equal the impedance of the trace (z o ), as well as the impedance of the load (z l ). this section discusses the following signal termination schemes: simple parallel termination thevenin parallel termination active parallel termination series-rc parallel termination series termination differential pair termination simple parallel termination in a simple parallel termination scheme, the termination resistor (r t ) is equal to the line impedance. place the r t as close to the load as possible to be efficient (see figure 11?22 ). figure 11?22. simple parallel termination the stub length from the r t to the receiver pin and pads should be as small as possible. a long stub length causes reflections from the receiver pads, resulting in signal degradation. if your design requires a long termination line between the termina tor and receiver, the placement of the resistor becomes important. for long termination line lengths, use fly-by termination (see figure 11?23 ). z o = 50 r t = z o sl s t u b s = source l = load
11?20 altera corporation stratix ii device handbook, volume 2 may 2007 termination schemes figure 11?23. simple parallel fly-by termination thevenin parallel termination an alternative parallel termination scheme uses a thevenin voltage divider (see figure 11?24 ). the r t is split between r 1 and r 2 , which equals the line impedance when combined. figure 11?24. thevenin parallel termination as noted in the previous section, stub length is dependen t on signal rise and fall time and should be kept to a minimum. if your design requires a long termination line between the te rminator and receiver, use fly-by termination or thevenin fly-by termination (see figures 11?23 and 11?25 ). z o = 50 r t = z o receiver / load p ad source z o = 50 r 2 r 1 r 1 r 2 = z o s l v cc s t u b
altera corporation 11?21 may 2007 stratix ii device handbook, volume 2 high-speed board layout guidelines figure 11?25. thevenin parallel fly-by termination active parallel termination figure 11?26 shows an active parallel termination scheme, where the terminating resistor (r t =z o ) is tied to a bias voltage (v bias ). in this scheme, the voltage is selected so that the output drivers can draw current from the high- and low-level signals. however, this scheme requires a separate voltage source that can sink and source currents to match the output transfer rates. figure 11?26. active para llel termination z o = 50 r 2 r 1 v cc r eceiver/load p ad source z o = 50 r t = z o s l v bias s t u b
11?22 altera corporation stratix ii device handbook, volume 2 may 2007 termination schemes figure 11?27 shows the active parallel fly-by termination scheme. figure 11?27. active parallel fly-by termination series-rc parallel termination a series-rc parallel termination sche me uses a resistor and capacitor (series-rc) network as the terminating impedance. r t is equal to z 0 . the capacitor must be large enough to filter the constant flow of dc current. for data patterns with long strings of 1 or 0, this termination scheme may delay the signal beyond the design th resholds, depending on the size of the capacitor. capacitors smaller than 100 pf diminish the effectiveness of termination. the capacitor blocks low-frequency si gnals while passing high-frequency signals. therefore, the dc loading effect of r t does not have an impact on the driver, as there is no dc path to ground. the series-rc termination scheme requires balanced dc signaling, the signals spend half the time on and half the time off. ac terminatio n is typically used if there is more than one load (see figure 11?28 ). figure 11?28. series-rc parallel termination z o = 50 r t = z o v bias r ece iv er /lo ad p ad source z o = 50 r t = z o c s l s t u b
altera corporation 11?23 may 2007 stratix ii device handbook, volume 2 high-speed board layout guidelines figure 11?29 shows series-rc parallel fly-by termination. figure 11?29. series-rc paralle l fly-by termination series termination in a series termination scheme, the resistor matc hes the impedance at the signal source instead of matching the impedance at each load (see figure 11?30 ). stratix ii devices have programmable output impedance. you can choose output impedance to match the line impedance without adding an external series resistor. the sum of r t and the impedance of the output driver should be equal to z 0 . because altera device output impedance is low, you should add a se ries resistor to match the signal source to the line impeda nce. the advantage of seri es termination is that it consumes little power. however, the disadvantage is that the rise time degrades because of the increased rc time constant. therefore, for high-speed designs, you should perf orm the pre-layout signal integrity simulation with altera i/o buffer in formation specification (ibis) models before using the series termination scheme. figure 11?30. series termination differential pair termination differential signal i/o standards require an r t between the signals at the receiving device (see figure 11?31 ). for the low-voltage differential signal (lvds) and low-voltage positive emitter-coupled logic (lvpecl) standard, the r t should match the differential load impedance of the bus (typically 100 ? ). z o = 50 s receiver/ load r t = z o c p ad z 0 = 50 r t sl
11?24 altera corporation stratix ii device handbook, volume 2 may 2007 simultaneous switching noise figure 11?31. differential pair (l vds & lvpecl) termination figure 11?32 shows the differential pair fl y-by termination scheme for the lvds and lvpecl standard. figure 11?32. differential pair (lvds & lvpecl) fly-by termination f see the board design guidelines for lvds systems white paper for more information on terminating differential signals. simultaneous switching noise as digital devices become faster, their output switching times decrease. this causes higher transient currents in outputs as the devices discharge load capacitances. these higher transi ent currents result in a board-level phenomenon known as ground bounce. because many factors contribute to ground bounce, you cannot use a standard test method to predict it s magnitude for all possible pcb environments. you can only test the device under a given set of conditions to determine the relative contributions of each condition and of the device itself. load capacitance, socket inductance, and the number of switching outputs are the predom inant factors that influence the magnitude of ground bounce in fpgas. altera requires 0.01- to 0.1- ? f surface-mount capacitors in parallel to reduce ground bounce. add an additional 0.001- ? f capacitor in parallel to these capacitors to filter high -frequency noise (> 100 mhz). you can also add 0.0047- ? f and 0.047- ? f capacitors. z 0 = 50 z 0 = 50 100 s l s t u b s t u b z 0 = 50 z 0 = 50 100 s p ads receiver/load + ?
altera corporation 11?25 may 2007 stratix ii device handbook, volume 2 high-speed board layout guidelines altera recommends that you take the following action to reduce ground bounce and v cc sag: configure unused i/o pins as output pins, and drive the output low to reduce ground bounce. this configuration will act as a virtual ground. connect the output pin to gnd on your board. configure the unused i/o pins as output, and drive high to prevent v cc sag. connect the output pin to v ccio of that i/o bank. create a programmable ground or v cc next to switching pins. reduce the number of outputs that can switch simultaneously and distribute them evenly throughout the device. manually assign ground pins in between i/o pins. (separating i/o pins with ground pins prevents ground bounce.) set the programmable drive strength feature with a weaker drive strength setting to slow down the edge rate. eliminate sockets whenever possible. sockets have inductance associated with them. depending on the problem, move sw itching outputs close to either a package ground or vcc pin. eliminate pull-up resistors, or use pull-down resistors. use multi-layer pcbs that provide separate v cc and ground planes to utilize the intrinsic capacitance of the v cc /gnd plane. create synchronous designs that are not affected by momentarily switching pins. add the recommended decoupling capacitors to v cc /gnd pairs. place the decoupling capacitors as close as possible to the power and ground pins of the device. connect the capacitor pad to the power and ground plane with larger vias to minimize the inductance in decoupling capacitors and allow for maximum current flow. use wide, short traces between the vias and capacitor pads, or place the via adjacent to the capacitor pad (see figure 11?33 ). figure 11?33. suggested via location that connects to capacitor pad via adjacent to capacitor pad via capacitor pads wide and short trac e
11?26 altera corporation stratix ii device handbook, volume 2 may 2007 simultaneous switching noise traces stretching from power pins to a power plane (or island, or a decoupling capacitor) should be as wide and as short as possible. this reduces series inductance, thereby reducing transient voltage drops from the power plane to the power pin which, in turn, decreases the possibility of ground bounce. use surface-mount low effective series resistance (esr) capacitors to minimize the lead inductance. the capacitors should have an esr value as small as possible. connect each ground pin or via to the ground plane individually. a daisy chain connection to the grou nd pins shares the ground path, which increases the return curr ent loop and thus inductance. power filtering & distribution you can reduce system noise by providing clean, evenly distributed power to v cc on all boards and devices. this section describes techniques for distributing and filtering power. filtering noise to decrease the low-frequency (< 1 khz) noise caused by the power supply, filter the noise on power lines at the point where the power connects to the pcb and to each device. place a 100- ? f electrolytic capacitor where the power supply li nes enter the pcb. if you use a voltage regulator, place the capacitor immediately after the pin that provides the vcc signal to the device(s). ca pacitors not only filter low-frequency noise from the power supply, but also supply extra current when many outputs switch simultaneously in a circuit. to filter power supply noise, use a non-resonant, surface-mount ferrite bead large enough to handle the curr ent in series with the power supply. place a 10- to 100- ? f bypass capacitor next to the ferrite bead (see figure 11?34 ). (if proper termination, layout, and filtering eliminate enough noise, you do not need to use a ferrite bead.) the ferrite bead acts as a short for high-frequency noise coming from the v cc source. any low-frequency noise is filtered by a large 10- ? f capacitor after the ferrite bead.
altera corporation 11?27 may 2007 stratix ii device handbook, volume 2 high-speed board layout guidelines figure 11?34. filtering noise with a ferrite bead usually, elements on the pcb add high-frequency noise to the power plane. to filter the high-frequency no ise at the device, place decoupling capacitors as close as possible to each v cc and gnd pair. f see the operating requirements for altera devices data sheet for more information on bypass capacitors. power distribution a system can distribute power thro ughout the pcb with either power planes or a power bus network. you can use power planes on multi-layer pcbs that consist of two or more metal layers that carry v cc and gnd to the devices. because the power plane covers the full area of the pcb, its dc resistance is very low. the power plane maintains v cc and distributes it equally to all devices while providing very high current-sink capability, noise protection, and shielding for the logic signals on the pcb. altera recommends using power planes to distribute power. the power bus network?which consists of two or more wide-metal traces that carry v cc and gnd to devices?is often used on two-layer pcbs and is less expensive than power planes. when designing with power bus networks, be sure to keep th e trace widths as wide as possible. the main drawback to using power bus networks is significant dc resistance. altera recommends using separate an alog and digital power planes. for fully digital systems that do not al ready have a separate analog power plane, it can be expensive to add new power planes. however, you can create partitioned islands (split planes). figure 11?35 shows an example board layout with phase-locked loop (pll) ground islands. v cc source ferrite bead v cc 10 f
11?28 altera corporation stratix ii device handbook, volume 2 may 2007 electromagnetic interference (emi) figure 11?35. board layout for gener al-purpose pll ground islands if your system shares the same plane between analog and digital power supplies, there may be unwanted interaction between the two circuit types. the following suggestions will reduce noise: for equal power distribution, use separate power planes for the analog (pll) power supply. avoid using trace or multiple signal layers to route the pll power supply. use a ground plane ne xt to the pll power supply plane to reduce power-generated noise. place analog and digital componen ts only over their respective ground planes. use ferrite beads to isolate the pll power supply from digital power supply. electromagnetic interference (emi) electromagnetic interferen ce (emi) is directly proportional to the change in current or voltage with respec t to time. emi is also directly proportional to the series inductance of the circuit. every pcb generates emi. precautions such as minimizing crosstalk, proper grounding, and proper layer stack-up signif icantly reduce emi problems. place each signal layer in between the ground plane and power (or ground) plane. inductance is direct ly proportional to the distance an electric charge has to cover from th e source of an electric charge to ground. as the distance gets shorte r, the inductance becomes smaller. p ower and ground gap width at least 25 to 100 m ils altera device analog g round p lane co mm on g round are a digital g round p lane pcb
altera corporation 11?29 may 2007 stratix ii device handbook, volume 2 high-speed board layout guidelines therefore, placing ground planes close to a signal source reduces inductance and helps contain emi. figure 11?36 shows an example of an eight-layer stack-up. in the stack-up, the stripline signal layers are the quietest because they are centered by power and gnd planes. a solid ground plane next to the power plane creates a set of low esr capacitors. with integrated circuit edge rates becoming faster and faster, these techniques help to contain emi. figure 11?36. example eight-layer stack-up component selection and proper plac ement on the board is important to controlling emi. the following guidelines can reduce emi: select low-inductance components, such as surface mount capacitors with low esr, and effective series inductance. use proper grounding for the shortest current return path. use solid ground planes next to power planes. in unavoidable circumstances, use respective ground planes next to each segmented power plane for analog and digital circuits. additional fpga-specific information this section provides the following additional information recommended by altera for board design and signal integrity: fpga-specific configuration, joint test action group (jtag) testing, and permanent test points. configuration the dclk signal is used in configuration devices and passive serial (ps) and passive parallel synchronous (p ps) configuration schemes. this signal drives edge-triggered pins in altera devices. therefore, any overshoot, undershoot, ringing, cros stalk, or other noise can affect configuration. use the same guidelin es for designing clock signals to signal ground ground ground signal signal signal power
11?30 altera corporation stratix ii device handbook, volume 2 may 2007 summary route the dclk trace (see the ?signal trace routing? section). if your design uses more than five config uration devices, altera recommends using buffers to split the fan-out on the dclk signal. jtag as pcbs become more complex, testing becomes increasingly important. advances in surface mount packaging and pcb manufacturing have resulted in smaller boards, making traditional test methods such as external test probes and ?bed-of-nails? test fixtures harder to implement. as a result, cost savings from pcb space reductions can be offset by cost increases in traditional testing methods. in addition to boundary scan testing (bst), you can use the ieee std. 1149.1 controller for in-system prog ramming. jtag consists of four required pins, test data input ( tdi ), test data output ( tdo ), test mode select ( tms ), and test clock input ( tck ) as well as an optional test reset input ( trst ) pin. use the same guidelines for la ying out clock signals to route tck traces. use multiple devices for long jtag sc an chains. minimize the jtag scan chain trace length that connects one device?s tdo pins to another device?s tdi pins to reduce delay. f see application note 39: ieee 1149.1 (jtag) boundary-scan testing in altera devices for additional details on bst. test point as device package pin density increa ses, it becomes more difficult to attach an oscilloscope or a logic analyzer probe on the device pin. using a physical probe directly on to the device pin can damage the device. if the ball grid array (bga) or fineline bga ? package is mounted on top of the board, it is difficult to probe the other side of the board. therefore, the pcb must have a permanent test po int to probe. the test point can be a via that connects to the signal under test with a very short stub. however, placing a via on a trace for a signal under test can cause reflection and poor signal integrity. summary you must carefully plan out a successful high-speed pcb. factors such as noise generation, signal reflection, crosstalk, and ground bounce can interfere with a signal, especially with the high speeds that altera devices transmit and receive. the signal routing, termination schemes, and power distribution techniques discussed in this chapter contribute to a more effectively designed pcb usin g high-speed altera devices.
altera corporation 11?31 may 2007 stratix ii device handbook, volume 2 high-speed board layout guidelines references johnson, h. w., and graham, m., ? high-speed digital design.? prentice hall, 1993. hall, s. h., hall, g. w., and mccall j. a., ?high-speed digital system design.? john wiley & sons, inc. 2000. document revision history table 11?3 shows the revision history for this chapter. table 11?3. document revision history date and document version changes made summary of changes may 2007, v1.4 updated ?simultaneous switching noise? section. ? moved the document revision history section to the end of the chapter. ? december 2005, v1.3 minor content update. ? march 2005, v1.2 minor content updates. ? january 2005, v1.1 this chapter was formally chapter 12. ? february 2004, v1.0 added document to the stratix ii device handbook. ?
11?32 altera corporation stratix ii device handbook, volume 2 may 2007 document revision history

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